@samitouri / QOSamiQemu
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1 /*
2 * QEMU model of the Xilinx Versal CANFD device.
3 *
4 * This implementation is based on the following datasheet:
5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
6 *
7 * Copyright (c) 2023 Advanced Micro Devices, Inc.
8 *
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
10 *
11 * Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and
12 * Pavel Pisa
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a copy
15 * of this software and associated documentation files (the "Software"), to deal
16 * in the Software without restriction, including without limitation the rights
17 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
18 * copies of the Software, and to permit persons to whom the Software is
19 * furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice shall be included in
22 * all copies or substantial portions of the Software.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
29 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * THE SOFTWARE.
31 */
32
33 #include "qemu/osdep.h"
34 #include "hw/core/sysbus.h"
35 #include "hw/core/irq.h"
36 #include "hw/core/register.h"
37 #include "qapi/error.h"
38 #include "qemu/log.h"
39 #include "hw/core/qdev-properties.h"
40 #include "migration/vmstate.h"
41 #include "hw/net/xlnx-versal-canfd.h"
42 #include "trace.h"
43
44 REG32(SOFTWARE_RESET_REGISTER, 0x0)
45 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
46 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
47 REG32(MODE_SELECT_REGISTER, 0x4)
48 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
49 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
50 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
51 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
52 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
53 FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1)
54 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
55 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
56 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
57 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
58 FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
59 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
60 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 16, 7)
61 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 8, 7)
62 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8)
63 REG32(ERROR_COUNTER_REGISTER, 0x10)
64 FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
65 FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
66 REG32(ERROR_STATUS_REGISTER, 0x14)
67 FIELD(ERROR_STATUS_REGISTER, F_BERR, 11, 1)
68 FIELD(ERROR_STATUS_REGISTER, F_STER, 10, 1)
69 FIELD(ERROR_STATUS_REGISTER, F_FMER, 9, 1)
70 FIELD(ERROR_STATUS_REGISTER, F_CRCER, 8, 1)
71 FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
72 FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
73 FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
74 FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
75 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
76 REG32(STATUS_REGISTER, 0x18)
77 FIELD(STATUS_REGISTER, TDCV, 16, 7)
78 FIELD(STATUS_REGISTER, SNOOP, 12, 1)
79 FIELD(STATUS_REGISTER, BSFR_CONFIG, 10, 1)
80 FIELD(STATUS_REGISTER, PEE_CONFIG, 9, 1)
81 FIELD(STATUS_REGISTER, ESTAT, 7, 2)
82 FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
83 FIELD(STATUS_REGISTER, BBSY, 5, 1)
84 FIELD(STATUS_REGISTER, BIDLE, 4, 1)
85 FIELD(STATUS_REGISTER, NORMAL, 3, 1)
86 FIELD(STATUS_REGISTER, SLEEP, 2, 1)
87 FIELD(STATUS_REGISTER, LBACK, 1, 1)
88 FIELD(STATUS_REGISTER, CONFIG, 0, 1)
89 REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
90 FIELD(INTERRUPT_STATUS_REGISTER, TXEWMFLL, 31, 1)
91 FIELD(INTERRUPT_STATUS_REGISTER, TXEOFLW, 30, 1)
92 FIELD(INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 24, 6)
93 FIELD(INTERRUPT_STATUS_REGISTER, RXLRM_BI, 18, 6)
94 FIELD(INTERRUPT_STATUS_REGISTER, RXMNF, 17, 1)
95 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 16, 1)
96 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 15, 1)
97 FIELD(INTERRUPT_STATUS_REGISTER, TXCRS, 14, 1)
98 FIELD(INTERRUPT_STATUS_REGISTER, TXRRS, 13, 1)
99 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
100 FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
101 FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
102 FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
103 /*
104 * In the original HW description below bit is named as ERROR but an ERROR
105 * field name collides with a macro in Windows build. To avoid Windows build
106 * failures, the bit is renamed to ERROR_BIT.
107 */
108 FIELD(INTERRUPT_STATUS_REGISTER, ERROR_BIT, 8, 1)
109 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW, 6, 1)
110 FIELD(INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 5, 1)
111 FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
112 FIELD(INTERRUPT_STATUS_REGISTER, BSFRD, 3, 1)
113 FIELD(INTERRUPT_STATUS_REGISTER, PEE, 2, 1)
114 FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
115 FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
116 REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
117 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEWMFLL, 31, 1)
118 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEOFLW, 30, 1)
119 FIELD(INTERRUPT_ENABLE_REGISTER, ERXMNF, 17, 1)
120 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL_1, 16, 1)
121 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFOFLW_1, 15, 1)
122 FIELD(INTERRUPT_ENABLE_REGISTER, ETXCRS, 14, 1)
123 FIELD(INTERRUPT_ENABLE_REGISTER, ETXRRS, 13, 1)
124 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
125 FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
126 FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
127 FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
128 FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
129 FIELD(INTERRUPT_ENABLE_REGISTER, ERFXOFLW, 6, 1)
130 FIELD(INTERRUPT_ENABLE_REGISTER, ETSCNT_OFLW, 5, 1)
131 FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
132 FIELD(INTERRUPT_ENABLE_REGISTER, EBSFRD, 3, 1)
133 FIELD(INTERRUPT_ENABLE_REGISTER, EPEE, 2, 1)
134 FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
135 FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1)
136 REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
137 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEWMFLL, 31, 1)
138 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEOFLW, 30, 1)
139 FIELD(INTERRUPT_CLEAR_REGISTER, CRXMNF, 17, 1)
140 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL_1, 16, 1)
141 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFOFLW_1, 15, 1)
142 FIELD(INTERRUPT_CLEAR_REGISTER, CTXCRS, 14, 1)
143 FIELD(INTERRUPT_CLEAR_REGISTER, CTXRRS, 13, 1)
144 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
145 FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
146 FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
147 FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
148 FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
149 FIELD(INTERRUPT_CLEAR_REGISTER, CRFXOFLW, 6, 1)
150 FIELD(INTERRUPT_CLEAR_REGISTER, CTSCNT_OFLW, 5, 1)
151 FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
152 FIELD(INTERRUPT_CLEAR_REGISTER, CBSFRD, 3, 1)
153 FIELD(INTERRUPT_CLEAR_REGISTER, CPEE, 2, 1)
154 FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
155 FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1)
156 REG32(TIMESTAMP_REGISTER, 0x28)
157 FIELD(TIMESTAMP_REGISTER, TIMESTAMP_CNT, 16, 16)
158 FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
159 REG32(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x88)
160 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDC, 16, 1)
161 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDCOFF, 8, 6)
162 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, DP_BRP, 0, 8)
163 REG32(DATA_PHASE_BIT_TIMING_REGISTER, 0x8c)
164 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_SJW, 16, 4)
165 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS2, 8, 4)
166 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS1, 0, 5)
167 REG32(TX_BUFFER_READY_REQUEST_REGISTER, 0x90)
168 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR31, 31, 1)
169 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR30, 30, 1)
170 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR29, 29, 1)
171 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR28, 28, 1)
172 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR27, 27, 1)
173 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR26, 26, 1)
174 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR25, 25, 1)
175 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1)
176 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR23, 23, 1)
177 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR22, 22, 1)
178 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR21, 21, 1)
179 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR20, 20, 1)
180 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR19, 19, 1)
181 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR18, 18, 1)
182 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR17, 17, 1)
183 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR16, 16, 1)
184 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR15, 15, 1)
185 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR14, 14, 1)
186 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR13, 13, 1)
187 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR12, 12, 1)
188 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR11, 11, 1)
189 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR10, 10, 1)
190 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR9, 9, 1)
191 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR8, 8, 1)
192 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR7, 7, 1)
193 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR6, 6, 1)
194 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR5, 5, 1)
195 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR4, 4, 1)
196 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR3, 3, 1)
197 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR2, 2, 1)
198 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR1, 1, 1)
199 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1)
200 REG32(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 0x94)
201 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS31, 31, 1)
202 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS30, 30, 1)
203 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS29, 29, 1)
204 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS28, 28, 1)
205 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS27, 27, 1)
206 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS26, 26, 1)
207 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS25, 25, 1)
208 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1)
209 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS23, 23, 1)
210 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS22, 22, 1)
211 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS21, 21, 1)
212 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS20, 20, 1)
213 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS19, 19, 1)
214 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS18, 18, 1)
215 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS17, 17, 1)
216 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS16, 16, 1)
217 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS15, 15, 1)
218 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS14, 14, 1)
219 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS13, 13, 1)
220 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS12, 12, 1)
221 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS11, 11, 1)
222 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS10, 10, 1)
223 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS9, 9, 1)
224 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS8, 8, 1)
225 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS7, 7, 1)
226 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS6, 6, 1)
227 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS5, 5, 1)
228 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS4, 4, 1)
229 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS3, 3, 1)
230 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS2, 2, 1)
231 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS1, 1, 1)
232 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1)
233 REG32(TX_BUFFER_CANCEL_REQUEST_REGISTER, 0x98)
234 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR31, 31, 1)
235 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR30, 30, 1)
236 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR29, 29, 1)
237 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR28, 28, 1)
238 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR27, 27, 1)
239 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR26, 26, 1)
240 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR25, 25, 1)
241 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1)
242 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR23, 23, 1)
243 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR22, 22, 1)
244 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR21, 21, 1)
245 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR20, 20, 1)
246 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR19, 19, 1)
247 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR18, 18, 1)
248 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR17, 17, 1)
249 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR16, 16, 1)
250 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR15, 15, 1)
251 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR14, 14, 1)
252 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR13, 13, 1)
253 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR12, 12, 1)
254 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR11, 11, 1)
255 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR10, 10, 1)
256 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR9, 9, 1)
257 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR8, 8, 1)
258 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR7, 7, 1)
259 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR6, 6, 1)
260 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR5, 5, 1)
261 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR4, 4, 1)
262 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR3, 3, 1)
263 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR2, 2, 1)
264 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1)
265 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1)
266 REG32(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 0x9c)
267 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS31, 31,
268 1)
269 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS30, 30,
270 1)
271 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS29, 29,
272 1)
273 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS28, 28,
274 1)
275 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS27, 27,
276 1)
277 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS26, 26,
278 1)
279 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS25, 25,
280 1)
281 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS24, 24,
282 1)
283 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS23, 23,
284 1)
285 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS22, 22,
286 1)
287 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS21, 21,
288 1)
289 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS20, 20,
290 1)
291 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS19, 19,
292 1)
293 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS18, 18,
294 1)
295 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS17, 17,
296 1)
297 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS16, 16,
298 1)
299 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS15, 15,
300 1)
301 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS14, 14,
302 1)
303 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS13, 13,
304 1)
305 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS12, 12,
306 1)
307 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS11, 11,
308 1)
309 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS10, 10,
310 1)
311 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS9, 9, 1)
312 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS8, 8, 1)
313 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS7, 7, 1)
314 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS6, 6, 1)
315 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS5, 5, 1)
316 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS4, 4, 1)
317 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS3, 3, 1)
318 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS2, 2, 1)
319 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS1, 1, 1)
320 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1)
321 REG32(TX_EVENT_FIFO_STATUS_REGISTER, 0xa0)
322 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 8, 6)
323 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI, 7, 1)
324 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 0, 5)
325 REG32(TX_EVENT_FIFO_WATERMARK_REGISTER, 0xa4)
326 FIELD(TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM, 0, 5)
327 REG32(ACCEPTANCE_FILTER_CONTROL_REGISTER, 0xe0)
328 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF31, 31, 1)
329 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF30, 30, 1)
330 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF29, 29, 1)
331 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF28, 28, 1)
332 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF27, 27, 1)
333 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF26, 26, 1)
334 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF25, 25, 1)
335 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1)
336 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF23, 23, 1)
337 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF22, 22, 1)
338 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF21, 21, 1)
339 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF20, 20, 1)
340 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF19, 19, 1)
341 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF18, 18, 1)
342 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF17, 17, 1)
343 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF16, 16, 1)
344 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF15, 15, 1)
345 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF14, 14, 1)
346 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF13, 13, 1)
347 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF12, 12, 1)
348 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF11, 11, 1)
349 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF10, 10, 1)
350 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF9, 9, 1)
351 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF8, 8, 1)
352 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF7, 7, 1)
353 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF6, 6, 1)
354 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF5, 5, 1)
355 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF4, 4, 1)
356 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF3, 3, 1)
357 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF2, 2, 1)
358 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF1, 1, 1)
359 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1)
360 REG32(RX_FIFO_STATUS_REGISTER, 0xe8)
361 FIELD(RX_FIFO_STATUS_REGISTER, FL_1, 24, 7)
362 FIELD(RX_FIFO_STATUS_REGISTER, IRI_1, 23, 1)
363 FIELD(RX_FIFO_STATUS_REGISTER, RI_1, 16, 6)
364 FIELD(RX_FIFO_STATUS_REGISTER, FL, 8, 7)
365 FIELD(RX_FIFO_STATUS_REGISTER, IRI, 7, 1)
366 FIELD(RX_FIFO_STATUS_REGISTER, RI, 0, 6)
367 REG32(RX_FIFO_WATERMARK_REGISTER, 0xec)
368 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFP, 16, 5)
369 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM_1, 8, 6)
370 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM, 0, 6)
371 REG32(TB_ID_REGISTER, 0x100)
372 FIELD(TB_ID_REGISTER, ID, 21, 11)
373 FIELD(TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
374 FIELD(TB_ID_REGISTER, IDE, 19, 1)
375 FIELD(TB_ID_REGISTER, ID_EXT, 1, 18)
376 FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1)
377 REG32(TB0_DLC_REGISTER, 0x104)
378 FIELD(TB0_DLC_REGISTER, DLC, 28, 4)
379 FIELD(TB0_DLC_REGISTER, FDF, 27, 1)
380 FIELD(TB0_DLC_REGISTER, BRS, 26, 1)
381 FIELD(TB0_DLC_REGISTER, RSVD2, 25, 1)
382 FIELD(TB0_DLC_REGISTER, EFC, 24, 1)
383 FIELD(TB0_DLC_REGISTER, MM, 16, 8)
384 FIELD(TB0_DLC_REGISTER, RSVD1, 0, 16)
385 REG32(TB_DW0_REGISTER, 0x108)
386 FIELD(TB_DW0_REGISTER, DATA_BYTES0, 24, 8)
387 FIELD(TB_DW0_REGISTER, DATA_BYTES1, 16, 8)
388 FIELD(TB_DW0_REGISTER, DATA_BYTES2, 8, 8)
389 FIELD(TB_DW0_REGISTER, DATA_BYTES3, 0, 8)
390 REG32(TB_DW1_REGISTER, 0x10c)
391 FIELD(TB_DW1_REGISTER, DATA_BYTES4, 24, 8)
392 FIELD(TB_DW1_REGISTER, DATA_BYTES5, 16, 8)
393 FIELD(TB_DW1_REGISTER, DATA_BYTES6, 8, 8)
394 FIELD(TB_DW1_REGISTER, DATA_BYTES7, 0, 8)
395 REG32(TB_DW2_REGISTER, 0x110)
396 FIELD(TB_DW2_REGISTER, DATA_BYTES8, 24, 8)
397 FIELD(TB_DW2_REGISTER, DATA_BYTES9, 16, 8)
398 FIELD(TB_DW2_REGISTER, DATA_BYTES10, 8, 8)
399 FIELD(TB_DW2_REGISTER, DATA_BYTES11, 0, 8)
400 REG32(TB_DW3_REGISTER, 0x114)
401 FIELD(TB_DW3_REGISTER, DATA_BYTES12, 24, 8)
402 FIELD(TB_DW3_REGISTER, DATA_BYTES13, 16, 8)
403 FIELD(TB_DW3_REGISTER, DATA_BYTES14, 8, 8)
404 FIELD(TB_DW3_REGISTER, DATA_BYTES15, 0, 8)
405 REG32(TB_DW4_REGISTER, 0x118)
406 FIELD(TB_DW4_REGISTER, DATA_BYTES16, 24, 8)
407 FIELD(TB_DW4_REGISTER, DATA_BYTES17, 16, 8)
408 FIELD(TB_DW4_REGISTER, DATA_BYTES18, 8, 8)
409 FIELD(TB_DW4_REGISTER, DATA_BYTES19, 0, 8)
410 REG32(TB_DW5_REGISTER, 0x11c)
411 FIELD(TB_DW5_REGISTER, DATA_BYTES20, 24, 8)
412 FIELD(TB_DW5_REGISTER, DATA_BYTES21, 16, 8)
413 FIELD(TB_DW5_REGISTER, DATA_BYTES22, 8, 8)
414 FIELD(TB_DW5_REGISTER, DATA_BYTES23, 0, 8)
415 REG32(TB_DW6_REGISTER, 0x120)
416 FIELD(TB_DW6_REGISTER, DATA_BYTES24, 24, 8)
417 FIELD(TB_DW6_REGISTER, DATA_BYTES25, 16, 8)
418 FIELD(TB_DW6_REGISTER, DATA_BYTES26, 8, 8)
419 FIELD(TB_DW6_REGISTER, DATA_BYTES27, 0, 8)
420 REG32(TB_DW7_REGISTER, 0x124)
421 FIELD(TB_DW7_REGISTER, DATA_BYTES28, 24, 8)
422 FIELD(TB_DW7_REGISTER, DATA_BYTES29, 16, 8)
423 FIELD(TB_DW7_REGISTER, DATA_BYTES30, 8, 8)
424 FIELD(TB_DW7_REGISTER, DATA_BYTES31, 0, 8)
425 REG32(TB_DW8_REGISTER, 0x128)
426 FIELD(TB_DW8_REGISTER, DATA_BYTES32, 24, 8)
427 FIELD(TB_DW8_REGISTER, DATA_BYTES33, 16, 8)
428 FIELD(TB_DW8_REGISTER, DATA_BYTES34, 8, 8)
429 FIELD(TB_DW8_REGISTER, DATA_BYTES35, 0, 8)
430 REG32(TB_DW9_REGISTER, 0x12c)
431 FIELD(TB_DW9_REGISTER, DATA_BYTES36, 24, 8)
432 FIELD(TB_DW9_REGISTER, DATA_BYTES37, 16, 8)
433 FIELD(TB_DW9_REGISTER, DATA_BYTES38, 8, 8)
434 FIELD(TB_DW9_REGISTER, DATA_BYTES39, 0, 8)
435 REG32(TB_DW10_REGISTER, 0x130)
436 FIELD(TB_DW10_REGISTER, DATA_BYTES40, 24, 8)
437 FIELD(TB_DW10_REGISTER, DATA_BYTES41, 16, 8)
438 FIELD(TB_DW10_REGISTER, DATA_BYTES42, 8, 8)
439 FIELD(TB_DW10_REGISTER, DATA_BYTES43, 0, 8)
440 REG32(TB_DW11_REGISTER, 0x134)
441 FIELD(TB_DW11_REGISTER, DATA_BYTES44, 24, 8)
442 FIELD(TB_DW11_REGISTER, DATA_BYTES45, 16, 8)
443 FIELD(TB_DW11_REGISTER, DATA_BYTES46, 8, 8)
444 FIELD(TB_DW11_REGISTER, DATA_BYTES47, 0, 8)
445 REG32(TB_DW12_REGISTER, 0x138)
446 FIELD(TB_DW12_REGISTER, DATA_BYTES48, 24, 8)
447 FIELD(TB_DW12_REGISTER, DATA_BYTES49, 16, 8)
448 FIELD(TB_DW12_REGISTER, DATA_BYTES50, 8, 8)
449 FIELD(TB_DW12_REGISTER, DATA_BYTES51, 0, 8)
450 REG32(TB_DW13_REGISTER, 0x13c)
451 FIELD(TB_DW13_REGISTER, DATA_BYTES52, 24, 8)
452 FIELD(TB_DW13_REGISTER, DATA_BYTES53, 16, 8)
453 FIELD(TB_DW13_REGISTER, DATA_BYTES54, 8, 8)
454 FIELD(TB_DW13_REGISTER, DATA_BYTES55, 0, 8)
455 REG32(TB_DW14_REGISTER, 0x140)
456 FIELD(TB_DW14_REGISTER, DATA_BYTES56, 24, 8)
457 FIELD(TB_DW14_REGISTER, DATA_BYTES57, 16, 8)
458 FIELD(TB_DW14_REGISTER, DATA_BYTES58, 8, 8)
459 FIELD(TB_DW14_REGISTER, DATA_BYTES59, 0, 8)
460 REG32(TB_DW15_REGISTER, 0x144)
461 FIELD(TB_DW15_REGISTER, DATA_BYTES60, 24, 8)
462 FIELD(TB_DW15_REGISTER, DATA_BYTES61, 16, 8)
463 FIELD(TB_DW15_REGISTER, DATA_BYTES62, 8, 8)
464 FIELD(TB_DW15_REGISTER, DATA_BYTES63, 0, 8)
465 REG32(AFMR_REGISTER, 0xa00)
466 FIELD(AFMR_REGISTER, AMID, 21, 11)
467 FIELD(AFMR_REGISTER, AMSRR, 20, 1)
468 FIELD(AFMR_REGISTER, AMIDE, 19, 1)
469 FIELD(AFMR_REGISTER, AMID_EXT, 1, 18)
470 FIELD(AFMR_REGISTER, AMRTR, 0, 1)
471 REG32(AFIR_REGISTER, 0xa04)
472 FIELD(AFIR_REGISTER, AIID, 21, 11)
473 FIELD(AFIR_REGISTER, AISRR, 20, 1)
474 FIELD(AFIR_REGISTER, AIIDE, 19, 1)
475 FIELD(AFIR_REGISTER, AIID_EXT, 1, 18)
476 FIELD(AFIR_REGISTER, AIRTR, 0, 1)
477 REG32(TXE_FIFO_TB_ID_REGISTER, 0x2000)
478 FIELD(TXE_FIFO_TB_ID_REGISTER, ID, 21, 11)
479 FIELD(TXE_FIFO_TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
480 FIELD(TXE_FIFO_TB_ID_REGISTER, IDE, 19, 1)
481 FIELD(TXE_FIFO_TB_ID_REGISTER, ID_EXT, 1, 18)
482 FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1)
483 REG32(TXE_FIFO_TB_DLC_REGISTER, 0x2004)
484 FIELD(TXE_FIFO_TB_DLC_REGISTER, DLC, 28, 4)
485 FIELD(TXE_FIFO_TB_DLC_REGISTER, FDF, 27, 1)
486 FIELD(TXE_FIFO_TB_DLC_REGISTER, BRS, 26, 1)
487 FIELD(TXE_FIFO_TB_DLC_REGISTER, ET, 24, 2)
488 FIELD(TXE_FIFO_TB_DLC_REGISTER, MM, 16, 8)
489 FIELD(TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 0, 16)
490 REG32(RB_ID_REGISTER, 0x2100)
491 FIELD(RB_ID_REGISTER, ID, 21, 11)
492 FIELD(RB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
493 FIELD(RB_ID_REGISTER, IDE, 19, 1)
494 FIELD(RB_ID_REGISTER, ID_EXT, 1, 18)
495 FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1)
496 REG32(RB_DLC_REGISTER, 0x2104)
497 FIELD(RB_DLC_REGISTER, DLC, 28, 4)
498 FIELD(RB_DLC_REGISTER, FDF, 27, 1)
499 FIELD(RB_DLC_REGISTER, BRS, 26, 1)
500 FIELD(RB_DLC_REGISTER, ESI, 25, 1)
501 FIELD(RB_DLC_REGISTER, MATCHED_FILTER_INDEX, 16, 5)
502 FIELD(RB_DLC_REGISTER, TIMESTAMP, 0, 16)
503 REG32(RB_DW0_REGISTER, 0x2108)
504 FIELD(RB_DW0_REGISTER, DATA_BYTES0, 24, 8)
505 FIELD(RB_DW0_REGISTER, DATA_BYTES1, 16, 8)
506 FIELD(RB_DW0_REGISTER, DATA_BYTES2, 8, 8)
507 FIELD(RB_DW0_REGISTER, DATA_BYTES3, 0, 8)
508 REG32(RB_DW1_REGISTER, 0x210c)
509 FIELD(RB_DW1_REGISTER, DATA_BYTES4, 24, 8)
510 FIELD(RB_DW1_REGISTER, DATA_BYTES5, 16, 8)
511 FIELD(RB_DW1_REGISTER, DATA_BYTES6, 8, 8)
512 FIELD(RB_DW1_REGISTER, DATA_BYTES7, 0, 8)
513 REG32(RB_DW2_REGISTER, 0x2110)
514 FIELD(RB_DW2_REGISTER, DATA_BYTES8, 24, 8)
515 FIELD(RB_DW2_REGISTER, DATA_BYTES9, 16, 8)
516 FIELD(RB_DW2_REGISTER, DATA_BYTES10, 8, 8)
517 FIELD(RB_DW2_REGISTER, DATA_BYTES11, 0, 8)
518 REG32(RB_DW3_REGISTER, 0x2114)
519 FIELD(RB_DW3_REGISTER, DATA_BYTES12, 24, 8)
520 FIELD(RB_DW3_REGISTER, DATA_BYTES13, 16, 8)
521 FIELD(RB_DW3_REGISTER, DATA_BYTES14, 8, 8)
522 FIELD(RB_DW3_REGISTER, DATA_BYTES15, 0, 8)
523 REG32(RB_DW4_REGISTER, 0x2118)
524 FIELD(RB_DW4_REGISTER, DATA_BYTES16, 24, 8)
525 FIELD(RB_DW4_REGISTER, DATA_BYTES17, 16, 8)
526 FIELD(RB_DW4_REGISTER, DATA_BYTES18, 8, 8)
527 FIELD(RB_DW4_REGISTER, DATA_BYTES19, 0, 8)
528 REG32(RB_DW5_REGISTER, 0x211c)
529 FIELD(RB_DW5_REGISTER, DATA_BYTES20, 24, 8)
530 FIELD(RB_DW5_REGISTER, DATA_BYTES21, 16, 8)
531 FIELD(RB_DW5_REGISTER, DATA_BYTES22, 8, 8)
532 FIELD(RB_DW5_REGISTER, DATA_BYTES23, 0, 8)
533 REG32(RB_DW6_REGISTER, 0x2120)
534 FIELD(RB_DW6_REGISTER, DATA_BYTES24, 24, 8)
535 FIELD(RB_DW6_REGISTER, DATA_BYTES25, 16, 8)
536 FIELD(RB_DW6_REGISTER, DATA_BYTES26, 8, 8)
537 FIELD(RB_DW6_REGISTER, DATA_BYTES27, 0, 8)
538 REG32(RB_DW7_REGISTER, 0x2124)
539 FIELD(RB_DW7_REGISTER, DATA_BYTES28, 24, 8)
540 FIELD(RB_DW7_REGISTER, DATA_BYTES29, 16, 8)
541 FIELD(RB_DW7_REGISTER, DATA_BYTES30, 8, 8)
542 FIELD(RB_DW7_REGISTER, DATA_BYTES31, 0, 8)
543 REG32(RB_DW8_REGISTER, 0x2128)
544 FIELD(RB_DW8_REGISTER, DATA_BYTES32, 24, 8)
545 FIELD(RB_DW8_REGISTER, DATA_BYTES33, 16, 8)
546 FIELD(RB_DW8_REGISTER, DATA_BYTES34, 8, 8)
547 FIELD(RB_DW8_REGISTER, DATA_BYTES35, 0, 8)
548 REG32(RB_DW9_REGISTER, 0x212c)
549 FIELD(RB_DW9_REGISTER, DATA_BYTES36, 24, 8)
550 FIELD(RB_DW9_REGISTER, DATA_BYTES37, 16, 8)
551 FIELD(RB_DW9_REGISTER, DATA_BYTES38, 8, 8)
552 FIELD(RB_DW9_REGISTER, DATA_BYTES39, 0, 8)
553 REG32(RB_DW10_REGISTER, 0x2130)
554 FIELD(RB_DW10_REGISTER, DATA_BYTES40, 24, 8)
555 FIELD(RB_DW10_REGISTER, DATA_BYTES41, 16, 8)
556 FIELD(RB_DW10_REGISTER, DATA_BYTES42, 8, 8)
557 FIELD(RB_DW10_REGISTER, DATA_BYTES43, 0, 8)
558 REG32(RB_DW11_REGISTER, 0x2134)
559 FIELD(RB_DW11_REGISTER, DATA_BYTES44, 24, 8)
560 FIELD(RB_DW11_REGISTER, DATA_BYTES45, 16, 8)
561 FIELD(RB_DW11_REGISTER, DATA_BYTES46, 8, 8)
562 FIELD(RB_DW11_REGISTER, DATA_BYTES47, 0, 8)
563 REG32(RB_DW12_REGISTER, 0x2138)
564 FIELD(RB_DW12_REGISTER, DATA_BYTES48, 24, 8)
565 FIELD(RB_DW12_REGISTER, DATA_BYTES49, 16, 8)
566 FIELD(RB_DW12_REGISTER, DATA_BYTES50, 8, 8)
567 FIELD(RB_DW12_REGISTER, DATA_BYTES51, 0, 8)
568 REG32(RB_DW13_REGISTER, 0x213c)
569 FIELD(RB_DW13_REGISTER, DATA_BYTES52, 24, 8)
570 FIELD(RB_DW13_REGISTER, DATA_BYTES53, 16, 8)
571 FIELD(RB_DW13_REGISTER, DATA_BYTES54, 8, 8)
572 FIELD(RB_DW13_REGISTER, DATA_BYTES55, 0, 8)
573 REG32(RB_DW14_REGISTER, 0x2140)
574 FIELD(RB_DW14_REGISTER, DATA_BYTES56, 24, 8)
575 FIELD(RB_DW14_REGISTER, DATA_BYTES57, 16, 8)
576 FIELD(RB_DW14_REGISTER, DATA_BYTES58, 8, 8)
577 FIELD(RB_DW14_REGISTER, DATA_BYTES59, 0, 8)
578 REG32(RB_DW15_REGISTER, 0x2144)
579 FIELD(RB_DW15_REGISTER, DATA_BYTES60, 24, 8)
580 FIELD(RB_DW15_REGISTER, DATA_BYTES61, 16, 8)
581 FIELD(RB_DW15_REGISTER, DATA_BYTES62, 8, 8)
582 FIELD(RB_DW15_REGISTER, DATA_BYTES63, 0, 8)
583 REG32(RB_ID_REGISTER_1, 0x4100)
584 FIELD(RB_ID_REGISTER_1, ID, 21, 11)
585 FIELD(RB_ID_REGISTER_1, SRR_RTR_RRS, 20, 1)
586 FIELD(RB_ID_REGISTER_1, IDE, 19, 1)
587 FIELD(RB_ID_REGISTER_1, ID_EXT, 1, 18)
588 FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1)
589 REG32(RB_DLC_REGISTER_1, 0x4104)
590 FIELD(RB_DLC_REGISTER_1, DLC, 28, 4)
591 FIELD(RB_DLC_REGISTER_1, FDF, 27, 1)
592 FIELD(RB_DLC_REGISTER_1, BRS, 26, 1)
593 FIELD(RB_DLC_REGISTER_1, ESI, 25, 1)
594 FIELD(RB_DLC_REGISTER_1, MATCHED_FILTER_INDEX, 16, 5)
595 FIELD(RB_DLC_REGISTER_1, TIMESTAMP, 0, 16)
596 REG32(RB0_DW0_REGISTER_1, 0x4108)
597 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES0, 24, 8)
598 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES1, 16, 8)
599 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES2, 8, 8)
600 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES3, 0, 8)
601 REG32(RB_DW1_REGISTER_1, 0x410c)
602 FIELD(RB_DW1_REGISTER_1, DATA_BYTES4, 24, 8)
603 FIELD(RB_DW1_REGISTER_1, DATA_BYTES5, 16, 8)
604 FIELD(RB_DW1_REGISTER_1, DATA_BYTES6, 8, 8)
605 FIELD(RB_DW1_REGISTER_1, DATA_BYTES7, 0, 8)
606 REG32(RB_DW2_REGISTER_1, 0x4110)
607 FIELD(RB_DW2_REGISTER_1, DATA_BYTES8, 24, 8)
608 FIELD(RB_DW2_REGISTER_1, DATA_BYTES9, 16, 8)
609 FIELD(RB_DW2_REGISTER_1, DATA_BYTES10, 8, 8)
610 FIELD(RB_DW2_REGISTER_1, DATA_BYTES11, 0, 8)
611 REG32(RB_DW3_REGISTER_1, 0x4114)
612 FIELD(RB_DW3_REGISTER_1, DATA_BYTES12, 24, 8)
613 FIELD(RB_DW3_REGISTER_1, DATA_BYTES13, 16, 8)
614 FIELD(RB_DW3_REGISTER_1, DATA_BYTES14, 8, 8)
615 FIELD(RB_DW3_REGISTER_1, DATA_BYTES15, 0, 8)
616 REG32(RB_DW4_REGISTER_1, 0x4118)
617 FIELD(RB_DW4_REGISTER_1, DATA_BYTES16, 24, 8)
618 FIELD(RB_DW4_REGISTER_1, DATA_BYTES17, 16, 8)
619 FIELD(RB_DW4_REGISTER_1, DATA_BYTES18, 8, 8)
620 FIELD(RB_DW4_REGISTER_1, DATA_BYTES19, 0, 8)
621 REG32(RB_DW5_REGISTER_1, 0x411c)
622 FIELD(RB_DW5_REGISTER_1, DATA_BYTES20, 24, 8)
623 FIELD(RB_DW5_REGISTER_1, DATA_BYTES21, 16, 8)
624 FIELD(RB_DW5_REGISTER_1, DATA_BYTES22, 8, 8)
625 FIELD(RB_DW5_REGISTER_1, DATA_BYTES23, 0, 8)
626 REG32(RB_DW6_REGISTER_1, 0x4120)
627 FIELD(RB_DW6_REGISTER_1, DATA_BYTES24, 24, 8)
628 FIELD(RB_DW6_REGISTER_1, DATA_BYTES25, 16, 8)
629 FIELD(RB_DW6_REGISTER_1, DATA_BYTES26, 8, 8)
630 FIELD(RB_DW6_REGISTER_1, DATA_BYTES27, 0, 8)
631 REG32(RB_DW7_REGISTER_1, 0x4124)
632 FIELD(RB_DW7_REGISTER_1, DATA_BYTES28, 24, 8)
633 FIELD(RB_DW7_REGISTER_1, DATA_BYTES29, 16, 8)
634 FIELD(RB_DW7_REGISTER_1, DATA_BYTES30, 8, 8)
635 FIELD(RB_DW7_REGISTER_1, DATA_BYTES31, 0, 8)
636 REG32(RB_DW8_REGISTER_1, 0x4128)
637 FIELD(RB_DW8_REGISTER_1, DATA_BYTES32, 24, 8)
638 FIELD(RB_DW8_REGISTER_1, DATA_BYTES33, 16, 8)
639 FIELD(RB_DW8_REGISTER_1, DATA_BYTES34, 8, 8)
640 FIELD(RB_DW8_REGISTER_1, DATA_BYTES35, 0, 8)
641 REG32(RB_DW9_REGISTER_1, 0x412c)
642 FIELD(RB_DW9_REGISTER_1, DATA_BYTES36, 24, 8)
643 FIELD(RB_DW9_REGISTER_1, DATA_BYTES37, 16, 8)
644 FIELD(RB_DW9_REGISTER_1, DATA_BYTES38, 8, 8)
645 FIELD(RB_DW9_REGISTER_1, DATA_BYTES39, 0, 8)
646 REG32(RB_DW10_REGISTER_1, 0x4130)
647 FIELD(RB_DW10_REGISTER_1, DATA_BYTES40, 24, 8)
648 FIELD(RB_DW10_REGISTER_1, DATA_BYTES41, 16, 8)
649 FIELD(RB_DW10_REGISTER_1, DATA_BYTES42, 8, 8)
650 FIELD(RB_DW10_REGISTER_1, DATA_BYTES43, 0, 8)
651 REG32(RB_DW11_REGISTER_1, 0x4134)
652 FIELD(RB_DW11_REGISTER_1, DATA_BYTES44, 24, 8)
653 FIELD(RB_DW11_REGISTER_1, DATA_BYTES45, 16, 8)
654 FIELD(RB_DW11_REGISTER_1, DATA_BYTES46, 8, 8)
655 FIELD(RB_DW11_REGISTER_1, DATA_BYTES47, 0, 8)
656 REG32(RB_DW12_REGISTER_1, 0x4138)
657 FIELD(RB_DW12_REGISTER_1, DATA_BYTES48, 24, 8)
658 FIELD(RB_DW12_REGISTER_1, DATA_BYTES49, 16, 8)
659 FIELD(RB_DW12_REGISTER_1, DATA_BYTES50, 8, 8)
660 FIELD(RB_DW12_REGISTER_1, DATA_BYTES51, 0, 8)
661 REG32(RB_DW13_REGISTER_1, 0x413c)
662 FIELD(RB_DW13_REGISTER_1, DATA_BYTES52, 24, 8)
663 FIELD(RB_DW13_REGISTER_1, DATA_BYTES53, 16, 8)
664 FIELD(RB_DW13_REGISTER_1, DATA_BYTES54, 8, 8)
665 FIELD(RB_DW13_REGISTER_1, DATA_BYTES55, 0, 8)
666 REG32(RB_DW14_REGISTER_1, 0x4140)
667 FIELD(RB_DW14_REGISTER_1, DATA_BYTES56, 24, 8)
668 FIELD(RB_DW14_REGISTER_1, DATA_BYTES57, 16, 8)
669 FIELD(RB_DW14_REGISTER_1, DATA_BYTES58, 8, 8)
670 FIELD(RB_DW14_REGISTER_1, DATA_BYTES59, 0, 8)
671 REG32(RB_DW15_REGISTER_1, 0x4144)
672 FIELD(RB_DW15_REGISTER_1, DATA_BYTES60, 24, 8)
673 FIELD(RB_DW15_REGISTER_1, DATA_BYTES61, 16, 8)
674 FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8)
675 FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8)
676
677 static void canfd_update_irq(XlnxVersalCANFDState *s)
678 {
679 const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] &
680 s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0;
681 g_autofree char *path = object_get_canonical_path(OBJECT(s));
682
683 /* RX watermark interrupts. */
684 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) >
685 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) {
686 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
687 }
688
689 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) >
690 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) {
691 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1);
692 }
693
694 /* TX watermark interrupt. */
695 if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) >
696 ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) {
697 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1);
698 }
699
700 trace_xlnx_canfd_update_irq(path, s->regs[R_INTERRUPT_STATUS_REGISTER],
701 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
702
703 qemu_set_irq(s->irq_canfd_int, irq);
704 }
705
706 static void canfd_ier_post_write(RegisterInfo *reg, uint64_t val64)
707 {
708 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
709
710 canfd_update_irq(s);
711 }
712
713 static uint64_t canfd_icr_pre_write(RegisterInfo *reg, uint64_t val64)
714 {
715 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
716 uint32_t val = val64;
717
718 s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
719
720 /*
721 * RXBOFLW_BI field is automatically cleared to default if RXBOFLW bit is
722 * cleared in ISR.
723 */
724 if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) {
725 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0);
726 }
727
728 canfd_update_irq(s);
729
730 return 0;
731 }
732
733 static void canfd_config_reset(XlnxVersalCANFDState *s)
734 {
735
736 unsigned int i;
737
738 /* Reset all the configuration registers. */
739 for (i = 0; i < R_RX_FIFO_WATERMARK_REGISTER; ++i) {
740 register_reset(&s->reg_info[i]);
741 }
742
743 canfd_update_irq(s);
744 }
745
746 static void canfd_config_mode(XlnxVersalCANFDState *s)
747 {
748 register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
749 register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
750 register_reset(&s->reg_info[R_STATUS_REGISTER]);
751
752 /* Put XlnxVersalCANFDState in configuration mode. */
753 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
754 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
755 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
756 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
757 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0);
758 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0);
759 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0);
760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
763
764 /* Clear the time stamp. */
765 ptimer_transaction_begin(s->canfd_timer);
766 ptimer_set_count(s->canfd_timer, 0);
767 ptimer_transaction_commit(s->canfd_timer);
768
769 canfd_update_irq(s);
770 }
771
772 static void update_status_register_mode_bits(XlnxVersalCANFDState *s)
773 {
774 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
775 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
776 /* Wake up interrupt bit. */
777 bool wakeup_irq_val = !sleep_mode && sleep_status;
778 /* Sleep interrupt bit. */
779 bool sleep_irq_val = sleep_mode && !sleep_status;
780
781 /* Clear previous core mode status bits. */
782 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
783 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
784 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
785 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
786
787 /* set current mode bit and generate irqs accordingly. */
788 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
790 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
791 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
792 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
793 sleep_irq_val);
794 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
795 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
796 } else {
797 /* If all bits are zero, XlnxVersalCANFDState is set in normal mode. */
798 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
799 /* Set wakeup interrupt bit. */
800 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
801 wakeup_irq_val);
802 }
803
804 /* Put the CANFD in error active state. */
805 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1);
806
807 canfd_update_irq(s);
808 }
809
810 static uint64_t canfd_msr_pre_write(RegisterInfo *reg, uint64_t val64)
811 {
812 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
813 uint32_t val = val64;
814 uint8_t multi_mode = 0;
815
816 /*
817 * Multiple mode set check. This is done to make sure user doesn't set
818 * multiple modes.
819 */
820 multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
821 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
822 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
823
824 if (multi_mode > 1) {
825 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to configure several modes"
826 " simultaneously. One mode will be selected according to"
827 " their priority: LBACK > SLEEP > SNOOP.\n");
828 }
829
830 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
831 /* In configuration mode, any mode can be selected. */
832 s->regs[R_MODE_SELECT_REGISTER] = val;
833 } else {
834 bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
835
836 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
837
838 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
839 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set LBACK mode"
840 " without setting CEN bit as 0\n");
841 } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
842 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set SNOOP mode"
843 " without setting CEN bit as 0\n");
844 }
845
846 update_status_register_mode_bits(s);
847 }
848
849 return s->regs[R_MODE_SELECT_REGISTER];
850 }
851
852 static void canfd_exit_sleep_mode(XlnxVersalCANFDState *s)
853 {
854 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
855 update_status_register_mode_bits(s);
856 }
857
858 static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
859 uint32_t reg_num)
860 {
861 uint32_t i = 0;
862 uint32_t j = 0;
863 uint32_t val = 0;
864 uint32_t dlc_reg_val = 0;
865 uint32_t dlc_value = 0;
866 uint32_t id_reg_val = 0;
867 bool is_rtr = false;
868
869 frame->flags = 0;
870
871 /* Check that reg_num should be within TX register space. */
872 assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE *
873 s->cfg.tx_fifo));
874
875 dlc_reg_val = s->regs[reg_num + 1];
876 dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC);
877
878 id_reg_val = s->regs[reg_num];
879 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, IDE)) {
880 frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) |
881 (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID_EXT)) |
882 QEMU_CAN_EFF_FLAG;
883 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, RTR_RRS)) {
884 is_rtr = true;
885 }
886 } else {
887 frame->can_id = FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID);
888 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, SRR_RTR_RRS)) {
889 is_rtr = true;
890 }
891 }
892
893 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) {
894 frame->flags |= QEMU_CAN_FRMF_TYPE_FD;
895
896 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) {
897 frame->flags |= QEMU_CAN_FRMF_BRS;
898 }
899 } else {
900 if (is_rtr) {
901 frame->can_id |= QEMU_CAN_RTR_FLAG;
902 }
903 }
904
905 frame->can_dlc = can_dlc2len(dlc_value);
906
907 for (j = 0; j < frame->can_dlc; j++) {
908 val = 8 * (3 - i);
909
910 frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8);
911 i++;
912
913 if (i % 4 == 0) {
914 i = 0;
915 }
916 }
917 }
918
919 static void process_cancellation_requests(XlnxVersalCANFDState *s)
920 {
921 uint32_t clear_mask = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &
922 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER];
923
924 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &= ~clear_mask;
925 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] &= ~clear_mask;
926
927 canfd_update_irq(s);
928 }
929
930 static uint32_t frame_to_reg_id(const qemu_can_frame *frame)
931 {
932 uint32_t id_reg_val = 0;
933 const bool is_canfd_frame = frame->flags & QEMU_CAN_FRMF_TYPE_FD;
934 const bool is_rtr = !is_canfd_frame && (frame->can_id & QEMU_CAN_RTR_FLAG);
935
936 if (frame->can_id & QEMU_CAN_EFF_FLAG) {
937 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID,
938 (frame->can_id & QEMU_CAN_EFF_MASK) >> 18);
939 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT,
940 frame->can_id & QEMU_CAN_EFF_MASK);
941 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1);
942 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1);
943 if (is_rtr) {
944 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1);
945 }
946 } else {
947 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID,
948 frame->can_id & QEMU_CAN_SFF_MASK);
949 if (is_rtr) {
950 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1);
951 }
952 }
953
954 return id_reg_val;
955 }
956
957 static void store_rx_sequential(XlnxVersalCANFDState *s,
958 const qemu_can_frame *frame,
959 uint32_t fill_level, uint32_t read_index,
960 uint32_t store_location, uint8_t rx_fifo,
961 bool rx_fifo_id, uint8_t filter_index)
962 {
963 int i;
964 uint8_t dlc = frame->can_dlc;
965 uint8_t rx_reg_num = 0;
966 uint32_t dlc_reg_val = 0;
967 uint32_t data_reg_val = 0;
968
969 /* Getting RX0/1 fill level */
970 if ((fill_level) > rx_fifo - 1) {
971 g_autofree char *path = object_get_canonical_path(OBJECT(s));
972
973 qemu_log_mask(LOG_GUEST_ERROR, "%s: RX%d Buffer is full. Discarding the"
974 " message\n", path, rx_fifo_id);
975
976 /* Set the corresponding RF buffer overflow interrupt. */
977 if (rx_fifo_id == 0) {
978 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 1);
979 } else {
980 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 1);
981 }
982 } else {
983 uint16_t rx_timestamp = CANFD_TIMER_MAX -
984 ptimer_get_count(s->canfd_timer);
985
986 if (rx_timestamp == 0xFFFF) {
987 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 1);
988 } else {
989 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT,
990 rx_timestamp);
991 }
992
993 if (rx_fifo_id == 0) {
994 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL,
995 fill_level + 1);
996 assert(store_location <=
997 R_RB_ID_REGISTER + (s->cfg.rx0_fifo *
998 NUM_REGS_PER_MSG_SPACE));
999 } else {
1000 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1,
1001 fill_level + 1);
1002 assert(store_location <=
1003 R_RB_ID_REGISTER_1 + (s->cfg.rx1_fifo *
1004 NUM_REGS_PER_MSG_SPACE));
1005 }
1006
1007 s->regs[store_location] = frame_to_reg_id(frame);
1008
1009 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc));
1010
1011 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) {
1012 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1);
1013
1014 if (frame->flags & QEMU_CAN_FRMF_BRS) {
1015 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1);
1016 }
1017 if (frame->flags & QEMU_CAN_FRMF_ESI) {
1018 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1);
1019 }
1020 }
1021
1022 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp);
1023 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX,
1024 filter_index);
1025 s->regs[store_location + 1] = dlc_reg_val;
1026
1027 for (i = 0; i < dlc; i++) {
1028 /* Register size is 4 byte but frame->data each is 1 byte. */
1029 switch (i % 4) {
1030 case 0:
1031 rx_reg_num = i / 4;
1032
1033 data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0,
1034 frame->data[i]);
1035 break;
1036 case 1:
1037 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1,
1038 frame->data[i]);
1039 break;
1040 case 2:
1041 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2,
1042 frame->data[i]);
1043 break;
1044 case 3:
1045 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3,
1046 frame->data[i]);
1047 /*
1048 * Last Bytes data which means we have all 4 bytes ready to
1049 * store in one rx regs.
1050 */
1051 s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1052 break;
1053 }
1054 }
1055
1056 if (i % 4) {
1057 /*
1058 * In case DLC is not multiplier of 4, data is not saved to RX FIFO
1059 * in above switch case. Store the remaining bytes here.
1060 */
1061 s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1062 }
1063
1064 /* set the interrupt as RXOK. */
1065 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1066 }
1067 }
1068
1069 static void update_rx_sequential(XlnxVersalCANFDState *s,
1070 const qemu_can_frame *frame)
1071 {
1072 bool filter_pass = false;
1073 uint8_t filter_index = 0;
1074 int i;
1075 int filter_partition = ARRAY_FIELD_EX32(s->regs,
1076 RX_FIFO_WATERMARK_REGISTER, RXFP);
1077 uint32_t store_location;
1078 uint32_t fill_level;
1079 uint32_t read_index;
1080 uint8_t store_index = 0;
1081 g_autofree char *path = NULL;
1082 /*
1083 * If all UAF bits are set to 0, then received messages are not stored
1084 * in the RX buffers.
1085 */
1086 if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) {
1087 uint32_t acceptance_filter_status =
1088 s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER];
1089 const uint32_t reg_id = frame_to_reg_id(frame);
1090
1091 for (i = 0; i < 32; i++) {
1092 if (acceptance_filter_status & 0x1) {
1093 uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] &
1094 reg_id;
1095 uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] &
1096 s->regs[R_AFMR_REGISTER + 2 * i];
1097 uint16_t std_msg_id_masked = FIELD_EX32(msg_id_masked,
1098 AFIR_REGISTER, AIID);
1099 uint16_t std_afir_id_masked = FIELD_EX32(afir_id_masked,
1100 AFIR_REGISTER, AIID);
1101 uint32_t ext_msg_id_masked = FIELD_EX32(msg_id_masked,
1102 AFIR_REGISTER,
1103 AIID_EXT);
1104 uint32_t ext_afir_id_masked = FIELD_EX32(afir_id_masked,
1105 AFIR_REGISTER,
1106 AIID_EXT);
1107 bool ext_ide = FIELD_EX32(s->regs[R_AFMR_REGISTER + 2 * i],
1108 AFMR_REGISTER, AMIDE);
1109
1110 if (std_msg_id_masked == std_afir_id_masked) {
1111 if (ext_ide) {
1112 /* Extended message ID message. */
1113 if (ext_msg_id_masked == ext_afir_id_masked) {
1114 filter_pass = true;
1115 filter_index = i;
1116
1117 break;
1118 }
1119 } else {
1120 /* Standard message ID. */
1121 filter_pass = true;
1122 filter_index = i;
1123
1124 break;
1125 }
1126 }
1127 }
1128 acceptance_filter_status >>= 1;
1129 }
1130 }
1131
1132 if (!filter_pass) {
1133 path = object_get_canonical_path(OBJECT(s));
1134
1135 trace_xlnx_canfd_rx_fifo_filter_reject(path, frame->can_id,
1136 frame->can_dlc);
1137 } else {
1138 if (filter_index <= filter_partition) {
1139 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL);
1140 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI);
1141 store_index = read_index + fill_level;
1142
1143 if (store_index > s->cfg.rx0_fifo - 1) {
1144 store_index -= s->cfg.rx0_fifo;
1145 }
1146
1147 store_location = R_RB_ID_REGISTER +
1148 (store_index * NUM_REGS_PER_MSG_SPACE);
1149
1150 store_rx_sequential(s, frame, fill_level, read_index,
1151 store_location, s->cfg.rx0_fifo, 0,
1152 filter_index);
1153 } else {
1154 /* RX 1 fill level message */
1155 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1156 FL_1);
1157 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1158 RI_1);
1159 store_index = read_index + fill_level;
1160
1161 if (store_index > s->cfg.rx1_fifo - 1) {
1162 store_index -= s->cfg.rx1_fifo;
1163 }
1164
1165 store_location = R_RB_ID_REGISTER_1 +
1166 (store_index * NUM_REGS_PER_MSG_SPACE);
1167
1168 store_rx_sequential(s, frame, fill_level, read_index,
1169 store_location, s->cfg.rx1_fifo, 1,
1170 filter_index);
1171 }
1172
1173 path = object_get_canonical_path(OBJECT(s));
1174
1175 trace_xlnx_canfd_rx_data(path, frame->can_id, frame->can_dlc,
1176 frame->flags);
1177 canfd_update_irq(s);
1178 }
1179 }
1180
1181 static bool tx_ready_check(XlnxVersalCANFDState *s)
1182 {
1183 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
1184 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1185
1186 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1187 " XlnxVersalCANFDState is in reset mode\n", path);
1188
1189 return false;
1190 }
1191
1192 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1193 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1194
1195 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1196 " XlnxVersalCANFDState is in configuration mode."
1197 " Reset the core so operations can start fresh\n",
1198 path);
1199 return false;
1200 }
1201
1202 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1203 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1204
1205 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1206 " XlnxVersalCANFDState is in SNOOP MODE\n",
1207 path);
1208 return false;
1209 }
1210
1211 return true;
1212 }
1213
1214 static void tx_fifo_stamp(XlnxVersalCANFDState *s, uint32_t tb0_regid)
1215 {
1216 /*
1217 * If EFC bit in DLC message is set, this means we will store the
1218 * event of this transmitted message with time stamp.
1219 */
1220 uint32_t dlc_reg_val = 0;
1221
1222 if (FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, EFC)) {
1223 uint8_t dlc_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1224 DLC);
1225 bool fdf_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1226 FDF);
1227 bool brs_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1228 BRS);
1229 uint8_t mm_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1230 MM);
1231 uint8_t fill_level = ARRAY_FIELD_EX32(s->regs,
1232 TX_EVENT_FIFO_STATUS_REGISTER,
1233 TXE_FL);
1234 uint8_t read_index = ARRAY_FIELD_EX32(s->regs,
1235 TX_EVENT_FIFO_STATUS_REGISTER,
1236 TXE_RI);
1237 uint8_t store_index = fill_level + read_index;
1238
1239 if ((fill_level) > s->cfg.tx_fifo - 1) {
1240 qemu_log_mask(LOG_GUEST_ERROR, "TX Event Buffer is full."
1241 " Discarding the message\n");
1242 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1);
1243 } else {
1244 if (store_index > s->cfg.tx_fifo - 1) {
1245 store_index -= s->cfg.tx_fifo;
1246 }
1247
1248 assert(store_index < s->cfg.tx_fifo);
1249
1250 uint32_t tx_event_reg0_id = R_TXE_FIFO_TB_ID_REGISTER +
1251 (store_index * 2);
1252
1253 /* Store message ID in TX event register. */
1254 s->regs[tx_event_reg0_id] = s->regs[tb0_regid];
1255
1256 uint16_t tx_timestamp = CANFD_TIMER_MAX -
1257 ptimer_get_count(s->canfd_timer);
1258
1259 /* Store DLC with time stamp in DLC regs. */
1260 dlc_reg_val = FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, DLC, dlc_val);
1261 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, FDF,
1262 fdf_val);
1263 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, BRS,
1264 brs_val);
1265 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, ET, 0x3);
1266 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, MM, mm_val);
1267 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP,
1268 tx_timestamp);
1269 s->regs[tx_event_reg0_id + 1] = dlc_reg_val;
1270
1271 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1272 fill_level + 1);
1273 }
1274 }
1275 }
1276
1277 static gint g_cmp_ids(gconstpointer data1, gconstpointer data2, gpointer d)
1278 {
1279 tx_ready_reg_info *tx_reg_1 = (tx_ready_reg_info *) data1;
1280 tx_ready_reg_info *tx_reg_2 = (tx_ready_reg_info *) data2;
1281
1282 if (tx_reg_1->can_id == tx_reg_2->can_id) {
1283 return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1;
1284 }
1285 return (tx_reg_1->can_id < tx_reg_2->can_id) ? -1 : 1;
1286 }
1287
1288 static void free_list(GSList *list)
1289 {
1290 GSList *iterator = NULL;
1291
1292 for (iterator = list; iterator != NULL; iterator = iterator->next) {
1293 g_free((tx_ready_reg_info *)iterator->data);
1294 }
1295
1296 g_slist_free(list);
1297 }
1298
1299 static GSList *prepare_tx_data(XlnxVersalCANFDState *s)
1300 {
1301 uint8_t i = 0;
1302 GSList *list = NULL;
1303 uint32_t reg_num = 0;
1304 uint32_t reg_ready = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER];
1305
1306 /* First find the messages which are ready for transmission. */
1307 for (i = 0; i < s->cfg.tx_fifo; i++) {
1308 if (reg_ready & 1) {
1309 reg_num = R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * i);
1310 tx_ready_reg_info *temp = g_new(tx_ready_reg_info, 1);
1311
1312 temp->can_id = s->regs[reg_num];
1313 temp->reg_num = reg_num;
1314 list = g_slist_prepend(list, temp);
1315 list = g_slist_sort_with_data(list, g_cmp_ids, NULL);
1316 }
1317
1318 reg_ready >>= 1;
1319 }
1320
1321 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0;
1322 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0;
1323
1324 return list;
1325 }
1326
1327 static void transfer_data(XlnxVersalCANFDState *s)
1328 {
1329 bool canfd_tx = tx_ready_check(s);
1330 GSList *list, *iterator = NULL;
1331 qemu_can_frame frame;
1332
1333 if (!canfd_tx) {
1334 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1335
1336 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller not enabled for data"
1337 " transfer\n", path);
1338 return;
1339 }
1340
1341 list = prepare_tx_data(s);
1342 if (list == NULL) {
1343 return;
1344 }
1345
1346 for (iterator = list; iterator != NULL; iterator = iterator->next) {
1347 regs2frame(s, &frame,
1348 ((tx_ready_reg_info *)iterator->data)->reg_num);
1349
1350 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1351 update_rx_sequential(s, &frame);
1352 tx_fifo_stamp(s, ((tx_ready_reg_info *)iterator->data)->reg_num);
1353
1354 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1355 } else {
1356 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1357
1358 trace_xlnx_canfd_tx_data(path, frame.can_id, frame.can_dlc,
1359 frame.flags);
1360 can_bus_client_send(&s->bus_client, &frame, 1);
1361 tx_fifo_stamp(s,
1362 ((tx_ready_reg_info *)iterator->data)->reg_num);
1363
1364 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXRRS, 1);
1365
1366 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
1367 canfd_exit_sleep_mode(s);
1368 }
1369 }
1370 }
1371
1372 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
1373 free_list(list);
1374
1375 canfd_update_irq(s);
1376 }
1377
1378 static uint64_t canfd_srr_pre_write(RegisterInfo *reg, uint64_t val64)
1379 {
1380 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1381 uint32_t val = val64;
1382
1383 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
1384 FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
1385
1386 if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
1387 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1388
1389 trace_xlnx_canfd_reset(path, val64);
1390
1391 /* First, core will do software reset then will enter in config mode. */
1392 canfd_config_reset(s);
1393 } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1394 canfd_config_mode(s);
1395 } else {
1396 /*
1397 * Leave config mode. Now XlnxVersalCANFD core will enter Normal, Sleep,
1398 * snoop or Loopback mode depending upon LBACK, SLEEP, SNOOP register
1399 * states.
1400 */
1401 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
1402
1403 ptimer_transaction_begin(s->canfd_timer);
1404 ptimer_set_count(s->canfd_timer, 0);
1405 ptimer_transaction_commit(s->canfd_timer);
1406 update_status_register_mode_bits(s);
1407 transfer_data(s);
1408 }
1409
1410 return s->regs[R_SOFTWARE_RESET_REGISTER];
1411 }
1412
1413 static void filter_reg_write(XlnxVersalCANFDState *s, hwaddr addr,
1414 unsigned bank_idx, uint32_t val)
1415 {
1416 size_t reg_idx = addr / sizeof(uint32_t);
1417
1418 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & (1 << bank_idx))) {
1419 s->regs[reg_idx] = val;
1420 } else {
1421 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1422
1423 qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter register 0x%"
1424 HWADDR_PRIx " changed while filter %u enabled\n",
1425 path, addr, bank_idx + 1);
1426 }
1427 }
1428
1429 static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1430 {
1431 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1432 uint32_t val = val64;
1433 uint8_t read_ind = 0;
1434 uint8_t fill_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1435 TXE_FL);
1436
1437 if (FIELD_EX32(val, TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI) && fill_ind) {
1438 read_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1439 TXE_RI) + 1;
1440
1441 if (read_ind > s->cfg.tx_fifo - 1) {
1442 read_ind = 0;
1443 }
1444
1445 /*
1446 * Increase the read index by 1 and decrease the fill level by 1.
1447 */
1448 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI,
1449 read_ind);
1450 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1451 fill_ind - 1);
1452 }
1453
1454 return s->regs[R_TX_EVENT_FIFO_STATUS_REGISTER];
1455 }
1456
1457 static uint64_t canfd_rx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1458 {
1459 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1460 uint32_t val = val64;
1461 uint8_t read_ind = 0;
1462 uint8_t fill_ind = 0;
1463
1464 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI)) {
1465 /* FL index is zero, setting IRI bit has no effect. */
1466 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) {
1467 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI) + 1;
1468
1469 if (read_ind > s->cfg.rx0_fifo - 1) {
1470 read_ind = 0;
1471 }
1472
1473 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) - 1;
1474
1475 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, read_ind);
1476 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, fill_ind);
1477 }
1478 }
1479
1480 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI_1)) {
1481 /* FL_1 index is zero, setting IRI_1 bit has no effect. */
1482 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) != 0) {
1483 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI_1) + 1;
1484
1485 if (read_ind > s->cfg.rx1_fifo - 1) {
1486 read_ind = 0;
1487 }
1488
1489 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) - 1;
1490
1491 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, read_ind);
1492 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, fill_ind);
1493 }
1494 }
1495
1496 return s->regs[R_RX_FIFO_STATUS_REGISTER];
1497 }
1498
1499 static uint64_t canfd_tsr_pre_write(RegisterInfo *reg, uint64_t val64)
1500 {
1501 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1502 uint32_t val = val64;
1503
1504 if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
1505 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0);
1506 ptimer_transaction_begin(s->canfd_timer);
1507 ptimer_set_count(s->canfd_timer, 0);
1508 ptimer_transaction_commit(s->canfd_timer);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static uint64_t canfd_trr_reg_prew(RegisterInfo *reg, uint64_t val64)
1515 {
1516 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1517
1518 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1519 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1520
1521 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in SNOOP mode."
1522 " tx_ready_register will stay in reset mode\n", path);
1523 return 0;
1524 } else {
1525 return val64;
1526 }
1527 }
1528
1529 static void canfd_trr_reg_postw(RegisterInfo *reg, uint64_t val64)
1530 {
1531 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1532
1533 transfer_data(s);
1534 }
1535
1536 static void canfd_cancel_reg_postw(RegisterInfo *reg, uint64_t val64)
1537 {
1538 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1539
1540 process_cancellation_requests(s);
1541 }
1542
1543 static uint64_t canfd_write_check_prew(RegisterInfo *reg, uint64_t val64)
1544 {
1545 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1546 uint32_t val = val64;
1547
1548 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1549 return val;
1550 }
1551 return 0;
1552 }
1553
1554 static const RegisterAccessInfo canfd_regs_info[] = {
1555 { .name = "SOFTWARE_RESET_REGISTER", .addr = A_SOFTWARE_RESET_REGISTER,
1556 .pre_write = canfd_srr_pre_write,
1557 },{ .name = "MODE_SELECT_REGISTER", .addr = A_MODE_SELECT_REGISTER,
1558 .pre_write = canfd_msr_pre_write,
1559 },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1560 .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1561 .pre_write = canfd_write_check_prew,
1562 },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
1563 .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
1564 .pre_write = canfd_write_check_prew,
1565 },{ .name = "ERROR_COUNTER_REGISTER", .addr = A_ERROR_COUNTER_REGISTER,
1566 .ro = 0xffff,
1567 },{ .name = "ERROR_STATUS_REGISTER", .addr = A_ERROR_STATUS_REGISTER,
1568 .w1c = 0xf1f,
1569 },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER,
1570 .reset = 0x1,
1571 .ro = 0x7f17ff,
1572 },{ .name = "INTERRUPT_STATUS_REGISTER",
1573 .addr = A_INTERRUPT_STATUS_REGISTER,
1574 .ro = 0xffffff7f,
1575 },{ .name = "INTERRUPT_ENABLE_REGISTER",
1576 .addr = A_INTERRUPT_ENABLE_REGISTER,
1577 .post_write = canfd_ier_post_write,
1578 },{ .name = "INTERRUPT_CLEAR_REGISTER",
1579 .addr = A_INTERRUPT_CLEAR_REGISTER, .pre_write = canfd_icr_pre_write,
1580 },{ .name = "TIMESTAMP_REGISTER", .addr = A_TIMESTAMP_REGISTER,
1581 .ro = 0xffff0000,
1582 .pre_write = canfd_tsr_pre_write,
1583 },{ .name = "DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1584 .addr = A_DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1585 .pre_write = canfd_write_check_prew,
1586 },{ .name = "DATA_PHASE_BIT_TIMING_REGISTER",
1587 .addr = A_DATA_PHASE_BIT_TIMING_REGISTER,
1588 .pre_write = canfd_write_check_prew,
1589 },{ .name = "TX_BUFFER_READY_REQUEST_REGISTER",
1590 .addr = A_TX_BUFFER_READY_REQUEST_REGISTER,
1591 .pre_write = canfd_trr_reg_prew,
1592 .post_write = canfd_trr_reg_postw,
1593 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER",
1594 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER,
1595 },{ .name = "TX_BUFFER_CANCEL_REQUEST_REGISTER",
1596 .addr = A_TX_BUFFER_CANCEL_REQUEST_REGISTER,
1597 .post_write = canfd_cancel_reg_postw,
1598 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER",
1599 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER,
1600 },{ .name = "TX_EVENT_FIFO_STATUS_REGISTER",
1601 .addr = A_TX_EVENT_FIFO_STATUS_REGISTER,
1602 .ro = 0x3f1f, .pre_write = canfd_tx_fifo_status_prew,
1603 },{ .name = "TX_EVENT_FIFO_WATERMARK_REGISTER",
1604 .addr = A_TX_EVENT_FIFO_WATERMARK_REGISTER,
1605 .reset = 0xf,
1606 .pre_write = canfd_write_check_prew,
1607 },{ .name = "ACCEPTANCE_FILTER_CONTROL_REGISTER",
1608 .addr = A_ACCEPTANCE_FILTER_CONTROL_REGISTER,
1609 },{ .name = "RX_FIFO_STATUS_REGISTER", .addr = A_RX_FIFO_STATUS_REGISTER,
1610 .ro = 0x7f3f7f3f, .pre_write = canfd_rx_fifo_status_prew,
1611 },{ .name = "RX_FIFO_WATERMARK_REGISTER",
1612 .addr = A_RX_FIFO_WATERMARK_REGISTER,
1613 .reset = 0x1f0f0f,
1614 .pre_write = canfd_write_check_prew,
1615 }
1616 };
1617
1618 static void xlnx_versal_canfd_ptimer_cb(void *opaque)
1619 {
1620 /* No action required on the timer rollover. */
1621 }
1622
1623 static bool canfd_decode_reg_bank(XlnxVersalCANFDState *s, hwaddr addr,
1624 hwaddr first_reg, hwaddr last_reg,
1625 size_t num_banks, unsigned *idx,
1626 hwaddr *offset)
1627 {
1628 hwaddr base = addr - first_reg;
1629 hwaddr span = last_reg - first_reg + sizeof(uint32_t);
1630 unsigned index = base / span;
1631
1632 if (index >= num_banks) {
1633 return false;
1634 }
1635 if (idx) {
1636 *idx = index;
1637 }
1638
1639 *offset = base % span;
1640 *offset += first_reg;
1641
1642 return true;
1643 }
1644
1645 /*
1646 * Decode the given addr into a (idx, offset) pair:
1647 * - idx is the bank index of the register at addr,
1648 * - offset is the register offset relative to bank 0
1649 *
1650 * @return true is the decoding succeded, false otherwise
1651 */
1652 static bool canfd_decode_addr(XlnxVersalCANFDState *s, hwaddr addr,
1653 unsigned *idx, hwaddr *offset)
1654 {
1655 if (addr <= A_RX_FIFO_WATERMARK_REGISTER) {
1656 /* from 0x0 to 0xec. Handled by the register API */
1657 g_assert_not_reached();
1658 } else if (addr < A_TB_ID_REGISTER) {
1659 /* no register in this gap */
1660 return false;
1661 } else if (addr < A_AFMR_REGISTER) {
1662 /* TX registers */
1663 return canfd_decode_reg_bank(s, addr,
1664 A_TB_ID_REGISTER, A_TB_DW15_REGISTER,
1665 s->cfg.tx_fifo, idx, offset);
1666 } else if (addr < A_TXE_FIFO_TB_ID_REGISTER) {
1667 /* Filter registers */
1668 return canfd_decode_reg_bank(s, addr,
1669 A_AFMR_REGISTER, A_AFIR_REGISTER,
1670 32, idx, offset);
1671 } else if (addr < A_RB_ID_REGISTER) {
1672 /* TX event registers */
1673 return canfd_decode_reg_bank(s, addr,
1674 A_TXE_FIFO_TB_ID_REGISTER,
1675 A_TXE_FIFO_TB_DLC_REGISTER,
1676 32, idx, offset);
1677 } else if (addr < A_RB_ID_REGISTER_1) {
1678 /* RX0 registers */
1679 return canfd_decode_reg_bank(s, addr,
1680 A_RB_ID_REGISTER,
1681 A_RB_DW15_REGISTER,
1682 s->cfg.rx0_fifo, idx, offset);
1683 } else if (addr <= A_RB_DW15_REGISTER_1) {
1684 /* RX1 registers */
1685 return canfd_decode_reg_bank(s, addr,
1686 A_RB_ID_REGISTER_1,
1687 A_RB_DW15_REGISTER_1,
1688 s->cfg.rx1_fifo, idx, offset);
1689 }
1690
1691 /* decode error */
1692 return false;
1693 }
1694
1695 static uint64_t canfd_read(void *opaque, hwaddr addr, unsigned size)
1696 {
1697 XlnxVersalCANFDState *s = XILINX_CANFD(opaque);
1698 hwaddr reg_offset;
1699 uint64_t ret;
1700
1701 if (!canfd_decode_addr(s, addr, NULL, &reg_offset)) {
1702 qemu_log_mask(LOG_GUEST_ERROR, TYPE_XILINX_CANFD
1703 ": read to unknown register at address 0x%"
1704 HWADDR_PRIx "\n", addr);
1705 return 0;
1706 }
1707
1708 switch (reg_offset) {
1709 default:
1710 ret = s->regs[addr / sizeof(uint32_t)];
1711 }
1712
1713 return ret;
1714 }
1715
1716 static void canfd_write(void *opaque, hwaddr addr, uint64_t value,
1717 unsigned size)
1718 {
1719 XlnxVersalCANFDState *s = XILINX_CANFD(opaque);
1720 unsigned bank_idx;
1721 hwaddr reg_offset;
1722
1723 if (!canfd_decode_addr(s, addr, &bank_idx, &reg_offset)) {
1724 qemu_log_mask(LOG_GUEST_ERROR, TYPE_XILINX_CANFD
1725 ": write to unknown register at address 0x%"
1726 HWADDR_PRIx "\n", addr);
1727 return;
1728 }
1729
1730 if (addr >= A_TXE_FIFO_TB_ID_REGISTER) {
1731 /* All registers from TX event regs to the end are read-only */
1732 qemu_log_mask(LOG_GUEST_ERROR, TYPE_XILINX_CANFD
1733 ": write to read-only register at 0x%" HWADDR_PRIx "\n",
1734 addr);
1735 return;
1736 }
1737
1738 switch (reg_offset) {
1739 case A_AFMR_REGISTER:
1740 case A_AFIR_REGISTER:
1741 filter_reg_write(s, addr, bank_idx, value);
1742 break;
1743
1744 default:
1745 s->regs[addr / sizeof(uint32_t)] = value;
1746 }
1747 }
1748
1749 static const MemoryRegionOps canfd_ops = {
1750 .read = canfd_read,
1751 .write = canfd_write,
1752 .endianness = DEVICE_LITTLE_ENDIAN,
1753 .valid = {
1754 .min_access_size = 4,
1755 .max_access_size = 4,
1756 },
1757 };
1758
1759 static const MemoryRegionOps canfd_regs_ops = {
1760 .read = register_read_memory,
1761 .write = register_write_memory,
1762 .endianness = DEVICE_LITTLE_ENDIAN,
1763 .valid = {
1764 .min_access_size = 4,
1765 .max_access_size = 4,
1766 },
1767 };
1768
1769 static void canfd_reset(DeviceState *dev)
1770 {
1771 XlnxVersalCANFDState *s = XILINX_CANFD(dev);
1772 unsigned int i;
1773
1774 for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) {
1775 register_reset(&s->reg_info[i]);
1776 }
1777
1778 ptimer_transaction_begin(s->canfd_timer);
1779 ptimer_set_count(s->canfd_timer, 0);
1780 ptimer_transaction_commit(s->canfd_timer);
1781 }
1782
1783 static bool can_xilinx_canfd_receive(CanBusClientState *client)
1784 {
1785 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1786 bus_client);
1787
1788 bool reset_state = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST);
1789 bool can_enabled = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN);
1790
1791 return !reset_state && can_enabled;
1792 }
1793
1794 static ssize_t canfd_xilinx_receive(CanBusClientState *client,
1795 const qemu_can_frame *buf,
1796 size_t buf_size)
1797 {
1798 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1799 bus_client);
1800 const qemu_can_frame *frame = buf;
1801
1802 assert(buf_size > 0);
1803
1804 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1805 /*
1806 * XlnxVersalCANFDState will not participate in normal bus communication
1807 * and does not receive any messages transmitted by other CAN nodes.
1808 */
1809 return 1;
1810 }
1811
1812 /* Update the status register that we are receiving message. */
1813 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1);
1814
1815 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
1816 /* Snoop Mode: Just keep the data. no response back. */
1817 update_rx_sequential(s, frame);
1818 } else {
1819 if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
1820 /*
1821 * XlnxVersalCANFDState is in sleep mode. Any data on bus will bring
1822 * it to the wake up state.
1823 */
1824 canfd_exit_sleep_mode(s);
1825 }
1826
1827 update_rx_sequential(s, frame);
1828 }
1829
1830 /* Message processing done. Update the status back to !busy */
1831 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0);
1832 return 1;
1833 }
1834
1835 static CanBusClientInfo canfd_xilinx_bus_client_info = {
1836 .can_receive = can_xilinx_canfd_receive,
1837 .receive = canfd_xilinx_receive,
1838 };
1839
1840 static int xlnx_canfd_connect_to_bus(XlnxVersalCANFDState *s,
1841 CanBusState *bus)
1842 {
1843 s->bus_client.info = &canfd_xilinx_bus_client_info;
1844
1845 return can_bus_insert_client(bus, &s->bus_client);
1846 }
1847
1848 static void canfd_realize(DeviceState *dev, Error **errp)
1849 {
1850 XlnxVersalCANFDState *s = XILINX_CANFD(dev);
1851 RegisterInfoArray *reg_array;
1852
1853 reg_array = register_init_block32(dev, canfd_regs_info,
1854 ARRAY_SIZE(canfd_regs_info), s->reg_info,
1855 s->regs, &canfd_regs_ops, false,
1856 A_RX_FIFO_WATERMARK_REGISTER
1857 + sizeof(uint32_t));
1858 memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
1859 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1860 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int);
1861
1862 if (s->canfdbus) {
1863 if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) {
1864 g_autofree char *path = object_get_canonical_path(OBJECT(s));
1865
1866 error_setg(errp, "%s: xlnx_canfd_connect_to_bus failed", path);
1867 return;
1868 }
1869
1870 }
1871
1872 /* Allocate a new timer. */
1873 s->canfd_timer = ptimer_init(xlnx_versal_canfd_ptimer_cb, s,
1874 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
1875 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
1876 PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
1877
1878 ptimer_transaction_begin(s->canfd_timer);
1879
1880 ptimer_set_freq(s->canfd_timer, s->cfg.ext_clk_freq);
1881 ptimer_set_limit(s->canfd_timer, CANFD_TIMER_MAX, 1);
1882 ptimer_run(s->canfd_timer, 0);
1883 ptimer_transaction_commit(s->canfd_timer);
1884 }
1885
1886 static void canfd_init(Object *obj)
1887 {
1888 XlnxVersalCANFDState *s = XILINX_CANFD(obj);
1889
1890 memory_region_init_io(&s->iomem, obj, &canfd_ops, s, TYPE_XILINX_CANFD,
1891 XLNX_VERSAL_CANFD_R_MAX * 4);
1892 }
1893
1894 static const VMStateDescription vmstate_canfd = {
1895 .name = TYPE_XILINX_CANFD,
1896 .version_id = 1,
1897 .minimum_version_id = 1,
1898 .fields = (const VMStateField[]) {
1899 VMSTATE_UINT32_ARRAY(regs, XlnxVersalCANFDState,
1900 XLNX_VERSAL_CANFD_R_MAX),
1901 VMSTATE_PTIMER(canfd_timer, XlnxVersalCANFDState),
1902 VMSTATE_END_OF_LIST(),
1903 }
1904 };
1905
1906 static const Property canfd_core_properties[] = {
1907 DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40),
1908 DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40),
1909 DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20),
1910 DEFINE_PROP_BOOL("enable-rx-fifo1", XlnxVersalCANFDState,
1911 cfg.enable_rx_fifo1, true),
1912 DEFINE_PROP_UINT32("ext_clk_freq", XlnxVersalCANFDState, cfg.ext_clk_freq,
1913 CANFD_DEFAULT_CLOCK),
1914 DEFINE_PROP_LINK("canfdbus", XlnxVersalCANFDState, canfdbus, TYPE_CAN_BUS,
1915 CanBusState *),
1916 };
1917
1918 static void canfd_class_init(ObjectClass *klass, const void *data)
1919 {
1920 DeviceClass *dc = DEVICE_CLASS(klass);
1921
1922 device_class_set_legacy_reset(dc, canfd_reset);
1923 dc->realize = canfd_realize;
1924 device_class_set_props(dc, canfd_core_properties);
1925 dc->vmsd = &vmstate_canfd;
1926 }
1927
1928 static const TypeInfo canfd_info = {
1929 .name = TYPE_XILINX_CANFD,
1930 .parent = TYPE_SYS_BUS_DEVICE,
1931 .instance_size = sizeof(XlnxVersalCANFDState),
1932 .class_init = canfd_class_init,
1933 .instance_init = canfd_init,
1934 };
1935
1936 static void canfd_register_types(void)
1937 {
1938 type_register_static(&canfd_info);
1939 }
1940
1941 type_init(canfd_register_types)