e1000e_core.c · samitouri/QOSamiQemu

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1	/*
2	* Core code for QEMU e1000e emulation
3	*
4	* Software developer's manuals:
5	* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6	*
7	* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8	* Developed by Daynix Computing LTD (http://www.daynix.com)
9	*
10	* Authors:
11	* Dmitry Fleytman <dmitry@daynix.com>
12	* Leonid Bloch <leonid@daynix.com>
13	* Yan Vugenfirer <yan@daynix.com>
14	*
15	* Based on work done by:
16	* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17	* Copyright (c) 2008 Qumranet
18	* Based on work done by:
19	* Copyright (c) 2007 Dan Aloni
20	* Copyright (c) 2004 Antony T Curtis
21	*
22	* This library is free software; you can redistribute it and/or
23	* modify it under the terms of the GNU Lesser General Public
24	* License as published by the Free Software Foundation; either
25	* version 2.1 of the License, or (at your option) any later version.
26	*
27	* This library is distributed in the hope that it will be useful,
28	* but WITHOUT ANY WARRANTY; without even the implied warranty of
29	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30	* Lesser General Public License for more details.
31	*
32	* You should have received a copy of the GNU Lesser General Public
33	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
34	*/
35
36	#include "qemu/osdep.h"
37	#include "qemu/log.h"
38	#include "net/net.h"
39	#include "net/tap.h"
40	#include "hw/net/mii.h"
41	#include "hw/pci/msi.h"
42	#include "hw/pci/msix.h"
43	#include "system/runstate.h"
44
45	#include "net_tx_pkt.h"
46	#include "net_rx_pkt.h"
47
48	#include "e1000_common.h"
49	#include "e1000x_common.h"
50	#include "e1000e_core.h"
51
52	#include "trace.h"
53
54	/* No more then 7813 interrupts per second according to spec 10.2.4.2 */
55	#define E1000E_MIN_XITR (500)
56
57	#define E1000E_MAX_TX_FRAGS (64)
58
59	union e1000_rx_desc_union {
60	struct e1000_rx_desc legacy;
61	union e1000_rx_desc_extended extended;
62	union e1000_rx_desc_packet_split packet_split;
63	};
64
65	static ssize_t
66	e1000e_receive_internal(E1000ECore core, const struct iovec iov, int iovcnt,
67	bool has_vnet);
68
69	static inline void
70	e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
71
72	static void e1000e_reset(E1000ECore *core, bool sw);
73
74	static inline void
75	e1000e_process_ts_option(E1000ECore core, struct e1000_tx_desc dp)
76	{
77	if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
78	trace_e1000e_wrn_no_ts_support();
79	}
80	}
81
82	static inline void
83	e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
84	{
85	if (cmd_and_length & E1000_TXD_CMD_SNAP) {
86	trace_e1000e_wrn_no_snap_support();
87	}
88	}
89
90	static inline void
91	e1000e_raise_legacy_irq(E1000ECore *core)
92	{
93	trace_e1000e_irq_legacy_notify(true);
94	e1000x_inc_reg_if_not_full(core->mac, IAC);
95	pci_set_irq(core->owner, 1);
96	}
97
98	static inline void
99	e1000e_lower_legacy_irq(E1000ECore *core)
100	{
101	trace_e1000e_irq_legacy_notify(false);
102	pci_set_irq(core->owner, 0);
103	}
104
105	static inline void
106	e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
107	{
108	int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
109	timer->delay_resolution_ns;
110
111	trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
112
113	timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
114
115	timer->running = true;
116	}
117
118	static void
119	e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
120	{
121	if (timer->running) {
122	e1000e_intrmgr_rearm_timer(timer);
123	}
124	}
125
126	static inline void
127	e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
128	{
129	if (timer->running) {
130	timer_del(timer->timer);
131	timer->running = false;
132	}
133	}
134
135	static inline void
136	e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
137	{
138	trace_e1000e_irq_fire_delayed_interrupts();
139	e1000e_set_interrupt_cause(core, 0);
140	}
141
142	static void
143	e1000e_intrmgr_on_timer(void *opaque)
144	{
145	E1000IntrDelayTimer *timer = opaque;
146
147	trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
148
149	timer->running = false;
150	e1000e_intrmgr_fire_delayed_interrupts(timer->core);
151	}
152
153	static void
154	e1000e_intrmgr_on_throttling_timer(void *opaque)
155	{
156	E1000IntrDelayTimer *timer = opaque;
157
158	timer->running = false;
159
160	if (timer->core->mac[IMS] & timer->core->mac[ICR]) {
161	if (msi_enabled(timer->core->owner)) {
162	trace_e1000e_irq_msi_notify_postponed();
163	msi_notify(timer->core->owner, 0);
164	} else {
165	trace_e1000e_irq_legacy_notify_postponed();
166	e1000e_raise_legacy_irq(timer->core);
167	}
168	}
169	}
170
171	static void
172	e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
173	{
174	E1000IntrDelayTimer *timer = opaque;
175	int idx = timer - &timer->core->eitr[0];
176
177	timer->running = false;
178
179	trace_e1000e_irq_msix_notify_postponed_vec(idx);
180	msix_notify(timer->core->owner, idx);
181	}
182
183	static void
184	e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
185	{
186	int i;
187
188	core->radv.delay_reg = RADV;
189	core->rdtr.delay_reg = RDTR;
190	core->raid.delay_reg = RAID;
191	core->tadv.delay_reg = TADV;
192	core->tidv.delay_reg = TIDV;
193
194	core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
195	core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
196	core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
197	core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
198	core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
199
200	core->radv.core = core;
201	core->rdtr.core = core;
202	core->raid.core = core;
203	core->tadv.core = core;
204	core->tidv.core = core;
205
206	core->itr.core = core;
207	core->itr.delay_reg = ITR;
208	core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
209
210	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
211	core->eitr[i].core = core;
212	core->eitr[i].delay_reg = EITR + i;
213	core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
214	}
215
216	if (!create) {
217	return;
218	}
219
220	core->radv.timer =
221	timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
222	core->rdtr.timer =
223	timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
224	core->raid.timer =
225	timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
226
227	core->tadv.timer =
228	timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
229	core->tidv.timer =
230	timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
231
232	core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
233	e1000e_intrmgr_on_throttling_timer,
234	&core->itr);
235
236	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
237	core->eitr[i].timer =
238	timer_new_ns(QEMU_CLOCK_VIRTUAL,
239	e1000e_intrmgr_on_msix_throttling_timer,
240	&core->eitr[i]);
241	}
242	}
243
244	static inline void
245	e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
246	{
247	e1000e_intrmgr_stop_timer(&core->radv);
248	e1000e_intrmgr_stop_timer(&core->rdtr);
249	e1000e_intrmgr_stop_timer(&core->raid);
250	e1000e_intrmgr_stop_timer(&core->tidv);
251	e1000e_intrmgr_stop_timer(&core->tadv);
252	}
253
254	static bool
255	e1000e_intrmgr_delay_rx_causes(E1000ECore core, uint32_t causes)
256	{
257	uint32_t delayable_causes;
258	uint32_t rdtr = core->mac[RDTR];
259	uint32_t radv = core->mac[RADV];
260	uint32_t raid = core->mac[RAID];
261
262	if (msix_enabled(core->owner)) {
263	return false;
264	}
265
266	delayable_causes = E1000_ICR_RXQ0 \|
267	E1000_ICR_RXQ1 \|
268	E1000_ICR_RXT0;
269
270	if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
271	delayable_causes \|= E1000_ICR_ACK;
272	}
273
274	/* Clean up all causes that may be delayed */
275	core->delayed_causes \|= *causes & delayable_causes;
276	*causes &= ~delayable_causes;
277
278	/*
279	* Check if delayed RX interrupts disabled by client
280	* or if there are causes that cannot be delayed
281	*/
282	if ((rdtr == 0) \|\| (*causes != 0)) {
283	return false;
284	}
285
286	/*
287	* Check if delayed RX ACK interrupts disabled by client
288	* and there is an ACK packet received
289	*/
290	if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
291	return false;
292	}
293
294	/* All causes delayed */
295	e1000e_intrmgr_rearm_timer(&core->rdtr);
296
297	if (!core->radv.running && (radv != 0)) {
298	e1000e_intrmgr_rearm_timer(&core->radv);
299	}
300
301	if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
302	e1000e_intrmgr_rearm_timer(&core->raid);
303	}
304
305	return true;
306	}
307
308	static bool
309	e1000e_intrmgr_delay_tx_causes(E1000ECore core, uint32_t causes)
310	{
311	static const uint32_t delayable_causes = E1000_ICR_TXQ0 \|
312	E1000_ICR_TXQ1 \|
313	E1000_ICR_TXQE \|
314	E1000_ICR_TXDW;
315
316	if (msix_enabled(core->owner)) {
317	return false;
318	}
319
320	/* Clean up all causes that may be delayed */
321	core->delayed_causes \|= *causes & delayable_causes;
322	*causes &= ~delayable_causes;
323
324	/* If there are causes that cannot be delayed */
325	if (*causes != 0) {
326	return false;
327	}
328
329	/* All causes delayed */
330	e1000e_intrmgr_rearm_timer(&core->tidv);
331
332	if (!core->tadv.running && (core->mac[TADV] != 0)) {
333	e1000e_intrmgr_rearm_timer(&core->tadv);
334	}
335
336	return true;
337	}
338
339	static uint32_t
340	e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
341	{
342	uint32_t res;
343
344	res = core->delayed_causes;
345	core->delayed_causes = 0;
346
347	e1000e_intrmgr_stop_delay_timers(core);
348
349	return res;
350	}
351
352	static void
353	e1000e_intrmgr_fire_all_timers(E1000ECore *core)
354	{
355	int i;
356
357	if (core->itr.running) {
358	timer_del(core->itr.timer);
359	e1000e_intrmgr_on_throttling_timer(&core->itr);
360	}
361
362	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
363	if (core->eitr[i].running) {
364	timer_del(core->eitr[i].timer);
365	e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
366	}
367	}
368	}
369
370	static void
371	e1000e_intrmgr_resume(E1000ECore *core)
372	{
373	int i;
374
375	e1000e_intmgr_timer_resume(&core->radv);
376	e1000e_intmgr_timer_resume(&core->rdtr);
377	e1000e_intmgr_timer_resume(&core->raid);
378	e1000e_intmgr_timer_resume(&core->tidv);
379	e1000e_intmgr_timer_resume(&core->tadv);
380
381	e1000e_intmgr_timer_resume(&core->itr);
382
383	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
384	e1000e_intmgr_timer_resume(&core->eitr[i]);
385	}
386	}
387
388	static void
389	e1000e_intrmgr_reset(E1000ECore *core)
390	{
391	int i;
392
393	core->delayed_causes = 0;
394
395	e1000e_intrmgr_stop_delay_timers(core);
396
397	e1000e_intrmgr_stop_timer(&core->itr);
398
399	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
400	e1000e_intrmgr_stop_timer(&core->eitr[i]);
401	}
402	}
403
404	static void
405	e1000e_intrmgr_pci_unint(E1000ECore *core)
406	{
407	int i;
408
409	timer_free(core->radv.timer);
410	timer_free(core->rdtr.timer);
411	timer_free(core->raid.timer);
412
413	timer_free(core->tadv.timer);
414	timer_free(core->tidv.timer);
415
416	timer_free(core->itr.timer);
417
418	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
419	timer_free(core->eitr[i].timer);
420	}
421	}
422
423	static void
424	e1000e_intrmgr_pci_realize(E1000ECore *core)
425	{
426	e1000e_intrmgr_initialize_all_timers(core, true);
427	}
428
429	static inline bool
430	e1000e_rx_csum_enabled(E1000ECore *core)
431	{
432	return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
433	}
434
435	static inline bool
436	e1000e_rx_use_legacy_descriptor(E1000ECore *core)
437	{
438	return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
439	}
440
441	static inline bool
442	e1000e_rx_use_ps_descriptor(E1000ECore *core)
443	{
444	return !e1000e_rx_use_legacy_descriptor(core) &&
445	(core->mac[RCTL] & E1000_RCTL_DTYP_PS);
446	}
447
448	static inline bool
449	e1000e_rss_enabled(E1000ECore *core)
450	{
451	return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
452	!e1000e_rx_csum_enabled(core) &&
453	!e1000e_rx_use_legacy_descriptor(core);
454	}
455
456	typedef struct E1000E_RSSInfo_st {
457	bool enabled;
458	uint32_t hash;
459	uint32_t queue;
460	uint32_t type;
461	} E1000E_RSSInfo;
462
463	static uint32_t
464	e1000e_rss_get_hash_type(E1000ECore core, struct NetRxPkt pkt)
465	{
466	bool hasip4, hasip6;
467	EthL4HdrProto l4hdr_proto;
468
469	assert(e1000e_rss_enabled(core));
470
471	net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
472
473	if (hasip4) {
474	trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
475	E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
476	E1000_MRQC_EN_IPV4(core->mac[MRQC]));
477
478	if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
479	E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
480	return E1000_MRQ_RSS_TYPE_IPV4TCP;
481	}
482
483	if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
484	return E1000_MRQ_RSS_TYPE_IPV4;
485	}
486	} else if (hasip6) {
487	eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
488
489	bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
490	bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
491
492	/*
493	* Following two traces must not be combined because resulting
494	* event will have 11 arguments totally and some trace backends
495	* (at least "ust") have limitation of maximum 10 arguments per
496	* event. Events with more arguments fail to compile for
497	* backends like these.
498	*/
499	trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
500	trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
501	ip6info->has_ext_hdrs,
502	ip6info->rss_ex_dst_valid,
503	ip6info->rss_ex_src_valid,
504	core->mac[MRQC],
505	E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
506	E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
507	E1000_MRQC_EN_IPV6(core->mac[MRQC]));
508
509	if ((!ex_dis \|\| !ip6info->has_ext_hdrs) &&
510	(!new_ex_dis \|\| !(ip6info->rss_ex_dst_valid \|\|
511	ip6info->rss_ex_src_valid))) {
512
513	if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
514	E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
515	return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
516	}
517
518	if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
519	return E1000_MRQ_RSS_TYPE_IPV6EX;
520	}
521
522	}
523
524	if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
525	return E1000_MRQ_RSS_TYPE_IPV6;
526	}
527
528	}
529
530	return E1000_MRQ_RSS_TYPE_NONE;
531	}
532
533	static uint32_t
534	e1000e_rss_calc_hash(E1000ECore *core,
535	struct NetRxPkt *pkt,
536	E1000E_RSSInfo *info)
537	{
538	NetRxPktRssType type;
539
540	assert(e1000e_rss_enabled(core));
541
542	switch (info->type) {
543	case E1000_MRQ_RSS_TYPE_IPV4:
544	type = NetPktRssIpV4;
545	break;
546	case E1000_MRQ_RSS_TYPE_IPV4TCP:
547	type = NetPktRssIpV4Tcp;
548	break;
549	case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
550	type = NetPktRssIpV6TcpEx;
551	break;
552	case E1000_MRQ_RSS_TYPE_IPV6:
553	type = NetPktRssIpV6;
554	break;
555	case E1000_MRQ_RSS_TYPE_IPV6EX:
556	type = NetPktRssIpV6Ex;
557	break;
558	default:
559	g_assert_not_reached();
560	}
561
562	return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
563	}
564
565	static void
566	e1000e_rss_parse_packet(E1000ECore *core,
567	struct NetRxPkt *pkt,
568	E1000E_RSSInfo *info)
569	{
570	trace_e1000e_rx_rss_started();
571
572	if (!e1000e_rss_enabled(core)) {
573	info->enabled = false;
574	info->hash = 0;
575	info->queue = 0;
576	info->type = 0;
577	trace_e1000e_rx_rss_disabled();
578	return;
579	}
580
581	info->enabled = true;
582
583	info->type = e1000e_rss_get_hash_type(core, pkt);
584
585	trace_e1000e_rx_rss_type(info->type);
586
587	if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
588	info->hash = 0;
589	info->queue = 0;
590	return;
591	}
592
593	info->hash = e1000e_rss_calc_hash(core, pkt, info);
594	info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
595	}
596
597	static bool
598	e1000e_setup_tx_offloads(E1000ECore core, struct e1000e_tx tx)
599	{
600	if (tx->props.tse && tx->cptse) {
601	if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) {
602	return false;
603	}
604
605	net_tx_pkt_update_ip_checksums(tx->tx_pkt);
606	e1000x_inc_reg_if_not_full(core->mac, TSCTC);
607	return true;
608	}
609
610	if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
611	if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
612	return false;
613	}
614	}
615
616	if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
617	net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
618	}
619
620	return true;
621	}
622
623	static void e1000e_tx_pkt_callback(void *core,
624	const struct iovec *iov,
625	int iovcnt,
626	const struct iovec *virt_iov,
627	int virt_iovcnt)
628	{
629	e1000e_receive_internal(core, virt_iov, virt_iovcnt, true);
630	}
631
632	static bool
633	e1000e_tx_pkt_send(E1000ECore core, struct e1000e_tx tx, int queue_index)
634	{
635	int target_queue = MIN(core->max_queue_num, queue_index);
636	NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
637
638	if (!e1000e_setup_tx_offloads(core, tx)) {
639	return false;
640	}
641
642	net_tx_pkt_dump(tx->tx_pkt);
643
644	if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) \|\|
645	((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
646	return net_tx_pkt_send_custom(tx->tx_pkt, false,
647	e1000e_tx_pkt_callback, core);
648	} else {
649	return net_tx_pkt_send(tx->tx_pkt, queue);
650	}
651	}
652
653	static void
654	e1000e_on_tx_done_update_stats(E1000ECore core, struct NetTxPkt tx_pkt)
655	{
656	static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
657	PTC1023, PTC1522 };
658
659	size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
660
661	e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
662	e1000x_inc_reg_if_not_full(core->mac, TPT);
663	e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
664
665	switch (net_tx_pkt_get_packet_type(tx_pkt)) {
666	case ETH_PKT_BCAST:
667	e1000x_inc_reg_if_not_full(core->mac, BPTC);
668	break;
669	case ETH_PKT_MCAST:
670	e1000x_inc_reg_if_not_full(core->mac, MPTC);
671	break;
672	case ETH_PKT_UCAST:
673	break;
674	default:
675	g_assert_not_reached();
676	}
677
678	e1000x_inc_reg_if_not_full(core->mac, GPTC);
679	e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
680	}
681
682	static void
683	e1000e_process_tx_desc(E1000ECore *core,
684	struct e1000e_tx *tx,
685	struct e1000_tx_desc *dp,
686	int queue_index)
687	{
688	uint32_t txd_lower = le32_to_cpu(dp->lower.data);
689	uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D);
690	unsigned int split_size = txd_lower & 0xffff;
691	uint64_t addr;
692	struct e1000_context_desc xp = (struct e1000_context_desc )dp;
693	bool eop = txd_lower & E1000_TXD_CMD_EOP;
694
695	if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
696	e1000x_read_tx_ctx_descr(xp, &tx->props);
697	e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
698	return;
699	} else if (dtype == (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D)) {
700	/* data descriptor */
701	tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
702	tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
703	e1000e_process_ts_option(core, dp);
704	} else {
705	/* legacy descriptor */
706	e1000e_process_ts_option(core, dp);
707	tx->cptse = 0;
708	}
709
710	addr = le64_to_cpu(dp->buffer_addr);
711
712	if (!tx->skip_cp) {
713	if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner,
714	addr, split_size)) {
715	tx->skip_cp = true;
716	}
717	}
718
719	if (eop) {
720	if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
721	if (e1000x_vlan_enabled(core->mac) &&
722	e1000x_is_vlan_txd(txd_lower)) {
723	net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
724	le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
725	}
726	if (e1000e_tx_pkt_send(core, tx, queue_index)) {
727	e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
728	}
729	}
730
731	tx->skip_cp = false;
732	net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
733
734	tx->sum_needed = 0;
735	tx->cptse = 0;
736	}
737	}
738
739	static inline uint32_t
740	e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
741	{
742	if (!msix_enabled(core->owner)) {
743	return E1000_ICR_TXDW;
744	}
745
746	return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
747	}
748
749	static inline uint32_t
750	e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
751	bool min_threshold_hit)
752	{
753	if (!msix_enabled(core->owner)) {
754	return E1000_ICS_RXT0 \| (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
755	}
756
757	return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
758	}
759
760	static uint32_t
761	e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
762	struct e1000_tx_desc dp, bool ide, int queue_idx)
763	{
764	uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
765
766	if (!(txd_lower & E1000_TXD_CMD_RS) &&
767	!(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
768	return 0;
769	}
770
771	*ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
772
773	txd_upper = le32_to_cpu(dp->upper.data) \| E1000_TXD_STAT_DD;
774
775	dp->upper.data = cpu_to_le32(txd_upper);
776	pci_dma_write(core->owner, base + ((char )&dp->upper - (char )dp),
777	&dp->upper, sizeof(dp->upper));
778	return e1000e_tx_wb_interrupt_cause(core, queue_idx);
779	}
780
781	typedef struct E1000ERingInfo {
782	int dbah;
783	int dbal;
784	int dlen;
785	int dh;
786	int dt;
787	int idx;
788	} E1000ERingInfo;
789
790	static inline bool
791	e1000e_ring_empty(E1000ECore core, const E1000ERingInfo r)
792	{
793	return core->mac[r->dh] == core->mac[r->dt] \|\|
794	core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
795	}
796
797	static inline uint64_t
798	e1000e_ring_base(E1000ECore core, const E1000ERingInfo r)
799	{
800	uint64_t bah = core->mac[r->dbah];
801	uint64_t bal = core->mac[r->dbal];
802
803	return (bah << 32) + bal;
804	}
805
806	static inline uint64_t
807	e1000e_ring_head_descr(E1000ECore core, const E1000ERingInfo r)
808	{
809	return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
810	}
811
812	static inline void
813	e1000e_ring_advance(E1000ECore core, const E1000ERingInfo r, uint32_t count)
814	{
815	core->mac[r->dh] += count;
816
817	if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
818	core->mac[r->dh] = 0;
819	}
820	}
821
822	static inline uint32_t
823	e1000e_ring_free_descr_num(E1000ECore core, const E1000ERingInfo r)
824	{
825	trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
826	core->mac[r->dh], core->mac[r->dt]);
827
828	if (core->mac[r->dh] <= core->mac[r->dt]) {
829	return core->mac[r->dt] - core->mac[r->dh];
830	}
831
832	if (core->mac[r->dh] > core->mac[r->dt]) {
833	return core->mac[r->dlen] / E1000_RING_DESC_LEN +
834	core->mac[r->dt] - core->mac[r->dh];
835	}
836
837	g_assert_not_reached();
838	}
839
840	static inline bool
841	e1000e_ring_enabled(E1000ECore core, const E1000ERingInfo r)
842	{
843	return core->mac[r->dlen] > 0;
844	}
845
846	static inline uint32_t
847	e1000e_ring_len(E1000ECore core, const E1000ERingInfo r)
848	{
849	return core->mac[r->dlen];
850	}
851
852	typedef struct E1000E_TxRing_st {
853	const E1000ERingInfo *i;
854	struct e1000e_tx *tx;
855	} E1000E_TxRing;
856
857	static inline int
858	e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
859	{
860	return (reg_idx - base_reg_idx) / (0x100 >> 2);
861	}
862
863	static inline void
864	e1000e_tx_ring_init(E1000ECore core, E1000E_TxRing txr, int idx)
865	{
866	static const E1000ERingInfo i[E1000E_NUM_QUEUES] = {
867	{ TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
868	{ TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
869	};
870
871	assert(idx < ARRAY_SIZE(i));
872
873	txr->i = &i[idx];
874	txr->tx = &core->tx[idx];
875	}
876
877	typedef struct E1000E_RxRing_st {
878	const E1000ERingInfo *i;
879	} E1000E_RxRing;
880
881	static inline void
882	e1000e_rx_ring_init(E1000ECore core, E1000E_RxRing rxr, int idx)
883	{
884	static const E1000ERingInfo i[E1000E_NUM_QUEUES] = {
885	{ RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
886	{ RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
887	};
888
889	assert(idx < ARRAY_SIZE(i));
890
891	rxr->i = &i[idx];
892	}
893
894	static void
895	e1000e_start_xmit(E1000ECore core, const E1000E_TxRing txr)
896	{
897	dma_addr_t base;
898	struct e1000_tx_desc desc;
899	bool ide = false;
900	const E1000ERingInfo *txi = txr->i;
901	uint32_t cause = E1000_ICS_TXQE;
902
903	if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
904	trace_e1000e_tx_disabled();
905	return;
906	}
907
908	while (!e1000e_ring_empty(core, txi)) {
909	base = e1000e_ring_head_descr(core, txi);
910
911	pci_dma_read(core->owner, base, &desc, sizeof(desc));
912
913	trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
914	desc.lower.data, desc.upper.data);
915
916	e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
917	cause \|= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
918
919	e1000e_ring_advance(core, txi, 1);
920	}
921
922	if (!ide \|\| !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
923	e1000e_set_interrupt_cause(core, cause);
924	}
925
926	net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
927	}
928
929	static bool
930	e1000e_has_rxbufs(E1000ECore core, const E1000ERingInfo r,
931	size_t total_size)
932	{
933	uint32_t bufs = e1000e_ring_free_descr_num(core, r);
934
935	trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
936	core->rx_desc_buf_size);
937
938	return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
939	core->rx_desc_buf_size;
940	}
941
942	void
943	e1000e_start_recv(E1000ECore *core)
944	{
945	int i;
946
947	trace_e1000e_rx_start_recv();
948
949	for (i = 0; i <= core->max_queue_num; i++) {
950	qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
951	}
952	}
953
954	bool
955	e1000e_can_receive(E1000ECore *core)
956	{
957	int i;
958
959	if (!e1000x_rx_ready(core->owner, core->mac)) {
960	return false;
961	}
962
963	for (i = 0; i < E1000E_NUM_QUEUES; i++) {
964	E1000E_RxRing rxr;
965
966	e1000e_rx_ring_init(core, &rxr, i);
967	if (e1000e_ring_enabled(core, rxr.i) &&
968	e1000e_has_rxbufs(core, rxr.i, 1)) {
969	trace_e1000e_rx_can_recv();
970	return true;
971	}
972	}
973
974	trace_e1000e_rx_can_recv_rings_full();
975	return false;
976	}
977
978	ssize_t
979	e1000e_receive(E1000ECore core, const uint8_t buf, size_t size)
980	{
981	const struct iovec iov = {
982	.iov_base = (uint8_t *)buf,
983	.iov_len = size
984	};
985
986	return e1000e_receive_iov(core, &iov, 1);
987	}
988
989	static inline bool
990	e1000e_rx_l3_cso_enabled(E1000ECore *core)
991	{
992	return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
993	}
994
995	static inline bool
996	e1000e_rx_l4_cso_enabled(E1000ECore *core)
997	{
998	return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
999	}
1000
1001	static bool
1002	e1000e_receive_filter(E1000ECore core, const void buf)
1003	{
1004	return (!e1000x_is_vlan_packet(buf, core->mac[VET]) \|\|
1005	e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) &&
1006	e1000x_rx_group_filter(core->mac, buf);
1007	}
1008
1009	static inline void
1010	e1000e_read_lgcy_rx_descr(E1000ECore core, struct e1000_rx_desc desc,
1011	hwaddr *buff_addr)
1012	{
1013	*buff_addr = le64_to_cpu(desc->buffer_addr);
1014	}
1015
1016	static inline void
1017	e1000e_read_ext_rx_descr(E1000ECore core, union e1000_rx_desc_extended desc,
1018	hwaddr *buff_addr)
1019	{
1020	*buff_addr = le64_to_cpu(desc->read.buffer_addr);
1021	}
1022
1023	static inline void
1024	e1000e_read_ps_rx_descr(E1000ECore *core,
1025	union e1000_rx_desc_packet_split *desc,
1026	hwaddr buff_addr[MAX_PS_BUFFERS])
1027	{
1028	int i;
1029
1030	for (i = 0; i < MAX_PS_BUFFERS; i++) {
1031	buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]);
1032	}
1033
1034	trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1],
1035	buff_addr[2], buff_addr[3]);
1036	}
1037
1038	static inline void
1039	e1000e_read_rx_descr(E1000ECore core, union e1000_rx_desc_union desc,
1040	hwaddr buff_addr[MAX_PS_BUFFERS])
1041	{
1042	if (e1000e_rx_use_legacy_descriptor(core)) {
1043	e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]);
1044	buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1045	} else {
1046	if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1047	e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr);
1048	} else {
1049	e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]);
1050	buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1051	}
1052	}
1053	}
1054
1055	static void
1056	e1000e_verify_csum_in_sw(E1000ECore *core,
1057	struct NetRxPkt *pkt,
1058	uint32_t *status_flags,
1059	EthL4HdrProto l4hdr_proto)
1060	{
1061	bool csum_valid;
1062	uint32_t csum_error;
1063
1064	if (e1000e_rx_l3_cso_enabled(core)) {
1065	if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1066	trace_e1000e_rx_metadata_l3_csum_validation_failed();
1067	} else {
1068	csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1069	*status_flags \|= E1000_RXD_STAT_IPCS \| csum_error;
1070	}
1071	} else {
1072	trace_e1000e_rx_metadata_l3_cso_disabled();
1073	}
1074
1075	if (!e1000e_rx_l4_cso_enabled(core)) {
1076	trace_e1000e_rx_metadata_l4_cso_disabled();
1077	return;
1078	}
1079
1080	if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
1081	l4hdr_proto != ETH_L4_HDR_PROTO_UDP) {
1082	return;
1083	}
1084
1085	if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1086	trace_e1000e_rx_metadata_l4_csum_validation_failed();
1087	return;
1088	}
1089
1090	csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1091	*status_flags \|= E1000_RXD_STAT_TCPCS \| csum_error;
1092
1093	if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1094	*status_flags \|= E1000_RXD_STAT_UDPCS;
1095	}
1096	}
1097
1098	static inline bool
1099	e1000e_is_tcp_ack(E1000ECore core, struct NetRxPkt rx_pkt)
1100	{
1101	if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1102	return false;
1103	}
1104
1105	if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1106	return !net_rx_pkt_has_tcp_data(rx_pkt);
1107	}
1108
1109	return true;
1110	}
1111
1112	static void
1113	e1000e_build_rx_metadata(E1000ECore *core,
1114	struct NetRxPkt *pkt,
1115	bool is_eop,
1116	const E1000E_RSSInfo *rss_info,
1117	uint32_t rss, uint32_t mrq,
1118	uint32_t *status_flags,
1119	uint16_t *ip_id,
1120	uint16_t *vlan_tag)
1121	{
1122	struct virtio_net_hdr *vhdr;
1123	bool hasip4, hasip6;
1124	EthL4HdrProto l4hdr_proto;
1125	uint32_t pkt_type;
1126
1127	*status_flags = E1000_RXD_STAT_DD;
1128
1129	/* No additional metadata needed for non-EOP descriptors */
1130	if (!is_eop) {
1131	goto func_exit;
1132	}
1133
1134	*status_flags \|= E1000_RXD_STAT_EOP;
1135
1136	net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1137	trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1138
1139	/* VLAN state */
1140	if (net_rx_pkt_is_vlan_stripped(pkt)) {
1141	*status_flags \|= E1000_RXD_STAT_VP;
1142	*vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1143	trace_e1000e_rx_metadata_vlan(*vlan_tag);
1144	}
1145
1146	/* Packet parsing results */
1147	if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1148	if (rss_info->enabled) {
1149	*rss = cpu_to_le32(rss_info->hash);
1150	*mrq = cpu_to_le32(rss_info->type \| (rss_info->queue << 8));
1151	trace_e1000e_rx_metadata_rss(rss, mrq);
1152	}
1153	} else if (hasip4) {
1154	*status_flags \|= E1000_RXD_STAT_IPIDV;
1155	*ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1156	trace_e1000e_rx_metadata_ip_id(*ip_id);
1157	}
1158
1159	if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) {
1160	*status_flags \|= E1000_RXD_STAT_ACK;
1161	trace_e1000e_rx_metadata_ack();
1162	}
1163
1164	if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1165	trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1166	pkt_type = E1000_RXD_PKT_MAC;
1167	} else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP \|\|
1168	l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1169	pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1170	} else if (hasip4 \|\| hasip6) {
1171	pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1172	} else {
1173	pkt_type = E1000_RXD_PKT_MAC;
1174	}
1175
1176	*status_flags \|= E1000_RXD_PKT_TYPE(pkt_type);
1177	trace_e1000e_rx_metadata_pkt_type(pkt_type);
1178
1179	/* RX CSO information */
1180	if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1181	trace_e1000e_rx_metadata_ipv6_sum_disabled();
1182	goto func_exit;
1183	}
1184
1185	vhdr = net_rx_pkt_get_vhdr(pkt);
1186
1187	if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1188	!(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1189	trace_e1000e_rx_metadata_virthdr_no_csum_info();
1190	e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1191	goto func_exit;
1192	}
1193
1194	if (e1000e_rx_l3_cso_enabled(core)) {
1195	*status_flags \|= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1196	} else {
1197	trace_e1000e_rx_metadata_l3_cso_disabled();
1198	}
1199
1200	if (e1000e_rx_l4_cso_enabled(core)) {
1201	switch (l4hdr_proto) {
1202	case ETH_L4_HDR_PROTO_TCP:
1203	*status_flags \|= E1000_RXD_STAT_TCPCS;
1204	break;
1205
1206	case ETH_L4_HDR_PROTO_UDP:
1207	*status_flags \|= E1000_RXD_STAT_TCPCS \| E1000_RXD_STAT_UDPCS;
1208	break;
1209
1210	default:
1211	break;
1212	}
1213	} else {
1214	trace_e1000e_rx_metadata_l4_cso_disabled();
1215	}
1216
1217	func_exit:
1218	trace_e1000e_rx_metadata_status_flags(*status_flags);
1219	status_flags = cpu_to_le32(status_flags);
1220	}
1221
1222	static inline void
1223	e1000e_write_lgcy_rx_descr(E1000ECore core, struct e1000_rx_desc desc,
1224	struct NetRxPkt *pkt,
1225	const E1000E_RSSInfo *rss_info,
1226	uint16_t length)
1227	{
1228	uint32_t status_flags, rss, mrq;
1229	uint16_t ip_id;
1230
1231	assert(!rss_info->enabled);
1232
1233	desc->length = cpu_to_le16(length);
1234	desc->csum = 0;
1235
1236	e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1237	rss_info,
1238	&rss, &mrq,
1239	&status_flags, &ip_id,
1240	&desc->special);
1241	desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1242	desc->status = (uint8_t) le32_to_cpu(status_flags);
1243	}
1244
1245	static inline void
1246	e1000e_write_ext_rx_descr(E1000ECore core, union e1000_rx_desc_extended desc,
1247	struct NetRxPkt *pkt,
1248	const E1000E_RSSInfo *rss_info,
1249	uint16_t length)
1250	{
1251	memset(&desc->wb, 0, sizeof(desc->wb));
1252
1253	desc->wb.upper.length = cpu_to_le16(length);
1254
1255	e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1256	rss_info,
1257	&desc->wb.lower.hi_dword.rss,
1258	&desc->wb.lower.mrq,
1259	&desc->wb.upper.status_error,
1260	&desc->wb.lower.hi_dword.csum_ip.ip_id,
1261	&desc->wb.upper.vlan);
1262	}
1263
1264	static inline void
1265	e1000e_write_ps_rx_descr(E1000ECore *core,
1266	union e1000_rx_desc_packet_split *desc,
1267	struct NetRxPkt *pkt,
1268	const E1000E_RSSInfo *rss_info,
1269	size_t ps_hdr_len,
1270	uint16_t(*written)[MAX_PS_BUFFERS])
1271	{
1272	int i;
1273
1274	memset(&desc->wb, 0, sizeof(desc->wb));
1275
1276	desc->wb.middle.length0 = cpu_to_le16((*written)[0]);
1277
1278	for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1279	desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1280	}
1281
1282	e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1283	rss_info,
1284	&desc->wb.lower.hi_dword.rss,
1285	&desc->wb.lower.mrq,
1286	&desc->wb.middle.status_error,
1287	&desc->wb.lower.hi_dword.csum_ip.ip_id,
1288	&desc->wb.middle.vlan);
1289
1290	desc->wb.upper.header_status =
1291	cpu_to_le16(ps_hdr_len \| (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1292
1293	trace_e1000e_rx_desc_ps_write((written)[0], (written)[1],
1294	(written)[2], (written)[3]);
1295	}
1296
1297	static inline void
1298	e1000e_write_rx_descr(E1000ECore core, union e1000_rx_desc_union desc,
1299	struct NetRxPkt pkt, const E1000E_RSSInfo rss_info,
1300	size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1301	{
1302	if (e1000e_rx_use_legacy_descriptor(core)) {
1303	assert(ps_hdr_len == 0);
1304	e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
1305	(*written)[0]);
1306	} else {
1307	if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1308	e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info,
1309	ps_hdr_len, written);
1310	} else {
1311	assert(ps_hdr_len == 0);
1312	e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info,
1313	(*written)[0]);
1314	}
1315	}
1316	}
1317
1318	static inline void
1319	e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr,
1320	union e1000_rx_desc_union *desc, dma_addr_t len)
1321	{
1322	PCIDevice *dev = core->owner;
1323
1324	if (e1000e_rx_use_legacy_descriptor(core)) {
1325	struct e1000_rx_desc *d = &desc->legacy;
1326	size_t offset = offsetof(struct e1000_rx_desc, status);
1327	uint8_t status = d->status;
1328
1329	d->status &= ~E1000_RXD_STAT_DD;
1330	pci_dma_write(dev, addr, desc, len);
1331
1332	if (status & E1000_RXD_STAT_DD) {
1333	d->status = status;
1334	pci_dma_write(dev, addr + offset, &status, sizeof(status));
1335	}
1336	} else {
1337	if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1338	union e1000_rx_desc_packet_split *d = &desc->packet_split;
1339	size_t offset = offsetof(union e1000_rx_desc_packet_split,
1340	wb.middle.status_error);
1341	uint32_t status = d->wb.middle.status_error;
1342
1343	d->wb.middle.status_error &= ~E1000_RXD_STAT_DD;
1344	pci_dma_write(dev, addr, desc, len);
1345
1346	if (status & E1000_RXD_STAT_DD) {
1347	d->wb.middle.status_error = status;
1348	pci_dma_write(dev, addr + offset, &status, sizeof(status));
1349	}
1350	} else {
1351	union e1000_rx_desc_extended *d = &desc->extended;
1352	size_t offset = offsetof(union e1000_rx_desc_extended,
1353	wb.upper.status_error);
1354	uint32_t status = d->wb.upper.status_error;
1355
1356	d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1357	pci_dma_write(dev, addr, desc, len);
1358
1359	if (status & E1000_RXD_STAT_DD) {
1360	d->wb.upper.status_error = status;
1361	pci_dma_write(dev, addr + offset, &status, sizeof(status));
1362	}
1363	}
1364	}
1365	}
1366
1367	typedef struct E1000EBAState {
1368	uint16_t written[MAX_PS_BUFFERS];
1369	uint8_t cur_idx;
1370	} E1000EBAState;
1371
1372	static inline void
1373	e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core,
1374	hwaddr ba[MAX_PS_BUFFERS],
1375	E1000EBAState *bastate,
1376	const char *data,
1377	dma_addr_t data_len)
1378	{
1379	assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1380
1381	pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len);
1382	bastate->written[0] += data_len;
1383
1384	bastate->cur_idx = 1;
1385	}
1386
1387	static void
1388	e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core,
1389	hwaddr ba[MAX_PS_BUFFERS],
1390	E1000EBAState *bastate,
1391	const char *data,
1392	dma_addr_t data_len)
1393	{
1394	while (data_len > 0) {
1395	uint32_t cur_buf_len, cur_buf_bytes_left, bytes_to_write;
1396
1397	assert(bastate->cur_idx < MAX_PS_BUFFERS);
1398
1399	cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1400	cur_buf_bytes_left = cur_buf_len - bastate->written[bastate->cur_idx];
1401	bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1402
1403	trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1404	ba[bastate->cur_idx],
1405	bastate->written[bastate->cur_idx],
1406	data,
1407	bytes_to_write);
1408
1409	pci_dma_write(core->owner,
1410	ba[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1411	data, bytes_to_write);
1412
1413	bastate->written[bastate->cur_idx] += bytes_to_write;
1414	data += bytes_to_write;
1415	data_len -= bytes_to_write;
1416
1417	if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1418	bastate->cur_idx++;
1419	}
1420	}
1421	}
1422
1423	static void
1424	e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size)
1425	{
1426	eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
1427	e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
1428	}
1429
1430	static inline bool
1431	e1000e_rx_descr_threshold_hit(E1000ECore core, const E1000ERingInfo rxi)
1432	{
1433	return e1000e_ring_free_descr_num(core, rxi) ==
1434	e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1435	}
1436
1437	static bool
1438	e1000e_do_ps(E1000ECore core, struct NetRxPkt pkt, size_t *hdr_len)
1439	{
1440	bool hasip4, hasip6;
1441	EthL4HdrProto l4hdr_proto;
1442	bool fragment;
1443
1444	if (!e1000e_rx_use_ps_descriptor(core)) {
1445	return false;
1446	}
1447
1448	net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1449
1450	if (hasip4) {
1451	fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1452	} else if (hasip6) {
1453	fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1454	} else {
1455	return false;
1456	}
1457
1458	if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1459	return false;
1460	}
1461
1462	if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP \|\|
1463	l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1464	*hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1465	} else {
1466	*hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1467	}
1468
1469	if ((*hdr_len > core->rxbuf_sizes[0]) \|\|
1470	(*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1471	return false;
1472	}
1473
1474	return true;
1475	}
1476
1477	static void
1478	e1000e_write_packet_to_guest(E1000ECore core, struct NetRxPkt pkt,
1479	const E1000E_RxRing *rxr,
1480	const E1000E_RSSInfo *rss_info)
1481	{
1482	PCIDevice *d = core->owner;
1483	dma_addr_t base;
1484	union e1000_rx_desc_union desc;
1485	size_t desc_offset = 0;
1486	size_t iov_ofs = 0;
1487
1488	struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1489	size_t size = net_rx_pkt_get_total_len(pkt);
1490	size_t total_size = size + e1000x_fcs_len(core->mac);
1491	const E1000ERingInfo *rxi;
1492	size_t ps_hdr_len = 0;
1493	bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1494	bool is_first = true;
1495
1496	rxi = rxr->i;
1497
1498	do {
1499	/*
1500	* Loop processing descriptors while we have packet data to
1501	* DMA to the guest. desc_offset tracks how much data we have
1502	* sent to the guest in total over all descriptors, and goes
1503	* from 0 up to total_size (the size of everything to send to
1504	* the guest including possible trailing 4 bytes of CRC data).
1505	*/
1506	hwaddr ba[MAX_PS_BUFFERS];
1507	E1000EBAState bastate = { { 0 } };
1508	bool is_last = false;
1509
1510	if (e1000e_ring_empty(core, rxi)) {
1511	return;
1512	}
1513
1514	base = e1000e_ring_head_descr(core, rxi);
1515
1516	pci_dma_read(d, base, &desc, core->rx_desc_len);
1517
1518	trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1519
1520	e1000e_read_rx_descr(core, &desc, ba);
1521
1522	if (ba[0]) {
1523	/* Total amount of data DMA'd to the guest in this iteration */
1524	size_t desc_size = 0;
1525	/*
1526	* Total space available in this descriptor (we will update
1527	* this as we use it up)
1528	*/
1529	size_t rx_desc_buf_size = core->rx_desc_buf_size;
1530
1531	if (desc_offset < size) {
1532	size_t iov_copy;
1533	/* Amount of data to copy from the incoming packet */
1534	size_t copy_size = size - desc_offset;
1535
1536	/* For PS mode copy the packet header first */
1537	if (do_ps) {
1538	if (is_first) {
1539	/*
1540	* e1000e_do_ps() guarantees that buffer 0 has enough
1541	* space for the header; otherwise we will not split
1542	* the packet (i.e. do_ps is false).
1543	*/
1544	size_t ps_hdr_copied = 0;
1545	do {
1546	iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1547	iov->iov_len - iov_ofs);
1548
1549	e1000e_write_hdr_frag_to_rx_buffers(core, ba,
1550	&bastate,
1551	iov->iov_base,
1552	iov_copy);
1553
1554	copy_size -= iov_copy;
1555	ps_hdr_copied += iov_copy;
1556
1557	iov_ofs += iov_copy;
1558	if (iov_ofs == iov->iov_len) {
1559	iov++;
1560	iov_ofs = 0;
1561	}
1562	} while (ps_hdr_copied < ps_hdr_len);
1563
1564	is_first = false;
1565	desc_size += ps_hdr_len;
1566	} else {
1567	/* Leave buffer 0 of each descriptor except first */
1568	/* empty as per spec 7.1.5.1 */
1569	e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate,
1570	NULL, 0);
1571	}
1572	rx_desc_buf_size -= core->rxbuf_sizes[0];
1573	}
1574
1575	/*
1576	* Clamp the amount of packet data we copy into what will fit
1577	* into the remaining buffers in the descriptor.
1578	*/
1579	if (copy_size > rx_desc_buf_size) {
1580	copy_size = rx_desc_buf_size;
1581	}
1582	desc_size += copy_size;
1583	rx_desc_buf_size -= copy_size;
1584
1585	/* Copy packet payload */
1586	while (copy_size) {
1587	iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1588
1589	e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate,
1590	iov->iov_base +
1591	iov_ofs,
1592	iov_copy);
1593
1594	copy_size -= iov_copy;
1595	iov_ofs += iov_copy;
1596	if (iov_ofs == iov->iov_len) {
1597	iov++;
1598	iov_ofs = 0;
1599	}
1600	}
1601	}
1602
1603	if (rx_desc_buf_size &&
1604	desc_offset >= size && desc_offset < total_size) {
1605	/*
1606	* We are in the last 4 bytes corresponding to the FCS checksum.
1607	* We only ever write zeroes here (unlike the hardware).
1608	*/
1609	static const uint32_t fcs_pad;
1610	/* Amount of space for the trailing checksum */
1611	size_t fcs_len = MIN(rx_desc_buf_size,
1612	total_size - desc_offset);
1613	e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate,
1614	(const char *)&fcs_pad,
1615	fcs_len);
1616	desc_size += fcs_len;
1617	}
1618	desc_offset += desc_size;
1619	if (desc_offset >= total_size) {
1620	is_last = true;
1621	}
1622	} else { /* as per intel docs; skip descriptors with null buf addr */
1623	trace_e1000e_rx_null_descriptor();
1624	}
1625
1626	e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1627	rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1628	e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len);
1629
1630	e1000e_ring_advance(core, rxi,
1631	core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1632
1633	} while (desc_offset < total_size);
1634
1635	e1000e_update_rx_stats(core, size, total_size);
1636	}
1637
1638	static inline void
1639	e1000e_rx_fix_l4_csum(E1000ECore core, struct NetRxPkt pkt)
1640	{
1641	struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1642
1643	if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1644	net_rx_pkt_fix_l4_csum(pkt);
1645	}
1646	}
1647
1648	ssize_t
1649	e1000e_receive_iov(E1000ECore core, const struct iovec iov, int iovcnt)
1650	{
1651	return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet);
1652	}
1653
1654	static ssize_t
1655	e1000e_receive_internal(E1000ECore core, const struct iovec iov, int iovcnt,
1656	bool has_vnet)
1657	{
1658	uint32_t causes = 0;
1659	uint8_t buf[ETH_ZLEN];
1660	struct iovec min_iov;
1661	size_t size, orig_size;
1662	size_t iov_ofs = 0;
1663	E1000E_RxRing rxr;
1664	E1000E_RSSInfo rss_info;
1665	size_t total_size;
1666	ssize_t retval;
1667	bool rdmts_hit;
1668
1669	trace_e1000e_rx_receive_iov(iovcnt);
1670
1671	if (!e1000x_hw_rx_enabled(core->mac)) {
1672	return -1;
1673	}
1674
1675	/* Pull virtio header in */
1676	if (has_vnet) {
1677	net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1678	iov_ofs = sizeof(struct virtio_net_hdr);
1679	} else {
1680	net_rx_pkt_unset_vhdr(core->rx_pkt);
1681	}
1682
1683	orig_size = iov_size(iov, iovcnt);
1684	size = orig_size - iov_ofs;
1685
1686	/* Pad to minimum Ethernet frame length */
1687	if (size < sizeof(buf)) {
1688	iov_to_buf(iov, iovcnt, iov_ofs, buf, size);
1689	memset(&buf[size], 0, sizeof(buf) - size);
1690	e1000x_inc_reg_if_not_full(core->mac, RUC);
1691	min_iov.iov_base = buf;
1692	min_iov.iov_len = size = sizeof(buf);
1693	iovcnt = 1;
1694	iov = &min_iov;
1695	iov_ofs = 0;
1696	} else {
1697	iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4);
1698	}
1699
1700	/* Discard oversized packets if !LPE and !SBP. */
1701	if (e1000x_is_oversized(core->mac, size)) {
1702	return orig_size;
1703	}
1704
1705	net_rx_pkt_set_packet_type(core->rx_pkt,
1706	get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1707
1708	if (!e1000e_receive_filter(core, buf)) {
1709	trace_e1000e_rx_flt_dropped();
1710	return orig_size;
1711	}
1712
1713	net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1714	e1000x_vlan_enabled(core->mac) ? 0 : -1,
1715	core->mac[VET], 0);
1716
1717	e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1718	e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1719
1720	total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1721	e1000x_fcs_len(core->mac);
1722
1723	if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1724	e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1725
1726	e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1727
1728	retval = orig_size;
1729
1730	/* Perform small receive detection (RSRPD) */
1731	if (total_size < core->mac[RSRPD]) {
1732	causes \|= E1000_ICS_SRPD;
1733	}
1734
1735	/* Perform ACK receive detection */
1736	if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1737	(e1000e_is_tcp_ack(core, core->rx_pkt))) {
1738	causes \|= E1000_ICS_ACK;
1739	}
1740
1741	/* Check if receive descriptor minimum threshold hit */
1742	rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1743	causes \|= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1744
1745	trace_e1000e_rx_written_to_guest(rxr.i->idx);
1746	} else {
1747	causes \|= E1000_ICS_RXO;
1748	retval = 0;
1749
1750	trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1751	}
1752
1753	if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) {
1754	trace_e1000e_rx_interrupt_set(causes);
1755	e1000e_set_interrupt_cause(core, causes);
1756	} else {
1757	trace_e1000e_rx_interrupt_delayed(causes);
1758	}
1759
1760	return retval;
1761	}
1762
1763	static inline bool
1764	e1000e_have_autoneg(E1000ECore *core)
1765	{
1766	return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN;
1767	}
1768
1769	static void e1000e_update_flowctl_status(E1000ECore *core)
1770	{
1771	if (e1000e_have_autoneg(core) &&
1772	core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) {
1773	trace_e1000e_link_autoneg_flowctl(true);
1774	core->mac[CTRL] \|= E1000_CTRL_TFCE \| E1000_CTRL_RFCE;
1775	} else {
1776	trace_e1000e_link_autoneg_flowctl(false);
1777	}
1778	}
1779
1780	static inline void
1781	e1000e_link_down(E1000ECore *core)
1782	{
1783	e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1784	e1000e_update_flowctl_status(core);
1785	}
1786
1787	static inline void
1788	e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1789	{
1790	/* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1791	core->phy[0][MII_BMCR] = val & ~(0x3f \|
1792	MII_BMCR_RESET \|
1793	MII_BMCR_ANRESTART);
1794
1795	if ((val & MII_BMCR_ANRESTART) &&
1796	e1000e_have_autoneg(core)) {
1797	e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1798	}
1799	}
1800
1801	static void
1802	e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1803	{
1804	core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1805
1806	if (val & BIT(10)) {
1807	e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1808	}
1809	}
1810
1811	static void
1812	e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1813	{
1814	core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1815	}
1816
1817	void
1818	e1000e_core_set_link_status(E1000ECore *core)
1819	{
1820	NetClientState *nc = qemu_get_queue(core->owner_nic);
1821	uint32_t old_status = core->mac[STATUS];
1822
1823	trace_e1000e_link_status_changed(nc->link_down ? false : true);
1824
1825	if (nc->link_down) {
1826	e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1827	} else {
1828	if (e1000e_have_autoneg(core) &&
1829	!(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
1830	e1000x_restart_autoneg(core->mac, core->phy[0],
1831	core->autoneg_timer);
1832	} else {
1833	e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1834	e1000e_start_recv(core);
1835	}
1836	}
1837
1838	if (core->mac[STATUS] != old_status) {
1839	e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1840	}
1841	}
1842
1843	static void
1844	e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1845	{
1846	trace_e1000e_core_ctrl_write(index, val);
1847
1848	/* RST is self clearing */
1849	core->mac[CTRL] = val & ~E1000_CTRL_RST;
1850	core->mac[CTRL_DUP] = core->mac[CTRL];
1851
1852	trace_e1000e_link_set_params(
1853	!!(val & E1000_CTRL_ASDE),
1854	(val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1855	!!(val & E1000_CTRL_FRCSPD),
1856	!!(val & E1000_CTRL_FRCDPX),
1857	!!(val & E1000_CTRL_RFCE),
1858	!!(val & E1000_CTRL_TFCE));
1859
1860	if (val & E1000_CTRL_RST) {
1861	trace_e1000e_core_ctrl_sw_reset();
1862	e1000e_reset(core, true);
1863	}
1864
1865	if (val & E1000_CTRL_PHY_RST) {
1866	trace_e1000e_core_ctrl_phy_reset();
1867	core->mac[STATUS] \|= E1000_STATUS_PHYRA;
1868	}
1869	}
1870
1871	static void
1872	e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1873	{
1874	trace_e1000e_rx_set_rfctl(val);
1875
1876	if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1877	trace_e1000e_wrn_iscsi_filtering_not_supported();
1878	}
1879
1880	if (!(val & E1000_RFCTL_NFSW_DIS)) {
1881	trace_e1000e_wrn_nfsw_filtering_not_supported();
1882	}
1883
1884	if (!(val & E1000_RFCTL_NFSR_DIS)) {
1885	trace_e1000e_wrn_nfsr_filtering_not_supported();
1886	}
1887
1888	core->mac[RFCTL] = val;
1889	}
1890
1891	static void
1892	e1000e_calc_per_desc_buf_size(E1000ECore *core)
1893	{
1894	int i;
1895	core->rx_desc_buf_size = 0;
1896
1897	for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1898	core->rx_desc_buf_size += core->rxbuf_sizes[i];
1899	}
1900	}
1901
1902	static void
1903	e1000e_parse_rxbufsize(E1000ECore *core)
1904	{
1905	uint32_t rctl = core->mac[RCTL];
1906
1907	memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1908
1909	if (rctl & E1000_RCTL_DTYP_MASK) {
1910	uint32_t bsize;
1911
1912	bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1913	core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1914
1915	bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1916	core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1917
1918	bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1919	core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1920
1921	bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1922	core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1923	} else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1924	int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1925	core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1926	} else {
1927	core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1928	}
1929
1930	trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1931	core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1932
1933	e1000e_calc_per_desc_buf_size(core);
1934	}
1935
1936	static void
1937	e1000e_calc_rxdesclen(E1000ECore *core)
1938	{
1939	if (e1000e_rx_use_legacy_descriptor(core)) {
1940	core->rx_desc_len = sizeof(struct e1000_rx_desc);
1941	} else {
1942	if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1943	core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1944	} else {
1945	core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1946	}
1947	}
1948	trace_e1000e_rx_desc_len(core->rx_desc_len);
1949	}
1950
1951	static void
1952	e1000e_calc_rxconf(E1000ECore *core)
1953	{
1954	e1000e_parse_rxbufsize(core);
1955	e1000e_calc_rxdesclen(core);
1956	core->rxbuf_min_shift =
1957	((core->mac[RCTL] / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1958	E1000_RING_DESC_LEN_SHIFT;
1959	}
1960
1961	static void
1962	e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1963	{
1964	core->mac[RCTL] = val;
1965	trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1966
1967	if (val & E1000_RCTL_EN) {
1968	e1000e_calc_rxconf(core);
1969	e1000e_start_recv(core);
1970	}
1971	}
1972
1973	static
1974	void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1975	(E1000ECore *, int, uint16_t) = {
1976	[0] = {
1977	[MII_BMCR] = e1000e_set_phy_ctrl,
1978	[PHY_PAGE] = e1000e_set_phy_page,
1979	[PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1980	}
1981	};
1982
1983	static inline bool
1984	e1000e_postpone_interrupt(E1000IntrDelayTimer *timer)
1985	{
1986	if (timer->running) {
1987	trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1988
1989	return true;
1990	}
1991
1992	if (timer->core->mac[timer->delay_reg] != 0) {
1993	e1000e_intrmgr_rearm_timer(timer);
1994	}
1995
1996	return false;
1997	}
1998
1999	static inline bool
2000	e1000e_itr_should_postpone(E1000ECore *core)
2001	{
2002	return e1000e_postpone_interrupt(&core->itr);
2003	}
2004
2005	static inline bool
2006	e1000e_eitr_should_postpone(E1000ECore *core, int idx)
2007	{
2008	return e1000e_postpone_interrupt(&core->eitr[idx]);
2009	}
2010
2011	static void
2012	e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2013	{
2014	uint32_t effective_eiac;
2015
2016	if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2017	uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2018	if (vec < E1000E_MSIX_VEC_NUM) {
2019	if (!e1000e_eitr_should_postpone(core, vec)) {
2020	trace_e1000e_irq_msix_notify_vec(vec);
2021	msix_notify(core->owner, vec);
2022	}
2023	} else {
2024	trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2025	}
2026	} else {
2027	trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2028	}
2029
2030	if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2031	trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2032	core->mac[IAM] &= ~cause;
2033	}
2034
2035	trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2036
2037	effective_eiac = core->mac[EIAC] & cause;
2038
2039	core->mac[ICR] &= ~effective_eiac;
2040
2041	if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2042	core->mac[IMS] &= ~effective_eiac;
2043	}
2044	}
2045
2046	static void
2047	e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2048	{
2049	if (causes & E1000_ICR_RXQ0) {
2050	e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2051	E1000_IVAR_RXQ0(core->mac[IVAR]));
2052	}
2053
2054	if (causes & E1000_ICR_RXQ1) {
2055	e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2056	E1000_IVAR_RXQ1(core->mac[IVAR]));
2057	}
2058
2059	if (causes & E1000_ICR_TXQ0) {
2060	e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2061	E1000_IVAR_TXQ0(core->mac[IVAR]));
2062	}
2063
2064	if (causes & E1000_ICR_TXQ1) {
2065	e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2066	E1000_IVAR_TXQ1(core->mac[IVAR]));
2067	}
2068
2069	if (causes & E1000_ICR_OTHER) {
2070	e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2071	E1000_IVAR_OTHER(core->mac[IVAR]));
2072	}
2073	}
2074
2075	static void
2076	e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2077	{
2078	if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2079	uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2080	if (vec < E1000E_MSIX_VEC_NUM) {
2081	trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2082	msix_clr_pending(core->owner, vec);
2083	} else {
2084	trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2085	}
2086	} else {
2087	trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2088	}
2089	}
2090
2091	static void
2092	e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2093	{
2094	if (causes & E1000_ICR_RXQ0) {
2095	e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2096	E1000_IVAR_RXQ0(core->mac[IVAR]));
2097	}
2098
2099	if (causes & E1000_ICR_RXQ1) {
2100	e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2101	E1000_IVAR_RXQ1(core->mac[IVAR]));
2102	}
2103
2104	if (causes & E1000_ICR_TXQ0) {
2105	e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2106	E1000_IVAR_TXQ0(core->mac[IVAR]));
2107	}
2108
2109	if (causes & E1000_ICR_TXQ1) {
2110	e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2111	E1000_IVAR_TXQ1(core->mac[IVAR]));
2112	}
2113
2114	if (causes & E1000_ICR_OTHER) {
2115	e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2116	E1000_IVAR_OTHER(core->mac[IVAR]));
2117	}
2118	}
2119
2120	static inline void
2121	e1000e_fix_icr_asserted(E1000ECore *core)
2122	{
2123	core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2124	if (core->mac[ICR]) {
2125	core->mac[ICR] \|= E1000_ICR_ASSERTED;
2126	}
2127
2128	trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2129	}
2130
2131	static void e1000e_raise_interrupts(E1000ECore *core,
2132	size_t index, uint32_t causes)
2133	{
2134	bool is_msix = msix_enabled(core->owner);
2135	uint32_t old_causes = core->mac[IMS] & core->mac[ICR];
2136	uint32_t raised_causes;
2137
2138	trace_e1000e_irq_set(index << 2,
2139	core->mac[index], core->mac[index] \| causes);
2140
2141	core->mac[index] \|= causes;
2142
2143	/* Set ICR[OTHER] for MSI-X */
2144	if (is_msix) {
2145	if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2146	core->mac[ICR] \|= E1000_ICR_OTHER;
2147	trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2148	}
2149	}
2150
2151	e1000e_fix_icr_asserted(core);
2152
2153	/*
2154	* Make sure ICR and ICS registers have the same value.
2155	* The spec says that the ICS register is write-only. However in practice,
2156	* on real hardware ICS is readable, and for reads it has the same value as
2157	* ICR (except that ICS does not have the clear on read behaviour of ICR).
2158	*
2159	* The VxWorks PRO/1000 driver uses this behaviour.
2160	*/
2161	core->mac[ICS] = core->mac[ICR];
2162
2163	trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2164	core->mac[ICR], core->mac[IMS]);
2165
2166	raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes;
2167	if (!raised_causes) {
2168	return;
2169	}
2170
2171	if (is_msix) {
2172	e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED);
2173	} else if (!e1000e_itr_should_postpone(core)) {
2174	if (msi_enabled(core->owner)) {
2175	trace_e1000e_irq_msi_notify(raised_causes);
2176	msi_notify(core->owner, 0);
2177	} else {
2178	e1000e_raise_legacy_irq(core);
2179	}
2180	}
2181	}
2182
2183	static void e1000e_lower_interrupts(E1000ECore *core,
2184	size_t index, uint32_t causes)
2185	{
2186	trace_e1000e_irq_clear(index << 2,
2187	core->mac[index], core->mac[index] & ~causes);
2188
2189	core->mac[index] &= ~causes;
2190
2191	/*
2192	* Make sure ICR and ICS registers have the same value.
2193	* The spec says that the ICS register is write-only. However in practice,
2194	* on real hardware ICS is readable, and for reads it has the same value as
2195	* ICR (except that ICS does not have the clear on read behaviour of ICR).
2196	*
2197	* The VxWorks PRO/1000 driver uses this behaviour.
2198	*/
2199	core->mac[ICS] = core->mac[ICR];
2200
2201	trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2202	core->mac[ICR], core->mac[IMS]);
2203
2204	if (!(core->mac[IMS] & core->mac[ICR]) &&
2205	!msix_enabled(core->owner) && !msi_enabled(core->owner)) {
2206	e1000e_lower_legacy_irq(core);
2207	}
2208	}
2209
2210	static void
2211	e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2212	{
2213	val \|= e1000e_intmgr_collect_delayed_causes(core);
2214	e1000e_raise_interrupts(core, ICR, val);
2215	}
2216
2217	static inline void
2218	e1000e_autoneg_timer(void *opaque)
2219	{
2220	E1000ECore *core = opaque;
2221	if (!qemu_get_queue(core->owner_nic)->link_down) {
2222	e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2223	e1000e_start_recv(core);
2224
2225	e1000e_update_flowctl_status(core);
2226	/* signal link status change to the guest */
2227	e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2228	}
2229	}
2230
2231	static inline uint16_t
2232	e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2233	{
2234	uint16_t index = (addr & 0x1ffff) >> 2;
2235	return index + (mac_reg_access[index] & 0xfffe);
2236	}
2237
2238	static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2239	[0] = {
2240	[MII_BMCR] = PHY_ANYPAGE \| PHY_RW,
2241	[MII_BMSR] = PHY_ANYPAGE \| PHY_R,
2242	[MII_PHYID1] = PHY_ANYPAGE \| PHY_R,
2243	[MII_PHYID2] = PHY_ANYPAGE \| PHY_R,
2244	[MII_ANAR] = PHY_ANYPAGE \| PHY_RW,
2245	[MII_ANLPAR] = PHY_ANYPAGE \| PHY_R,
2246	[MII_ANER] = PHY_ANYPAGE \| PHY_R,
2247	[MII_ANNP] = PHY_ANYPAGE \| PHY_RW,
2248	[MII_ANLPRNP] = PHY_ANYPAGE \| PHY_R,
2249	[MII_CTRL1000] = PHY_ANYPAGE \| PHY_RW,
2250	[MII_STAT1000] = PHY_ANYPAGE \| PHY_R,
2251	[MII_EXTSTAT] = PHY_ANYPAGE \| PHY_R,
2252	[PHY_PAGE] = PHY_ANYPAGE \| PHY_RW,
2253
2254	[PHY_COPPER_CTRL1] = PHY_RW,
2255	[PHY_COPPER_STAT1] = PHY_R,
2256	[PHY_COPPER_CTRL3] = PHY_RW,
2257	[PHY_RX_ERR_CNTR] = PHY_R,
2258	[PHY_OEM_BITS] = PHY_RW,
2259	[PHY_BIAS_1] = PHY_RW,
2260	[PHY_BIAS_2] = PHY_RW,
2261	[PHY_COPPER_INT_ENABLE] = PHY_RW,
2262	[PHY_COPPER_STAT2] = PHY_R,
2263	[PHY_COPPER_CTRL2] = PHY_RW
2264	},
2265	[2] = {
2266	[PHY_MAC_CTRL1] = PHY_RW,
2267	[PHY_MAC_INT_ENABLE] = PHY_RW,
2268	[PHY_MAC_STAT] = PHY_R,
2269	[PHY_MAC_CTRL2] = PHY_RW
2270	},
2271	[3] = {
2272	[PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2273	[PHY_LED_03_POL_CTRL] = PHY_RW,
2274	[PHY_LED_TIMER_CTRL] = PHY_RW,
2275	[PHY_LED_45_CTRL] = PHY_RW
2276	},
2277	[5] = {
2278	[PHY_1000T_SKEW] = PHY_R,
2279	[PHY_1000T_SWAP] = PHY_R
2280	},
2281	[6] = {
2282	[PHY_CRC_COUNTERS] = PHY_R
2283	}
2284	};
2285
2286	static bool
2287	e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2288	char cap, uint8_t *page)
2289	{
2290	*page =
2291	(e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2292	: core->phy[0][PHY_PAGE];
2293
2294	if (*page >= E1000E_PHY_PAGES) {
2295	return false;
2296	}
2297
2298	return e1000e_phy_regcap[*page][addr] & cap;
2299	}
2300
2301	static void
2302	e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2303	uint32_t addr, uint16_t data)
2304	{
2305	assert(page < E1000E_PHY_PAGES);
2306	assert(addr < E1000E_PHY_PAGE_SIZE);
2307
2308	if (e1000e_phyreg_writeops[page][addr]) {
2309	e1000e_phyreg_writeops[page][addr](core, addr, data);
2310	} else {
2311	core->phy[page][addr] = data;
2312	}
2313	}
2314
2315	static void
2316	e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2317	{
2318	uint32_t data = val & E1000_MDIC_DATA_MASK;
2319	uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2320	uint8_t page;
2321
2322	if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2323	val = core->mac[MDIC] \| E1000_MDIC_ERROR;
2324	} else if (val & E1000_MDIC_OP_READ) {
2325	if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2326	trace_e1000e_core_mdic_read_unhandled(page, addr);
2327	val \|= E1000_MDIC_ERROR;
2328	} else {
2329	val = (val ^ data) \| core->phy[page][addr];
2330	trace_e1000e_core_mdic_read(page, addr, val);
2331	}
2332	} else if (val & E1000_MDIC_OP_WRITE) {
2333	if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2334	trace_e1000e_core_mdic_write_unhandled(page, addr);
2335	val \|= E1000_MDIC_ERROR;
2336	} else {
2337	trace_e1000e_core_mdic_write(page, addr, data);
2338	e1000e_phy_reg_write(core, page, addr, data);
2339	}
2340	}
2341	core->mac[MDIC] = val \| E1000_MDIC_READY;
2342
2343	if (val & E1000_MDIC_INT_EN) {
2344	e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2345	}
2346	}
2347
2348	static void
2349	e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2350	{
2351	core->mac[index] = val & 0xffff;
2352	trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2353	e1000e_start_recv(core);
2354	}
2355
2356	static void
2357	e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2358	{
2359	if ((val & E1000_STATUS_PHYRA) == 0) {
2360	core->mac[index] &= ~E1000_STATUS_PHYRA;
2361	}
2362	}
2363
2364	static void
2365	e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2366	{
2367	trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2368	!!(val & E1000_CTRL_EXT_SPD_BYPS));
2369
2370	/* Zero self-clearing bits */
2371	val &= ~(E1000_CTRL_EXT_ASDCHK \| E1000_CTRL_EXT_EE_RST);
2372	core->mac[CTRL_EXT] = val;
2373	}
2374
2375	static void
2376	e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2377	{
2378	int i;
2379
2380	core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2381
2382	if (!msix_enabled(core->owner)) {
2383	return;
2384	}
2385
2386	for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2387	if (core->mac[PBACLR] & BIT(i)) {
2388	msix_clr_pending(core->owner, i);
2389	}
2390	}
2391	}
2392
2393	static void
2394	e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2395	{
2396	core->mac[FCRTH] = val & 0xFFF8;
2397	}
2398
2399	static void
2400	e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2401	{
2402	core->mac[FCRTL] = val & 0x8000FFF8;
2403	}
2404
2405	#define E1000E_LOW_BITS_SET_FUNC(num) \
2406	static void \
2407	e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2408	{ \
2409	core->mac[index] = val & (BIT(num) - 1); \
2410	}
2411
2412	E1000E_LOW_BITS_SET_FUNC(4)
2413	E1000E_LOW_BITS_SET_FUNC(6)
2414	E1000E_LOW_BITS_SET_FUNC(11)
2415	E1000E_LOW_BITS_SET_FUNC(12)
2416	E1000E_LOW_BITS_SET_FUNC(13)
2417	E1000E_LOW_BITS_SET_FUNC(16)
2418
2419	static void
2420	e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2421	{
2422	core->mac[VET] = val & 0xffff;
2423	trace_e1000e_vlan_vet(core->mac[VET]);
2424	}
2425
2426	static void
2427	e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2428	{
2429	core->mac[index] = val & E1000_XDLEN_MASK;
2430	}
2431
2432	static void
2433	e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2434	{
2435	core->mac[index] = val & E1000_XDBAL_MASK;
2436	}
2437
2438	static void
2439	e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2440	{
2441	E1000E_TxRing txr;
2442	core->mac[index] = val;
2443
2444	if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2445	e1000e_tx_ring_init(core, &txr, 0);
2446	e1000e_start_xmit(core, &txr);
2447	}
2448
2449	if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2450	e1000e_tx_ring_init(core, &txr, 1);
2451	e1000e_start_xmit(core, &txr);
2452	}
2453	}
2454
2455	static void
2456	e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2457	{
2458	E1000E_TxRing txr;
2459	int qidx = e1000e_mq_queue_idx(TDT, index);
2460	uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2461
2462	core->mac[index] = val & 0xffff;
2463
2464	if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2465	e1000e_tx_ring_init(core, &txr, qidx);
2466	e1000e_start_xmit(core, &txr);
2467	}
2468	}
2469
2470	static void
2471	e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2472	{
2473	trace_e1000e_irq_write_ics(val);
2474	e1000e_set_interrupt_cause(core, val);
2475	}
2476
2477	static void
2478	e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2479	{
2480	if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2481	(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2482	trace_e1000e_irq_icr_process_iame();
2483	e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
2484	}
2485
2486	/*
2487	* Windows driver expects that the "receive overrun" bit and other
2488	* ones to be cleared when the "Other" bit (#24) is cleared.
2489	*/
2490	if (val & E1000_ICR_OTHER) {
2491	val \|= E1000_ICR_OTHER_CAUSES;
2492	}
2493	e1000e_lower_interrupts(core, ICR, val);
2494	}
2495
2496	static void
2497	e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2498	{
2499	trace_e1000e_irq_ims_clear_set_imc(val);
2500	e1000e_lower_interrupts(core, IMS, val);
2501	}
2502
2503	static void
2504	e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2505	{
2506	static const uint32_t ims_ext_mask =
2507	E1000_IMS_RXQ0 \| E1000_IMS_RXQ1 \|
2508	E1000_IMS_TXQ0 \| E1000_IMS_TXQ1 \|
2509	E1000_IMS_OTHER;
2510
2511	static const uint32_t ims_valid_mask =
2512	E1000_IMS_TXDW \| E1000_IMS_TXQE \| E1000_IMS_LSC \|
2513	E1000_IMS_RXDMT0 \| E1000_IMS_RXO \| E1000_IMS_RXT0 \|
2514	E1000_IMS_MDAC \| E1000_IMS_TXD_LOW \| E1000_IMS_SRPD \|
2515	E1000_IMS_ACK \| E1000_IMS_MNG \| E1000_IMS_RXQ0 \|
2516	E1000_IMS_RXQ1 \| E1000_IMS_TXQ0 \| E1000_IMS_TXQ1 \|
2517	E1000_IMS_OTHER;
2518
2519	uint32_t valid_val = val & ims_valid_mask;
2520
2521	if ((valid_val & ims_ext_mask) &&
2522	(core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2523	msix_enabled(core->owner)) {
2524	e1000e_msix_clear(core, valid_val);
2525	}
2526
2527	if ((valid_val == ims_valid_mask) &&
2528	(core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2529	trace_e1000e_irq_fire_all_timers(val);
2530	e1000e_intrmgr_fire_all_timers(core);
2531	}
2532
2533	e1000e_raise_interrupts(core, IMS, valid_val);
2534	}
2535
2536	static void
2537	e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2538	{
2539	e1000e_set_16bit(core, index, val);
2540
2541	if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2542	trace_e1000e_irq_rdtr_fpd_running();
2543	e1000e_intrmgr_fire_delayed_interrupts(core);
2544	} else {
2545	trace_e1000e_irq_rdtr_fpd_not_running();
2546	}
2547	}
2548
2549	static void
2550	e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2551	{
2552	e1000e_set_16bit(core, index, val);
2553
2554	if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2555	trace_e1000e_irq_tidv_fpd_running();
2556	e1000e_intrmgr_fire_delayed_interrupts(core);
2557	} else {
2558	trace_e1000e_irq_tidv_fpd_not_running();
2559	}
2560	}
2561
2562	static uint32_t
2563	e1000e_mac_readreg(E1000ECore *core, int index)
2564	{
2565	return core->mac[index];
2566	}
2567
2568	static uint32_t
2569	e1000e_mac_ics_read(E1000ECore *core, int index)
2570	{
2571	trace_e1000e_irq_read_ics(core->mac[ICS]);
2572	return core->mac[ICS];
2573	}
2574
2575	static uint32_t
2576	e1000e_mac_ims_read(E1000ECore *core, int index)
2577	{
2578	trace_e1000e_irq_read_ims(core->mac[IMS]);
2579	return core->mac[IMS];
2580	}
2581
2582	static uint32_t
2583	e1000e_mac_swsm_read(E1000ECore *core, int index)
2584	{
2585	uint32_t val = core->mac[SWSM];
2586	core->mac[SWSM] = val \| E1000_SWSM_SMBI;
2587	return val;
2588	}
2589
2590	static uint32_t
2591	e1000e_mac_itr_read(E1000ECore *core, int index)
2592	{
2593	return core->itr_guest_value;
2594	}
2595
2596	static uint32_t
2597	e1000e_mac_eitr_read(E1000ECore *core, int index)
2598	{
2599	return core->eitr_guest_value[index - EITR];
2600	}
2601
2602	static uint32_t
2603	e1000e_mac_icr_read(E1000ECore *core, int index)
2604	{
2605	uint32_t ret = core->mac[ICR];
2606
2607	if (core->mac[IMS] == 0) {
2608	trace_e1000e_irq_icr_clear_zero_ims();
2609	e1000e_lower_interrupts(core, ICR, 0xffffffff);
2610	}
2611
2612	if (!msix_enabled(core->owner)) {
2613	trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2614	e1000e_lower_interrupts(core, ICR, 0xffffffff);
2615	}
2616
2617	if (core->mac[ICR] & E1000_ICR_ASSERTED) {
2618	if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) {
2619	trace_e1000e_irq_icr_clear_iame();
2620	e1000e_lower_interrupts(core, ICR, 0xffffffff);
2621	trace_e1000e_irq_icr_process_iame();
2622	e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
2623	}
2624
2625	/*
2626	* The datasheet does not say what happens when interrupt was asserted
2627	* (ICR.INT_ASSERT=1) and auto mask is not active.
2628	* However, section of 13.3.27 the PCIe* GbE Controllers Open Source
2629	* Software Developer’s Manual, which were written for older devices,
2630	* namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI &
2631	* 82573E/82573V/82573L, does say:
2632	* > If IMS = 0b, then the ICR register is always clear-on-read. If IMS
2633	* > is not 0b, but some ICR bit is set where the corresponding IMS bit
2634	* > is not set, then a read does not clear the ICR register. For
2635	* > example, if IMS = 10101010b and ICR = 01010101b, then a read to the
2636	* > ICR register does not clear it. If IMS = 10101010b and
2637	* > ICR = 0101011b, then a read to the ICR register clears it entirely
2638	* > (ICR.INT_ASSERTED = 1b).
2639	*
2640	* Linux does no longer activate auto mask since commit
2641	* 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware
2642	* clears ICR even in such a case so we also should do so.
2643	*/
2644	if (core->mac[ICR] & core->mac[IMS]) {
2645	trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR],
2646	core->mac[IMS]);
2647	e1000e_lower_interrupts(core, ICR, 0xffffffff);
2648	}
2649	}
2650
2651	return ret;
2652	}
2653
2654	static uint32_t
2655	e1000e_mac_read_clr4(E1000ECore *core, int index)
2656	{
2657	uint32_t ret = core->mac[index];
2658
2659	core->mac[index] = 0;
2660	return ret;
2661	}
2662
2663	static uint32_t
2664	e1000e_mac_read_clr8(E1000ECore *core, int index)
2665	{
2666	uint32_t ret = core->mac[index];
2667
2668	core->mac[index] = 0;
2669	core->mac[index - 1] = 0;
2670	return ret;
2671	}
2672
2673	static uint32_t
2674	e1000e_get_ctrl(E1000ECore *core, int index)
2675	{
2676	uint32_t val = core->mac[CTRL];
2677
2678	trace_e1000e_link_read_params(
2679	!!(val & E1000_CTRL_ASDE),
2680	(val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2681	!!(val & E1000_CTRL_FRCSPD),
2682	!!(val & E1000_CTRL_FRCDPX),
2683	!!(val & E1000_CTRL_RFCE),
2684	!!(val & E1000_CTRL_TFCE));
2685
2686	return val;
2687	}
2688
2689	static uint32_t
2690	e1000e_get_status(E1000ECore *core, int index)
2691	{
2692	uint32_t res = core->mac[STATUS];
2693
2694	if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2695	res \|= E1000_STATUS_GIO_MASTER_ENABLE;
2696	}
2697
2698	if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2699	res \|= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2700	} else {
2701	res \|= E1000_STATUS_FD;
2702	}
2703
2704	if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) \|\|
2705	(core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2706	switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2707	case E1000_CTRL_SPD_10:
2708	res \|= E1000_STATUS_SPEED_10;
2709	break;
2710	case E1000_CTRL_SPD_100:
2711	res \|= E1000_STATUS_SPEED_100;
2712	break;
2713	case E1000_CTRL_SPD_1000:
2714	default:
2715	res \|= E1000_STATUS_SPEED_1000;
2716	break;
2717	}
2718	} else {
2719	res \|= E1000_STATUS_SPEED_1000;
2720	}
2721
2722	trace_e1000e_link_status(
2723	!!(res & E1000_STATUS_LU),
2724	!!(res & E1000_STATUS_FD),
2725	(res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2726	(res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2727
2728	return res;
2729	}
2730
2731	static uint32_t
2732	e1000e_get_tarc(E1000ECore *core, int index)
2733	{
2734	return core->mac[index] & ((BIT(11) - 1) \|
2735	BIT(27) \|
2736	BIT(28) \|
2737	BIT(29) \|
2738	BIT(30));
2739	}
2740
2741	static void
2742	e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2743	{
2744	core->mac[index] = val;
2745	}
2746
2747	static void
2748	e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2749	{
2750	uint32_t macaddr[2];
2751
2752	core->mac[index] = val;
2753
2754	macaddr[0] = cpu_to_le32(core->mac[RA]);
2755	macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2756	qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2757	(uint8_t *) macaddr);
2758
2759	trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2760	}
2761
2762	static void
2763	e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2764	{
2765	static const uint32_t ro_bits = E1000_EECD_PRES \|
2766	E1000_EECD_AUTO_RD \|
2767	E1000_EECD_SIZE_EX_MASK;
2768
2769	core->mac[EECD] = (core->mac[EECD] & ro_bits) \| (val & ~ro_bits);
2770	}
2771
2772	static void
2773	e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2774	{
2775	uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2776	uint32_t flags = 0;
2777	uint32_t data = 0;
2778
2779	if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2780	data = core->eeprom[addr];
2781	flags = E1000_EERW_DONE;
2782	}
2783
2784	core->mac[EERD] = flags \|
2785	(addr << E1000_EERW_ADDR_SHIFT) \|
2786	(data << E1000_EERW_DATA_SHIFT);
2787	}
2788
2789	static void
2790	e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2791	{
2792	uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2793	uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2794	uint32_t flags = 0;
2795
2796	if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2797	core->eeprom[addr] = data;
2798	flags = E1000_EERW_DONE;
2799	}
2800
2801	core->mac[EERD] = flags \|
2802	(addr << E1000_EERW_ADDR_SHIFT) \|
2803	(data << E1000_EERW_DATA_SHIFT);
2804	}
2805
2806	static void
2807	e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2808	{
2809	core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2810	}
2811
2812	static void
2813	e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2814	{
2815	uint32_t interval = val & 0xffff;
2816
2817	trace_e1000e_irq_itr_set(val);
2818
2819	core->itr_guest_value = interval;
2820	core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2821	}
2822
2823	static void
2824	e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2825	{
2826	uint32_t interval = val & 0xffff;
2827	uint32_t eitr_num = index - EITR;
2828
2829	trace_e1000e_irq_eitr_set(eitr_num, val);
2830
2831	core->eitr_guest_value[eitr_num] = interval;
2832	core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2833	}
2834
2835	static void
2836	e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2837	{
2838	if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2839
2840	if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2841	qemu_log_mask(LOG_GUEST_ERROR,
2842	"e1000e: PSRCTL.BSIZE0 cannot be zero");
2843	return;
2844	}
2845
2846	if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2847	qemu_log_mask(LOG_GUEST_ERROR,
2848	"e1000e: PSRCTL.BSIZE1 cannot be zero");
2849	return;
2850	}
2851	}
2852
2853	core->mac[PSRCTL] = val;
2854	}
2855
2856	static void
2857	e1000e_update_rx_offloads(E1000ECore *core)
2858	{
2859	int cso_state = e1000e_rx_l4_cso_enabled(core);
2860
2861	trace_e1000e_rx_set_cso(cso_state);
2862
2863	if (core->has_vnet) {
2864	NetOffloads ol = { .csum = cso_state };
2865
2866	qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, &ol);
2867	}
2868	}
2869
2870	static void
2871	e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2872	{
2873	core->mac[RXCSUM] = val;
2874	e1000e_update_rx_offloads(core);
2875	}
2876
2877	static void
2878	e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2879	{
2880	uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2881	core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) \| ro_bits;
2882	}
2883
2884	static uint32_t e1000e_get_systiml(E1000ECore *core, int index)
2885	{
2886	e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2887	return core->mac[SYSTIML];
2888	}
2889
2890	static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index)
2891	{
2892	core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2893	return core->mac[RXSATRH];
2894	}
2895
2896	static uint32_t e1000e_get_txstmph(E1000ECore *core, int index)
2897	{
2898	core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2899	return core->mac[TXSTMPH];
2900	}
2901
2902	static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val)
2903	{
2904	e1000x_set_timinca(core->mac, &core->timadj, val);
2905	}
2906
2907	static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val)
2908	{
2909	core->mac[TIMADJH] = val;
2910	core->timadj += core->mac[TIMADJL] \| ((int64_t)core->mac[TIMADJH] << 32);
2911	}
2912
2913	#define e1000e_getreg(x) [x] = e1000e_mac_readreg
2914	typedef uint32_t (readops)(E1000ECore , int);
2915	static const readops e1000e_macreg_readops[] = {
2916	e1000e_getreg(PBA),
2917	e1000e_getreg(WUFC),
2918	e1000e_getreg(MANC),
2919	e1000e_getreg(TOTL),
2920	e1000e_getreg(RDT0),
2921	e1000e_getreg(RDBAH0),
2922	e1000e_getreg(TDBAL1),
2923	e1000e_getreg(RDLEN0),
2924	e1000e_getreg(RDH1),
2925	e1000e_getreg(LATECOL),
2926	e1000e_getreg(SEQEC),
2927	e1000e_getreg(XONTXC),
2928	e1000e_getreg(AIT),
2929	e1000e_getreg(TDFH),
2930	e1000e_getreg(TDFT),
2931	e1000e_getreg(TDFHS),
2932	e1000e_getreg(TDFTS),
2933	e1000e_getreg(TDFPC),
2934	e1000e_getreg(WUS),
2935	e1000e_getreg(PBS),
2936	e1000e_getreg(RDFH),
2937	e1000e_getreg(RDFT),
2938	e1000e_getreg(RDFHS),
2939	e1000e_getreg(RDFTS),
2940	e1000e_getreg(RDFPC),
2941	e1000e_getreg(GORCL),
2942	e1000e_getreg(MGTPRC),
2943	e1000e_getreg(EERD),
2944	e1000e_getreg(EIAC),
2945	e1000e_getreg(PSRCTL),
2946	e1000e_getreg(MANC2H),
2947	e1000e_getreg(RXCSUM),
2948	e1000e_getreg(GSCL_3),
2949	e1000e_getreg(GSCN_2),
2950	e1000e_getreg(RSRPD),
2951	e1000e_getreg(RDBAL1),
2952	e1000e_getreg(FCAH),
2953	e1000e_getreg(FCRTH),
2954	e1000e_getreg(FLOP),
2955	e1000e_getreg(FLASHT),
2956	e1000e_getreg(RXSTMPH),
2957	e1000e_getreg(TXSTMPL),
2958	e1000e_getreg(TIMADJL),
2959	e1000e_getreg(TXDCTL),
2960	e1000e_getreg(RDH0),
2961	e1000e_getreg(TDT1),
2962	e1000e_getreg(TNCRS),
2963	e1000e_getreg(RJC),
2964	e1000e_getreg(IAM),
2965	e1000e_getreg(GSCL_2),
2966	e1000e_getreg(RDBAH1),
2967	e1000e_getreg(FLSWDATA),
2968	e1000e_getreg(TIPG),
2969	e1000e_getreg(FLMNGCTL),
2970	e1000e_getreg(FLMNGCNT),
2971	e1000e_getreg(TSYNCTXCTL),
2972	e1000e_getreg(EXTCNF_SIZE),
2973	e1000e_getreg(EXTCNF_CTRL),
2974	e1000e_getreg(EEMNGDATA),
2975	e1000e_getreg(CTRL_EXT),
2976	e1000e_getreg(SYSTIMH),
2977	e1000e_getreg(EEMNGCTL),
2978	e1000e_getreg(FLMNGDATA),
2979	e1000e_getreg(TSYNCRXCTL),
2980	e1000e_getreg(TDH),
2981	e1000e_getreg(LEDCTL),
2982	e1000e_getreg(TCTL),
2983	e1000e_getreg(TDBAL),
2984	e1000e_getreg(TDLEN),
2985	e1000e_getreg(TDH1),
2986	e1000e_getreg(RADV),
2987	e1000e_getreg(ECOL),
2988	e1000e_getreg(DC),
2989	e1000e_getreg(RLEC),
2990	e1000e_getreg(XOFFTXC),
2991	e1000e_getreg(RFC),
2992	e1000e_getreg(RNBC),
2993	e1000e_getreg(MGTPTC),
2994	e1000e_getreg(TIMINCA),
2995	e1000e_getreg(RXCFGL),
2996	e1000e_getreg(MFUTP01),
2997	e1000e_getreg(FACTPS),
2998	e1000e_getreg(GSCL_1),
2999	e1000e_getreg(GSCN_0),
3000	e1000e_getreg(GCR2),
3001	e1000e_getreg(RDT1),
3002	e1000e_getreg(PBACLR),
3003	e1000e_getreg(FCTTV),
3004	e1000e_getreg(EEWR),
3005	e1000e_getreg(FLSWCTL),
3006	e1000e_getreg(RXDCTL1),
3007	e1000e_getreg(RXSATRL),
3008	e1000e_getreg(RXUDP),
3009	e1000e_getreg(TORL),
3010	e1000e_getreg(TDLEN1),
3011	e1000e_getreg(MCC),
3012	e1000e_getreg(WUC),
3013	e1000e_getreg(EECD),
3014	e1000e_getreg(MFUTP23),
3015	e1000e_getreg(RAID),
3016	e1000e_getreg(FCRTV),
3017	e1000e_getreg(TXDCTL1),
3018	e1000e_getreg(RCTL),
3019	e1000e_getreg(TDT),
3020	e1000e_getreg(MDIC),
3021	e1000e_getreg(FCRUC),
3022	e1000e_getreg(VET),
3023	e1000e_getreg(RDBAL0),
3024	e1000e_getreg(TDBAH1),
3025	e1000e_getreg(RDTR),
3026	e1000e_getreg(SCC),
3027	e1000e_getreg(COLC),
3028	e1000e_getreg(CEXTERR),
3029	e1000e_getreg(XOFFRXC),
3030	e1000e_getreg(IPAV),
3031	e1000e_getreg(GOTCL),
3032	e1000e_getreg(MGTPDC),
3033	e1000e_getreg(GCR),
3034	e1000e_getreg(IVAR),
3035	e1000e_getreg(POEMB),
3036	e1000e_getreg(MFVAL),
3037	e1000e_getreg(FUNCTAG),
3038	e1000e_getreg(GSCL_4),
3039	e1000e_getreg(GSCN_3),
3040	e1000e_getreg(MRQC),
3041	e1000e_getreg(RDLEN1),
3042	e1000e_getreg(FCT),
3043	e1000e_getreg(FLA),
3044	e1000e_getreg(FLOL),
3045	e1000e_getreg(RXDCTL),
3046	e1000e_getreg(RXSTMPL),
3047	e1000e_getreg(TIMADJH),
3048	e1000e_getreg(FCRTL),
3049	e1000e_getreg(TDBAH),
3050	e1000e_getreg(TADV),
3051	e1000e_getreg(XONRXC),
3052	e1000e_getreg(TSCTFC),
3053	e1000e_getreg(RFCTL),
3054	e1000e_getreg(GSCN_1),
3055	e1000e_getreg(FCAL),
3056	e1000e_getreg(FLSWCNT),
3057
3058	[TOTH] = e1000e_mac_read_clr8,
3059	[GOTCH] = e1000e_mac_read_clr8,
3060	[PRC64] = e1000e_mac_read_clr4,
3061	[PRC255] = e1000e_mac_read_clr4,
3062	[PRC1023] = e1000e_mac_read_clr4,
3063	[PTC64] = e1000e_mac_read_clr4,
3064	[PTC255] = e1000e_mac_read_clr4,
3065	[PTC1023] = e1000e_mac_read_clr4,
3066	[GPRC] = e1000e_mac_read_clr4,
3067	[TPT] = e1000e_mac_read_clr4,
3068	[RUC] = e1000e_mac_read_clr4,
3069	[BPRC] = e1000e_mac_read_clr4,
3070	[MPTC] = e1000e_mac_read_clr4,
3071	[IAC] = e1000e_mac_read_clr4,
3072	[ICR] = e1000e_mac_icr_read,
3073	[STATUS] = e1000e_get_status,
3074	[TARC0] = e1000e_get_tarc,
3075	[ICS] = e1000e_mac_ics_read,
3076	[TORH] = e1000e_mac_read_clr8,
3077	[GORCH] = e1000e_mac_read_clr8,
3078	[PRC127] = e1000e_mac_read_clr4,
3079	[PRC511] = e1000e_mac_read_clr4,
3080	[PRC1522] = e1000e_mac_read_clr4,
3081	[PTC127] = e1000e_mac_read_clr4,
3082	[PTC511] = e1000e_mac_read_clr4,
3083	[PTC1522] = e1000e_mac_read_clr4,
3084	[GPTC] = e1000e_mac_read_clr4,
3085	[TPR] = e1000e_mac_read_clr4,
3086	[ROC] = e1000e_mac_read_clr4,
3087	[MPRC] = e1000e_mac_read_clr4,
3088	[BPTC] = e1000e_mac_read_clr4,
3089	[TSCTC] = e1000e_mac_read_clr4,
3090	[ITR] = e1000e_mac_itr_read,
3091	[CTRL] = e1000e_get_ctrl,
3092	[TARC1] = e1000e_get_tarc,
3093	[SWSM] = e1000e_mac_swsm_read,
3094	[IMS] = e1000e_mac_ims_read,
3095	[SYSTIML] = e1000e_get_systiml,
3096	[RXSATRH] = e1000e_get_rxsatrh,
3097	[TXSTMPH] = e1000e_get_txstmph,
3098
3099	[CRCERRS ... MPC] = e1000e_mac_readreg,
3100	[IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3101	[IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3102	[RA ... RA + 31] = e1000e_mac_readreg,
3103	[WUPM ... WUPM + 31] = e1000e_mac_readreg,
3104	[MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg,
3105	[VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg,
3106	[FFMT ... FFMT + 254] = e1000e_mac_readreg,
3107	[FFVT ... FFVT + 254] = e1000e_mac_readreg,
3108	[MDEF ... MDEF + 7] = e1000e_mac_readreg,
3109	[FFLT ... FFLT + 10] = e1000e_mac_readreg,
3110	[FTFT ... FTFT + 254] = e1000e_mac_readreg,
3111	[PBM ... PBM + 10239] = e1000e_mac_readreg,
3112	[RETA ... RETA + 31] = e1000e_mac_readreg,
3113	[RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3114	[MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3115	[EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3116	};
3117	enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3118
3119	#define e1000e_putreg(x) [x] = e1000e_mac_writereg
3120	typedef void (writeops)(E1000ECore , int, uint32_t);
3121	static const writeops e1000e_macreg_writeops[] = {
3122	e1000e_putreg(PBA),
3123	e1000e_putreg(SWSM),
3124	e1000e_putreg(WUFC),
3125	e1000e_putreg(RDBAH1),
3126	e1000e_putreg(TDBAH),
3127	e1000e_putreg(TXDCTL),
3128	e1000e_putreg(RDBAH0),
3129	e1000e_putreg(LEDCTL),
3130	e1000e_putreg(FCAL),
3131	e1000e_putreg(FCRUC),
3132	e1000e_putreg(WUC),
3133	e1000e_putreg(WUS),
3134	e1000e_putreg(IPAV),
3135	e1000e_putreg(TDBAH1),
3136	e1000e_putreg(IAM),
3137	e1000e_putreg(EIAC),
3138	e1000e_putreg(IVAR),
3139	e1000e_putreg(TARC0),
3140	e1000e_putreg(TARC1),
3141	e1000e_putreg(FLSWDATA),
3142	e1000e_putreg(POEMB),
3143	e1000e_putreg(MFUTP01),
3144	e1000e_putreg(MFUTP23),
3145	e1000e_putreg(MANC),
3146	e1000e_putreg(MANC2H),
3147	e1000e_putreg(MFVAL),
3148	e1000e_putreg(EXTCNF_CTRL),
3149	e1000e_putreg(FACTPS),
3150	e1000e_putreg(FUNCTAG),
3151	e1000e_putreg(GSCL_1),
3152	e1000e_putreg(GSCL_2),
3153	e1000e_putreg(GSCL_3),
3154	e1000e_putreg(GSCL_4),
3155	e1000e_putreg(GSCN_0),
3156	e1000e_putreg(GSCN_1),
3157	e1000e_putreg(GSCN_2),
3158	e1000e_putreg(GSCN_3),
3159	e1000e_putreg(GCR2),
3160	e1000e_putreg(MRQC),
3161	e1000e_putreg(FLOP),
3162	e1000e_putreg(FLOL),
3163	e1000e_putreg(FLSWCTL),
3164	e1000e_putreg(FLSWCNT),
3165	e1000e_putreg(FLA),
3166	e1000e_putreg(RXDCTL1),
3167	e1000e_putreg(TXDCTL1),
3168	e1000e_putreg(TIPG),
3169	e1000e_putreg(RXSTMPH),
3170	e1000e_putreg(RXSTMPL),
3171	e1000e_putreg(RXSATRL),
3172	e1000e_putreg(RXSATRH),
3173	e1000e_putreg(TXSTMPL),
3174	e1000e_putreg(TXSTMPH),
3175	e1000e_putreg(SYSTIML),
3176	e1000e_putreg(SYSTIMH),
3177	e1000e_putreg(TIMADJL),
3178	e1000e_putreg(RXUDP),
3179	e1000e_putreg(RXCFGL),
3180	e1000e_putreg(TSYNCRXCTL),
3181	e1000e_putreg(TSYNCTXCTL),
3182	e1000e_putreg(EXTCNF_SIZE),
3183	e1000e_putreg(EEMNGCTL),
3184	e1000e_putreg(RA),
3185
3186	[TDH1] = e1000e_set_16bit,
3187	[TDT1] = e1000e_set_tdt,
3188	[TCTL] = e1000e_set_tctl,
3189	[TDT] = e1000e_set_tdt,
3190	[MDIC] = e1000e_set_mdic,
3191	[ICS] = e1000e_set_ics,
3192	[TDH] = e1000e_set_16bit,
3193	[RDH0] = e1000e_set_16bit,
3194	[RDT0] = e1000e_set_rdt,
3195	[IMC] = e1000e_set_imc,
3196	[IMS] = e1000e_set_ims,
3197	[ICR] = e1000e_set_icr,
3198	[EECD] = e1000e_set_eecd,
3199	[RCTL] = e1000e_set_rx_control,
3200	[CTRL] = e1000e_set_ctrl,
3201	[RDTR] = e1000e_set_rdtr,
3202	[RADV] = e1000e_set_16bit,
3203	[TADV] = e1000e_set_16bit,
3204	[ITR] = e1000e_set_itr,
3205	[EERD] = e1000e_set_eerd,
3206	[AIT] = e1000e_set_16bit,
3207	[TDFH] = e1000e_set_13bit,
3208	[TDFT] = e1000e_set_13bit,
3209	[TDFHS] = e1000e_set_13bit,
3210	[TDFTS] = e1000e_set_13bit,
3211	[TDFPC] = e1000e_set_13bit,
3212	[RDFH] = e1000e_set_13bit,
3213	[RDFHS] = e1000e_set_13bit,
3214	[RDFT] = e1000e_set_13bit,
3215	[RDFTS] = e1000e_set_13bit,
3216	[RDFPC] = e1000e_set_13bit,
3217	[PBS] = e1000e_set_6bit,
3218	[GCR] = e1000e_set_gcr,
3219	[PSRCTL] = e1000e_set_psrctl,
3220	[RXCSUM] = e1000e_set_rxcsum,
3221	[RAID] = e1000e_set_16bit,
3222	[RSRPD] = e1000e_set_12bit,
3223	[TIDV] = e1000e_set_tidv,
3224	[TDLEN1] = e1000e_set_dlen,
3225	[TDLEN] = e1000e_set_dlen,
3226	[RDLEN0] = e1000e_set_dlen,
3227	[RDLEN1] = e1000e_set_dlen,
3228	[TDBAL] = e1000e_set_dbal,
3229	[TDBAL1] = e1000e_set_dbal,
3230	[RDBAL0] = e1000e_set_dbal,
3231	[RDBAL1] = e1000e_set_dbal,
3232	[RDH1] = e1000e_set_16bit,
3233	[RDT1] = e1000e_set_rdt,
3234	[STATUS] = e1000e_set_status,
3235	[PBACLR] = e1000e_set_pbaclr,
3236	[CTRL_EXT] = e1000e_set_ctrlext,
3237	[FCAH] = e1000e_set_16bit,
3238	[FCT] = e1000e_set_16bit,
3239	[FCTTV] = e1000e_set_16bit,
3240	[FCRTV] = e1000e_set_16bit,
3241	[FCRTH] = e1000e_set_fcrth,
3242	[FCRTL] = e1000e_set_fcrtl,
3243	[VET] = e1000e_set_vet,
3244	[RXDCTL] = e1000e_set_rxdctl,
3245	[FLASHT] = e1000e_set_16bit,
3246	[EEWR] = e1000e_set_eewr,
3247	[CTRL_DUP] = e1000e_set_ctrl,
3248	[RFCTL] = e1000e_set_rfctl,
3249	[RA + 1] = e1000e_mac_setmacaddr,
3250	[TIMINCA] = e1000e_set_timinca,
3251	[TIMADJH] = e1000e_set_timadjh,
3252
3253	[IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3254	[IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3255	[RA + 2 ... RA + 31] = e1000e_mac_writereg,
3256	[WUPM ... WUPM + 31] = e1000e_mac_writereg,
3257	[MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg,
3258	[VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg,
3259	[FFMT ... FFMT + 254] = e1000e_set_4bit,
3260	[FFVT ... FFVT + 254] = e1000e_mac_writereg,
3261	[PBM ... PBM + 10239] = e1000e_mac_writereg,
3262	[MDEF ... MDEF + 7] = e1000e_mac_writereg,
3263	[FFLT ... FFLT + 10] = e1000e_set_11bit,
3264	[FTFT ... FTFT + 254] = e1000e_mac_writereg,
3265	[RETA ... RETA + 31] = e1000e_mac_writereg,
3266	[RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3267	[MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3268	[EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3269	};
3270	enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3271
3272	enum { MAC_ACCESS_PARTIAL = 1 };
3273
3274	/*
3275	* The array below combines alias offsets of the index values for the
3276	* MAC registers that have aliases, with the indication of not fully
3277	* implemented registers (lowest bit). This combination is possible
3278	* because all of the offsets are even.
3279	*/
3280	static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3281	/* Alias index offsets */
3282	[FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3283	[RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3284	[RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3285	[TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3286	[TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3287	[RA_A ... RA_A + 31] = 0x14f0,
3288	[VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3289	[RDBAL0_A ... RDLEN0_A] = 0x09bc,
3290	[TDBAL_A ... TDLEN_A] = 0x0cf8,
3291	/* Access options */
3292	[RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3293	[RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3294	[RDFPC] = MAC_ACCESS_PARTIAL,
3295	[TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3296	[TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3297	[TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3298	[PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3299	[FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3300	[FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3301	[FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3302	[FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3303	[TXDCTL1] = MAC_ACCESS_PARTIAL,
3304	[MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3305	};
3306
3307	void
3308	e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3309	{
3310	uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3311
3312	if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3313	if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3314	trace_e1000e_wrn_regs_write_trivial(index << 2);
3315	}
3316	trace_e1000e_core_write(index << 2, size, val);
3317	e1000e_macreg_writeops[index](core, index, val);
3318	} else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3319	trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3320	} else {
3321	trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3322	}
3323	}
3324
3325	uint64_t
3326	e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3327	{
3328	uint64_t val;
3329	uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3330
3331	if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3332	if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3333	trace_e1000e_wrn_regs_read_trivial(index << 2);
3334	}
3335	val = e1000e_macreg_readops[index](core, index);
3336	trace_e1000e_core_read(index << 2, size, val);
3337	return val;
3338	} else {
3339	trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3340	}
3341	return 0;
3342	}
3343
3344	static void
3345	e1000e_autoneg_resume(E1000ECore *core)
3346	{
3347	if (e1000e_have_autoneg(core) &&
3348	!(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
3349	qemu_get_queue(core->owner_nic)->link_down = false;
3350	timer_mod(core->autoneg_timer,
3351	qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3352	}
3353	}
3354
3355	void
3356	e1000e_core_pci_realize(E1000ECore *core,
3357	const uint16_t *eeprom_templ,
3358	uint32_t eeprom_size,
3359	const uint8_t *macaddr)
3360	{
3361	int i;
3362
3363	core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3364	e1000e_autoneg_timer, core);
3365	e1000e_intrmgr_pci_realize(core);
3366
3367	for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3368	net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
3369	}
3370
3371	net_rx_pkt_init(&core->rx_pkt);
3372
3373	e1000x_core_prepare_eeprom(core->eeprom,
3374	eeprom_templ,
3375	eeprom_size,
3376	PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3377	macaddr);
3378	e1000e_update_rx_offloads(core);
3379	}
3380
3381	void
3382	e1000e_core_pci_uninit(E1000ECore *core)
3383	{
3384	int i;
3385
3386	timer_free(core->autoneg_timer);
3387
3388	e1000e_intrmgr_pci_unint(core);
3389
3390	for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3391	net_tx_pkt_uninit(core->tx[i].tx_pkt);
3392	}
3393
3394	net_rx_pkt_uninit(core->rx_pkt);
3395	}
3396
3397	static const uint16_t
3398	e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3399	[0] = {
3400	[MII_BMCR] = MII_BMCR_SPEED1000 \|
3401	MII_BMCR_FD \|
3402	MII_BMCR_AUTOEN,
3403
3404	[MII_BMSR] = MII_BMSR_EXTCAP \|
3405	MII_BMSR_LINK_ST \|
3406	MII_BMSR_AUTONEG \|
3407	MII_BMSR_MFPS \|
3408	MII_BMSR_EXTSTAT \|
3409	MII_BMSR_10T_HD \|
3410	MII_BMSR_10T_FD \|
3411	MII_BMSR_100TX_HD \|
3412	MII_BMSR_100TX_FD,
3413
3414	[MII_PHYID1] = 0x141,
3415	[MII_PHYID2] = E1000_PHY_ID2_82574x,
3416	[MII_ANAR] = MII_ANAR_CSMACD \| MII_ANAR_10 \|
3417	MII_ANAR_10FD \| MII_ANAR_TX \|
3418	MII_ANAR_TXFD \| MII_ANAR_PAUSE \|
3419	MII_ANAR_PAUSE_ASYM,
3420	[MII_ANLPAR] = MII_ANLPAR_10 \| MII_ANLPAR_10FD \|
3421	MII_ANLPAR_TX \| MII_ANLPAR_TXFD \|
3422	MII_ANLPAR_T4 \| MII_ANLPAR_PAUSE,
3423	[MII_ANER] = MII_ANER_NP \| MII_ANER_NWAY,
3424	[MII_ANNP] = 1 \| MII_ANNP_MP,
3425	[MII_CTRL1000] = MII_CTRL1000_HALF \| MII_CTRL1000_FULL \|
3426	MII_CTRL1000_PORT \| MII_CTRL1000_MASTER,
3427	[MII_STAT1000] = MII_STAT1000_HALF \| MII_STAT1000_FULL \|
3428	MII_STAT1000_ROK \| MII_STAT1000_LOK,
3429	[MII_EXTSTAT] = MII_EXTSTAT_1000T_HD \| MII_EXTSTAT_1000T_FD,
3430
3431	[PHY_COPPER_CTRL1] = BIT(5) \| BIT(6) \| BIT(8) \| BIT(9) \|
3432	BIT(12) \| BIT(13),
3433	[PHY_COPPER_STAT1] = BIT(3) \| BIT(10) \| BIT(11) \| BIT(13) \| BIT(15)
3434	},
3435	[2] = {
3436	[PHY_MAC_CTRL1] = BIT(3) \| BIT(7),
3437	[PHY_MAC_CTRL2] = BIT(1) \| BIT(2) \| BIT(6) \| BIT(12)
3438	},
3439	[3] = {
3440	[PHY_LED_TIMER_CTRL] = BIT(0) \| BIT(2) \| BIT(14)
3441	}
3442	};
3443
3444	static const uint32_t e1000e_mac_reg_init[] = {
3445	[PBA] = 0x00140014,
3446	[LEDCTL] = BIT(1) \| BIT(8) \| BIT(9) \| BIT(15) \| BIT(17) \| BIT(18),
3447	[EXTCNF_CTRL] = BIT(3),
3448	[EEMNGCTL] = BIT(31),
3449	[FLASHT] = 0x2,
3450	[FLSWCTL] = BIT(30) \| BIT(31),
3451	[FLOL] = BIT(0),
3452	[RXDCTL] = BIT(16),
3453	[RXDCTL1] = BIT(16),
3454	[TIPG] = 0x8 \| (0x8 << 10) \| (0x6 << 20),
3455	[RXCFGL] = 0x88F7,
3456	[RXUDP] = 0x319,
3457	[CTRL] = E1000_CTRL_FD \| E1000_CTRL_SWDPIN2 \| E1000_CTRL_SWDPIN0 \|
3458	E1000_CTRL_SPD_1000 \| E1000_CTRL_SLU \|
3459	E1000_CTRL_ADVD3WUC,
3460	[STATUS] = E1000_STATUS_ASDV_1000 \| E1000_STATUS_LU,
3461	[PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) \|
3462	(4 << E1000_PSRCTL_BSIZE1_SHIFT) \|
3463	(4 << E1000_PSRCTL_BSIZE2_SHIFT),
3464	[TARC0] = 0x3 \| E1000_TARC_ENABLE,
3465	[TARC1] = 0x3 \| E1000_TARC_ENABLE,
3466	[EECD] = E1000_EECD_AUTO_RD \| E1000_EECD_PRES,
3467	[EERD] = E1000_EERW_DONE,
3468	[EEWR] = E1000_EERW_DONE,
3469	[GCR] = E1000_L0S_ADJUST \|
3470	E1000_L1_ENTRY_LATENCY_MSB \|
3471	E1000_L1_ENTRY_LATENCY_LSB,
3472	[TDFH] = 0x600,
3473	[TDFT] = 0x600,
3474	[TDFHS] = 0x600,
3475	[TDFTS] = 0x600,
3476	[POEMB] = 0x30D,
3477	[PBS] = 0x028,
3478	[MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3479	[FACTPS] = E1000_FACTPS_LAN0_ON \| 0x20000000,
3480	[SWSM] = 1,
3481	[RXCSUM] = E1000_RXCSUM_IPOFLD \| E1000_RXCSUM_TUOFLD,
3482	[ITR] = E1000E_MIN_XITR,
3483	[EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3484	};
3485
3486	static void e1000e_reset(E1000ECore *core, bool sw)
3487	{
3488	int i;
3489
3490	timer_del(core->autoneg_timer);
3491
3492	e1000e_intrmgr_reset(core);
3493
3494	memset(core->phy, 0, sizeof core->phy);
3495	memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3496
3497	for (i = 0; i < E1000E_MAC_SIZE; i++) {
3498	if (sw && (i == PBA \|\| i == PBS \|\| i == FLA)) {
3499	continue;
3500	}
3501
3502	core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ?
3503	e1000e_mac_reg_init[i] : 0;
3504	}
3505
3506	core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3507
3508	if (qemu_get_queue(core->owner_nic)->link_down) {
3509	e1000e_link_down(core);
3510	}
3511
3512	e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3513
3514	for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3515	memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3516	core->tx[i].skip_cp = false;
3517	}
3518	}
3519
3520	void
3521	e1000e_core_reset(E1000ECore *core)
3522	{
3523	e1000e_reset(core, false);
3524	}
3525
3526	void e1000e_core_pre_save(E1000ECore *core)
3527	{
3528	int i;
3529	NetClientState *nc = qemu_get_queue(core->owner_nic);
3530
3531	/*
3532	* If link is down and auto-negotiation is supported and ongoing,
3533	* complete auto-negotiation immediately. This allows us to look
3534	* at MII_BMSR_AN_COMP to infer link status on load.
3535	*/
3536	if (nc->link_down && e1000e_have_autoneg(core)) {
3537	core->phy[0][MII_BMSR] \|= MII_BMSR_AN_COMP;
3538	e1000e_update_flowctl_status(core);
3539	}
3540
3541	for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3542	if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3543	core->tx[i].skip_cp = true;
3544	}
3545	}
3546	}
3547
3548	int
3549	e1000e_core_post_load(E1000ECore *core)
3550	{
3551	NetClientState *nc = qemu_get_queue(core->owner_nic);
3552
3553	/*
3554	* nc.link_down can't be migrated, so infer link_down according
3555	* to link status bit in core.mac[STATUS].
3556	*/
3557	nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3558
3559	/*
3560	* we need to restart intrmgr timers, as an older version of
3561	* QEMU can have stopped them before migration
3562	*/
3563	e1000e_intrmgr_resume(core);
3564	e1000e_autoneg_resume(core);
3565
3566	e1000e_calc_rxconf(core);
3567
3568	return 0;
3569	}