| 1 | /* |
| 2 | * QEMU Intel i82596 (Apricot) emulation |
| 3 | * |
| 4 | * Copyright (c) 2019 Helge Deller <deller@gmx.de> |
| 5 | * |
| 6 | * Additional functionality added by: |
| 7 | * Soumyajyotii Ssarkar <soumyajyotisarkar23@gmail.com> |
| 8 | * During GSOC 2025 under mentorship of Helge Deller. |
| 9 | * |
| 10 | * This work is licensed under the GNU GPL license version 2 or later. |
| 11 | * This software was written to be compatible with the specification: |
| 12 | * https://parisc.docs.kernel.org/en/latest/_downloads/96672be0650d9fc046bbcea40b92482f/82596CA.pdf |
| 13 | * |
| 14 | * INDEX: |
| 15 | * 1. Reset |
| 16 | * 2. Address Translation |
| 17 | * 3. Transmit functions |
| 18 | * 4. Receive Helper functions |
| 19 | * 5. Receive functions |
| 20 | * 6. Misc Functionality Functions |
| 21 | * 6.1 Individual Address |
| 22 | * 6.2 Multicast Address List |
| 23 | * 6.3 Link Status |
| 24 | * 6.4 CSMA/CD functions |
| 25 | * 6.5 Unified CRC Calculation |
| 26 | * 6.6 Unified Statistics Update |
| 27 | * 7. Bus Throttling Timer |
| 28 | * 8. Dump functions |
| 29 | * 9. Configure |
| 30 | * 10. Command Loop |
| 31 | * 11. Examine SCB |
| 32 | * 12. Channel attention (CA) |
| 33 | * 13. LASI interface |
| 34 | * 14. Polling functions |
| 35 | * 15. QOM and interface functions |
| 36 | * |
| 37 | */ |
| 38 | |
| 39 | #include "qemu/osdep.h" |
| 40 | #include "qemu/timer.h" |
| 41 | #include "net/net.h" |
| 42 | #include "net/eth.h" |
| 43 | #include "hw/core/irq.h" |
| 44 | #include "hw/core/qdev-properties.h" |
| 45 | #include "migration/vmstate.h" |
| 46 | #include "system/address-spaces.h" |
| 47 | #include "qemu/module.h" |
| 48 | #include "trace.h" |
| 49 | #include "i82596.h" |
| 50 | #include <zlib.h> /* for crc32 */ |
| 51 | |
| 52 | #define USE_TIMER 1 |
| 53 | |
| 54 | #define MAX_MC_CNT 64 |
| 55 | #define I596_NULL ((uint32_t)0xffffffff) |
| 56 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
| 57 | |
| 58 | #define SCB_STATUS_CX 0x8000 /* CU finished command with I bit */ |
| 59 | #define SCB_STATUS_FR 0x4000 /* RU finished receiving a frame */ |
| 60 | #define SCB_STATUS_CNA 0x2000 /* CU left active state */ |
| 61 | #define SCB_STATUS_RNR 0x1000 /* RU left active state */ |
| 62 | #define SCB_ACK_MASK 0xF000 /* All interrupt acknowledge bits */ |
| 63 | |
| 64 | /* 82596 Operational Modes */ |
| 65 | #define I82586_MODE 0x00 |
| 66 | #define I82596_MODE_SEGMENTED 0x01 |
| 67 | #define I82596_MODE_LINEAR 0x02 |
| 68 | |
| 69 | /* Monitor Options */ |
| 70 | #define MONITOR_NORMAL 0x00 |
| 71 | #define MONITOR_FILTERED 0x01 |
| 72 | #define MONITOR_ALL 0x02 |
| 73 | #define MONITOR_DISABLED 0x03 |
| 74 | |
| 75 | /* Operation mode flags from SYSBUS byte */ |
| 76 | #define SYSBUS_LOCK_EN 0x08 |
| 77 | #define SYSBUS_INT_ACTIVE_LOW 0x10 |
| 78 | #define SYSBUS_BIG_ENDIAN_32 0x80 |
| 79 | #define SYSBUS_THROTTLE_MASK 0x60 |
| 80 | |
| 81 | /* SCB commands - Command Unit (CU) */ |
| 82 | #define SCB_CUC_NOP 0x00 |
| 83 | #define SCB_CUC_START 0x01 |
| 84 | #define SCB_CUC_RESUME 0x02 |
| 85 | #define SCB_CUC_SUSPEND 0x03 |
| 86 | #define SCB_CUC_ABORT 0x04 |
| 87 | #define SCB_CUC_LOAD_THROTTLE 0x05 |
| 88 | #define SCB_CUC_LOAD_START 0x06 |
| 89 | |
| 90 | /* SCB commands - Receive Unit (RU) */ |
| 91 | #define SCB_RUC_NOP 0x00 |
| 92 | #define SCB_RUC_START 0x01 |
| 93 | #define SCB_RUC_RESUME 0x02 |
| 94 | #define SCB_RUC_SUSPEND 0x03 |
| 95 | #define SCB_RUC_ABORT 0x04 |
| 96 | |
| 97 | /* SCB statuses - Command Unit (CU) */ |
| 98 | #define CU_IDLE 0 |
| 99 | #define CU_SUSPENDED 1 |
| 100 | #define CU_ACTIVE 2 |
| 101 | |
| 102 | /* SCB statuses - Receive Unit (RU) */ |
| 103 | #define RX_IDLE 0x00 |
| 104 | #define RX_SUSPENDED 0x01 |
| 105 | #define RX_NO_RESOURCES 0x02 |
| 106 | #define RX_READY 0x04 |
| 107 | #define RX_NO_RESO_RBD 0x0A |
| 108 | #define RX_NO_MORE_RBD 0x0C |
| 109 | |
| 110 | #define CMD_FLEX 0x0008 |
| 111 | #define CMD_MASK 0x0007 |
| 112 | |
| 113 | #define CMD_EOL 0x8000 |
| 114 | #define CMD_SUSP 0x4000 |
| 115 | #define CMD_INTR 0x2000 |
| 116 | |
| 117 | #define ISCP_BUSY 0x01 |
| 118 | #define NANOSECONDS_PER_MICROSECOND 1000 |
| 119 | |
| 120 | #define DUMP_BUF_SZ 304 |
| 121 | |
| 122 | enum commands { |
| 123 | CmdNOp = 0, CmdSASetup = 1, CmdConfigure = 2, CmdMulticastList = 3, |
| 124 | CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7 |
| 125 | }; |
| 126 | |
| 127 | |
| 128 | #define STAT_C 0x8000 /* Set to 0 after execution */ |
| 129 | #define STAT_B 0x4000 /* Command being executed */ |
| 130 | #define STAT_OK 0x2000 /* Command executed ok */ |
| 131 | #define STAT_A 0x1000 /* Command aborted */ |
| 132 | |
| 133 | #define I596_EOF 0x8000 |
| 134 | #define SIZE_MASK 0x3fff |
| 135 | |
| 136 | #define CSMA_SLOT_TIME 51 |
| 137 | #define CSMA_MAX_RETRIES 16 |
| 138 | #define CSMA_BACKOFF_LIMIT 10 |
| 139 | |
| 140 | /* Global Flags fetched from config bytes */ |
| 141 | #define I596_PREFETCH (s->config[0] & 0x80) |
| 142 | #define SAVE_BAD_FRAMES (s->config[2] & 0x80) |
| 143 | #define I596_NO_SRC_ADD_IN (s->config[3] & 0x08) |
| 144 | #define I596_LOOPBACK (s->config[3] >> 6) |
| 145 | #define I596_PROMISC (s->config[8] & 0x01) |
| 146 | #define I596_BC_DISABLE (s->config[8] & 0x02) |
| 147 | #define I596_NOCRC_INS (s->config[8] & 0x08) |
| 148 | #define I596_CRC16_32 (s->config[8] & 0x10) |
| 149 | #define I596_PADDING (s->config[8] & 0x80) |
| 150 | #define I596_MIN_FRAME_LEN (s->config[10]) |
| 151 | #define I596_CRCINM (s->config[11] & 0x04) |
| 152 | #define I596_MONITOR_MODE ((s->config[11] >> 6) & 0x03) |
| 153 | #define I596_MC_ALL (s->config[11] & 0x20) |
| 154 | #define I596_FULL_DUPLEX (s->config[12] & 0x40) |
| 155 | #define I596_MULTIIA (s->config[13] & 0x40) |
| 156 | |
| 157 | /* RX Error flags */ |
| 158 | #define RX_COLLISIONS 0x0001 |
| 159 | #define RX_LENGTH_ERRORS 0x0080 |
| 160 | #define RX_OVER_ERRORS 0x0100 |
| 161 | #define RX_FIFO_ERRORS 0x0400 |
| 162 | #define RX_FRAME_ERRORS 0x0800 |
| 163 | #define RX_CRC_ERRORS 0x1000 |
| 164 | #define RX_LENGTH_ERRORS_ALT 0x2000 |
| 165 | #define RFD_STATUS_TRUNC 0x0020 |
| 166 | #define RFD_STATUS_NOBUFS 0x0200 |
| 167 | |
| 168 | /* TX Error flags */ |
| 169 | #define TX_COLLISIONS 0x0020 |
| 170 | #define TX_HEARTBEAT_ERRORS 0x0040 |
| 171 | #define TX_CARRIER_ERRORS 0x0400 |
| 172 | #define TX_COLLISIONS_ALT 0x0800 |
| 173 | #define TX_ABORTED_ERRORS 0x1000 |
| 174 | |
| 175 | static void i82596_update_scb_irq(I82596State *s, bool trigger); |
| 176 | static void i82596_update_cu_status(I82596State *s, uint16_t cmd_status, |
| 177 | bool generate_interrupt); |
| 178 | static void update_scb_status(I82596State *s); |
| 179 | static void examine_scb(I82596State *s); |
| 180 | static bool i82596_check_medium_status(I82596State *s); |
| 181 | static int i82596_csma_backoff(I82596State *s, int retry_count); |
| 182 | static uint16_t i82596_calculate_crc16(const uint8_t *data, size_t len); |
| 183 | static size_t i82596_append_crc(I82596State *s, uint8_t *buffer, size_t len); |
| 184 | static void i82596_bus_throttle_timer(void *opaque); |
| 185 | static void i82596_flush_queue_timer(void *opaque); |
| 186 | static int i82596_flush_packet_queue(I82596State *s); |
| 187 | static void i82596_update_statistics(I82596State *s, bool is_tx, |
| 188 | uint16_t error_flags, |
| 189 | uint16_t collision_count); |
| 190 | |
| 191 | static uint8_t get_byte(uint32_t addr) |
| 192 | { |
| 193 | return ldub_phys(&address_space_memory, addr); |
| 194 | } |
| 195 | |
| 196 | static void set_byte(uint32_t addr, uint8_t c) |
| 197 | { |
| 198 | return stb_phys(&address_space_memory, addr, c); |
| 199 | } |
| 200 | |
| 201 | static uint16_t get_uint16(uint32_t addr) |
| 202 | { |
| 203 | return lduw_be_phys(&address_space_memory, addr); |
| 204 | } |
| 205 | |
| 206 | static void set_uint16(uint32_t addr, uint16_t w) |
| 207 | { |
| 208 | return stw_be_phys(&address_space_memory, addr, w); |
| 209 | } |
| 210 | |
| 211 | static uint32_t get_uint32(uint32_t addr) |
| 212 | { |
| 213 | uint32_t lo = lduw_be_phys(&address_space_memory, addr); |
| 214 | uint32_t hi = lduw_be_phys(&address_space_memory, addr + 2); |
| 215 | return (hi << 16) | lo; |
| 216 | } |
| 217 | |
| 218 | static void set_uint32(uint32_t addr, uint32_t val) |
| 219 | { |
| 220 | set_uint16(addr, (uint16_t) val); |
| 221 | set_uint16(addr + 2, val >> 16); |
| 222 | } |
| 223 | |
| 224 | /* Centralized error detection and update mechanism */ |
| 225 | static void i82596_record_error(I82596State *s, uint16_t error_type, bool is_tx) |
| 226 | { |
| 227 | if (is_tx) { |
| 228 | if (error_type & TX_ABORTED_ERRORS) { |
| 229 | s->tx_aborted_errors++; |
| 230 | set_uint32(s->scb + 28, s->tx_aborted_errors); |
| 231 | } |
| 232 | } else { |
| 233 | if (error_type & RX_CRC_ERRORS) { |
| 234 | s->crc_err++; |
| 235 | set_uint32(s->scb + 16, s->crc_err); |
| 236 | } |
| 237 | |
| 238 | if (error_type & (RX_LENGTH_ERRORS | RX_LENGTH_ERRORS_ALT | |
| 239 | RX_FRAME_ERRORS)) { |
| 240 | s->align_err++; |
| 241 | set_uint32(s->scb + 18, s->align_err); |
| 242 | } |
| 243 | |
| 244 | if (error_type & RFD_STATUS_NOBUFS) { |
| 245 | s->resource_err++; |
| 246 | set_uint32(s->scb + 20, s->resource_err); |
| 247 | } |
| 248 | |
| 249 | if (error_type & (RX_OVER_ERRORS | RX_FIFO_ERRORS)) { |
| 250 | s->over_err++; |
| 251 | set_uint32(s->scb + 22, s->over_err); |
| 252 | } |
| 253 | |
| 254 | if (error_type & RFD_STATUS_TRUNC) { |
| 255 | s->short_fr_error++; |
| 256 | set_uint32(s->scb + 26, s->short_fr_error); |
| 257 | } |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | /* Packet Header Debugger */ |
| 262 | struct qemu_ether_header { |
| 263 | uint8_t ether_dhost[6]; |
| 264 | uint8_t ether_shost[6]; |
| 265 | uint16_t ether_type; |
| 266 | }; |
| 267 | |
| 268 | #define PRINT_PKTHDR(txt, BUF) do { \ |
| 269 | struct qemu_ether_header *hdr = (void *)(BUF); \ |
| 270 | printf(txt ": packet dhost=" MAC_FMT ", shost=" MAC_FMT ", type=0x%04x\n",\ |
| 271 | MAC_ARG(hdr->ether_dhost), MAC_ARG(hdr->ether_shost), \ |
| 272 | be16_to_cpu(hdr->ether_type)); \ |
| 273 | } while (0) |
| 274 | |
| 275 | static void i82596_cleanup(I82596State *s) |
| 276 | { |
| 277 | if (s->throttle_timer) { |
| 278 | timer_del(s->throttle_timer); |
| 279 | } |
| 280 | if (s->flush_queue_timer) { |
| 281 | timer_del(s->flush_queue_timer); |
| 282 | } |
| 283 | s->queue_head = 0; |
| 284 | s->queue_tail = 0; |
| 285 | s->queue_count = 0; |
| 286 | } |
| 287 | |
| 288 | static void i82596_s_reset(I82596State *s) |
| 289 | { |
| 290 | trace_i82596_s_reset(s); |
| 291 | i82596_cleanup(s); |
| 292 | |
| 293 | /* Clearing config bits */ |
| 294 | memset(s->config, 0, sizeof(s->config)); |
| 295 | s->scp = 0x00FFFFF4; |
| 296 | s->scb = 0; |
| 297 | s->scb_base = 0; |
| 298 | s->scb_status = 0; |
| 299 | s->cu_status = CU_IDLE; |
| 300 | s->rx_status = RX_IDLE; |
| 301 | s->cmd_p = I596_NULL; |
| 302 | s->lnkst = 0x8000; |
| 303 | s->ca = s->ca_active = 0; |
| 304 | s->send_irq = 0; |
| 305 | |
| 306 | /* Statistical Counters */ |
| 307 | s->crc_err = 0; |
| 308 | s->align_err = 0; |
| 309 | s->resource_err = 0; |
| 310 | s->over_err = 0; |
| 311 | s->rcvdt_err = 0; |
| 312 | s->short_fr_error = 0; |
| 313 | s->total_frames = 0; |
| 314 | s->total_good_frames = 0; |
| 315 | s->collision_events = 0; |
| 316 | s->total_collisions = 0; |
| 317 | s->tx_good_frames = 0; |
| 318 | s->tx_collisions = 0; |
| 319 | s->tx_aborted_errors = 0; |
| 320 | s->last_tx_len = 0; |
| 321 | |
| 322 | s->last_good_rfa = 0; |
| 323 | s->queue_head = 0; |
| 324 | s->queue_tail = 0; |
| 325 | s->queue_count = 0; |
| 326 | |
| 327 | s->t_on = 0xFFFF; |
| 328 | s->t_off = 0; |
| 329 | s->throttle_state = true; |
| 330 | |
| 331 | if (!s->throttle_timer) { |
| 332 | s->throttle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 333 | i82596_bus_throttle_timer, s); |
| 334 | } else { |
| 335 | timer_del(s->throttle_timer); |
| 336 | } |
| 337 | |
| 338 | if (!I596_FULL_DUPLEX && s->t_on != 0xFFFF) { |
| 339 | timer_mod(s->throttle_timer, |
| 340 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 341 | s->t_on * NANOSECONDS_PER_MICROSECOND); |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | void i82596_h_reset(void *opaque) |
| 346 | { |
| 347 | I82596State *s = opaque; |
| 348 | |
| 349 | i82596_s_reset(s); |
| 350 | } |
| 351 | |
| 352 | /* |
| 353 | * Mode Transition of address functionality. |
| 354 | * Note: As of now the 82596 is tested only for Linear Mode as it is most |
| 355 | * widely used by Linux and HPUX systems. This function is here for |
| 356 | * futureproofing our 82596 device model. |
| 357 | * According to the documentation the translation of addresses based on mode |
| 358 | * are done for the following cases: ISCP, SCB, CBP, RFD, TFD, |
| 359 | * RBD, TBD, Rx Buffers, Tx Buffers |
| 360 | * Please refer to the documentation for more details. |
| 361 | */ |
| 362 | static uint32_t i82596_translate_address(I82596State *s, |
| 363 | uint32_t addr, |
| 364 | bool is_data_buffer) |
| 365 | { |
| 366 | if (addr == I596_NULL || addr == 0) { |
| 367 | return addr; |
| 368 | } |
| 369 | switch (s->mode) { |
| 370 | case I82586_MODE: |
| 371 | if (is_data_buffer) { |
| 372 | return addr & 0x00FFFFFF; |
| 373 | } else { |
| 374 | if (s->scb_base) { |
| 375 | return (s->scb_base & 0x00FFFFFF) + (addr & 0xFFFF); |
| 376 | } else { |
| 377 | return addr & 0x00FFFFFF; |
| 378 | } |
| 379 | } |
| 380 | break; |
| 381 | case I82596_MODE_SEGMENTED: |
| 382 | if (is_data_buffer) { |
| 383 | return addr; |
| 384 | } else { |
| 385 | if (s->scb_base) { |
| 386 | return s->scb_base + (addr & 0xFFFF); |
| 387 | } else { |
| 388 | return addr; |
| 389 | } |
| 390 | } |
| 391 | break; |
| 392 | case I82596_MODE_LINEAR: |
| 393 | default: |
| 394 | return addr; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | /* (TFD) Transmit Frame Descriptor */ |
| 399 | struct i82596_tx_descriptor { |
| 400 | uint16_t status_bits; |
| 401 | uint16_t command; |
| 402 | uint32_t link_addr; |
| 403 | uint32_t tbd_addr; |
| 404 | uint16_t tcb_count; |
| 405 | uint8_t dest_addr[6]; |
| 406 | uint16_t length_field; |
| 407 | }; |
| 408 | |
| 409 | /* (TBD) Transmit Buffer Descriptor */ |
| 410 | struct i82596_tx_buffer_desc { |
| 411 | uint16_t size; |
| 412 | uint32_t link; |
| 413 | uint32_t buffer; |
| 414 | }; |
| 415 | |
| 416 | /* (RFD) Receive Frame Descriptor */ |
| 417 | struct i82596_rx_descriptor { |
| 418 | uint16_t status_bits; |
| 419 | uint16_t command; |
| 420 | uint32_t link; |
| 421 | uint32_t rbd_addr; |
| 422 | uint16_t actual_count; |
| 423 | uint16_t size; |
| 424 | uint8_t dest_addr[6]; |
| 425 | uint8_t src_addr[6]; |
| 426 | uint16_t length_field; |
| 427 | }; |
| 428 | |
| 429 | /* (RBD) Receive Buffer Descriptor */ |
| 430 | struct i82596_rx_buffer_desc { |
| 431 | uint16_t actual_count; |
| 432 | uint32_t next_rbd_addr; |
| 433 | uint32_t buffer_addr; |
| 434 | uint16_t size; |
| 435 | }; |
| 436 | |
| 437 | static void i82596_tx_tfd_read(I82596State *s, hwaddr addr, |
| 438 | struct i82596_tx_descriptor *desc) |
| 439 | { |
| 440 | desc->status_bits = get_uint16(addr + 0); |
| 441 | desc->command = get_uint16(addr + 2); |
| 442 | desc->link_addr = get_uint32(addr + 4); |
| 443 | desc->tbd_addr = get_uint32(addr + 8); |
| 444 | desc->tcb_count = get_uint16(addr + 12); |
| 445 | address_space_read(&address_space_memory, addr + 14, |
| 446 | MEMTXATTRS_UNSPECIFIED, desc->dest_addr, 6); |
| 447 | desc->length_field = get_uint16(addr + 20); |
| 448 | } |
| 449 | |
| 450 | static void i82596_tx_tfd_write(I82596State *s, hwaddr addr, |
| 451 | struct i82596_tx_descriptor *desc) |
| 452 | { |
| 453 | set_uint16(addr + 0, desc->status_bits); |
| 454 | set_uint16(addr + 2, desc->command); |
| 455 | set_uint32(addr + 4, desc->link_addr); |
| 456 | set_uint32(addr + 8, desc->tbd_addr); |
| 457 | set_uint16(addr + 12, desc->tcb_count); |
| 458 | address_space_write(&address_space_memory, addr + 14, |
| 459 | MEMTXATTRS_UNSPECIFIED, desc->dest_addr, 6); |
| 460 | set_uint16(addr + 20, desc->length_field); |
| 461 | } |
| 462 | |
| 463 | static void i82596_tbd_read(I82596State *s, hwaddr addr, |
| 464 | struct i82596_tx_buffer_desc *tbd) |
| 465 | { |
| 466 | tbd->size = get_uint16(addr + 0); |
| 467 | tbd->link = get_uint32(addr + 4); |
| 468 | tbd->buffer = get_uint32(addr + 8); |
| 469 | } |
| 470 | |
| 471 | static void i82596_rx_rfd_read(I82596State *s, hwaddr addr, |
| 472 | struct i82596_rx_descriptor *desc) |
| 473 | { |
| 474 | desc->status_bits = get_uint16(addr + 0x0); |
| 475 | desc->command = get_uint16(addr + 0x2); |
| 476 | desc->link = get_uint32(addr + 0x4); |
| 477 | desc->rbd_addr = get_uint32(addr + 0x8); |
| 478 | desc->actual_count = get_uint16(addr + 0xC); |
| 479 | desc->size = get_uint16(addr + 0xE); |
| 480 | |
| 481 | address_space_read(&address_space_memory, addr + 0x10, |
| 482 | MEMTXATTRS_UNSPECIFIED, desc->dest_addr, 6); |
| 483 | address_space_read(&address_space_memory, addr + 0x16, |
| 484 | MEMTXATTRS_UNSPECIFIED, desc->src_addr, 6); |
| 485 | desc->length_field = get_uint16(addr + 28); |
| 486 | } |
| 487 | |
| 488 | static void i82596_rx_desc_write(I82596State *s, hwaddr addr, |
| 489 | struct i82596_rx_descriptor *desc, |
| 490 | bool write_full) |
| 491 | { |
| 492 | set_uint16(addr + 0x0, desc->status_bits); |
| 493 | set_uint16(addr + 0xC, desc->actual_count); |
| 494 | |
| 495 | if (write_full) { |
| 496 | set_uint16(addr + 0x2, desc->command); |
| 497 | set_uint32(addr + 0x4, desc->link); |
| 498 | set_uint32(addr + 0x8, desc->rbd_addr); |
| 499 | set_uint16(addr + 0xE, desc->size); |
| 500 | |
| 501 | address_space_write(&address_space_memory, addr + 0x10, |
| 502 | MEMTXATTRS_UNSPECIFIED, desc->dest_addr, 6); |
| 503 | address_space_write(&address_space_memory, addr + 0x16, |
| 504 | MEMTXATTRS_UNSPECIFIED, desc->src_addr, 6); |
| 505 | set_uint16(addr + 0x1C, desc->length_field); |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | static void i82596_rbd_read(I82596State *s, hwaddr addr, |
| 510 | struct i82596_rx_buffer_desc *rbd) |
| 511 | { |
| 512 | rbd->actual_count = get_uint16(addr + 0x0); |
| 513 | rbd->next_rbd_addr = get_uint32(addr + 0x4); |
| 514 | rbd->buffer_addr = get_uint32(addr + 0x8); |
| 515 | rbd->size = get_uint16(addr + 0xC); |
| 516 | } |
| 517 | |
| 518 | static void i82596_rbd_write(I82596State *s, hwaddr addr, |
| 519 | struct i82596_rx_buffer_desc *rbd) |
| 520 | { |
| 521 | set_uint16(addr + 0x0, rbd->actual_count); |
| 522 | set_uint32(addr + 0x4, rbd->next_rbd_addr); |
| 523 | set_uint32(addr + 0x8, rbd->buffer_addr); |
| 524 | set_uint16(addr + 0xC, rbd->size); |
| 525 | } |
| 526 | |
| 527 | static int i82596_tx_copy_buffers(I82596State *s, hwaddr tfd_addr, |
| 528 | struct i82596_tx_descriptor *desc) |
| 529 | { |
| 530 | bool simplified_mode = !(desc->command & CMD_FLEX); |
| 531 | uint32_t total_len = 0; |
| 532 | uint32_t tbd_addr; |
| 533 | struct i82596_tx_buffer_desc tbd; |
| 534 | |
| 535 | s->tx_frame_len = 0; |
| 536 | |
| 537 | if (simplified_mode) { |
| 538 | uint16_t frame_len = desc->tcb_count & SIZE_MASK; |
| 539 | if (frame_len == 0 || frame_len > sizeof(s->tx_buffer)) { |
| 540 | return -1; |
| 541 | } |
| 542 | address_space_read(&address_space_memory, tfd_addr + 16, |
| 543 | MEMTXATTRS_UNSPECIFIED, s->tx_buffer, frame_len); |
| 544 | total_len = frame_len; |
| 545 | |
| 546 | } else { |
| 547 | tbd_addr = desc->tbd_addr; |
| 548 | while (tbd_addr != I596_NULL && tbd_addr != 0) { |
| 549 | uint16_t buf_size; |
| 550 | uint32_t buf_addr; |
| 551 | tbd_addr = i82596_translate_address(s, tbd_addr, false); |
| 552 | if (tbd_addr == 0 || tbd_addr == I596_NULL) { |
| 553 | return -1; |
| 554 | } |
| 555 | i82596_tbd_read(s, tbd_addr, &tbd); |
| 556 | trace_i82596_tx_tbd(tbd_addr, tbd.size, tbd.buffer); |
| 557 | buf_size = tbd.size & SIZE_MASK; |
| 558 | buf_addr = i82596_translate_address(s, tbd.buffer, true); |
| 559 | |
| 560 | if (total_len + buf_size > sizeof(s->tx_buffer)) { |
| 561 | return -1; |
| 562 | } |
| 563 | |
| 564 | if (buf_size > 0 && buf_addr != 0 && buf_addr != I596_NULL) { |
| 565 | address_space_read(&address_space_memory, buf_addr, |
| 566 | MEMTXATTRS_UNSPECIFIED, |
| 567 | s->tx_buffer + total_len, buf_size); |
| 568 | total_len += buf_size; |
| 569 | } |
| 570 | if (tbd.size & I596_EOF) { |
| 571 | break; |
| 572 | } |
| 573 | tbd_addr = tbd.link; |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | s->tx_frame_len = total_len; |
| 578 | return total_len; |
| 579 | } |
| 580 | |
| 581 | static int i82596_tx_process_frame(I82596State *s, bool insert_crc) |
| 582 | { |
| 583 | uint32_t total_len = s->tx_frame_len; |
| 584 | |
| 585 | if (total_len == 0) { |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | if (I596_NO_SRC_ADD_IN == 0 && total_len >= ETH_ALEN * 2) { |
| 590 | memcpy(&s->tx_buffer[ETH_ALEN], s->conf.macaddr.a, ETH_ALEN); |
| 591 | } |
| 592 | |
| 593 | if (I596_PADDING && total_len < I596_MIN_FRAME_LEN) { |
| 594 | size_t pad_len = I596_MIN_FRAME_LEN - total_len; |
| 595 | memset(s->tx_buffer + total_len, 0, pad_len); |
| 596 | total_len = I596_MIN_FRAME_LEN; |
| 597 | } |
| 598 | |
| 599 | if (insert_crc) { |
| 600 | total_len = i82596_append_crc(s, s->tx_buffer, total_len); |
| 601 | } |
| 602 | |
| 603 | s->tx_frame_len = total_len; |
| 604 | return total_len; |
| 605 | } |
| 606 | |
| 607 | static void i82596_tx_update_status(I82596State *s, hwaddr tfd_addr, |
| 608 | struct i82596_tx_descriptor *desc, |
| 609 | uint16_t tx_status, |
| 610 | uint16_t collision_count, |
| 611 | bool success) |
| 612 | { |
| 613 | desc->status_bits = STAT_C; |
| 614 | |
| 615 | if (success) { |
| 616 | desc->status_bits |= STAT_OK; |
| 617 | } else { |
| 618 | desc->status_bits |= STAT_A; |
| 619 | } |
| 620 | |
| 621 | if (collision_count > 0) { |
| 622 | desc->status_bits |= (collision_count & 0x0F); |
| 623 | } |
| 624 | |
| 625 | i82596_tx_tfd_write(s, tfd_addr, desc); |
| 626 | } |
| 627 | |
| 628 | static int i82596_tx_csma_cd(I82596State *s, uint16_t *tx_status) |
| 629 | { |
| 630 | int retry_count = 0; |
| 631 | bool medium_available; |
| 632 | |
| 633 | if (I596_FULL_DUPLEX || I596_LOOPBACK) { |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | while (retry_count < CSMA_MAX_RETRIES) { |
| 638 | medium_available = i82596_check_medium_status(s); |
| 639 | |
| 640 | if (medium_available) { |
| 641 | break; |
| 642 | } |
| 643 | i82596_csma_backoff(s, retry_count); |
| 644 | retry_count++; |
| 645 | s->total_collisions++; |
| 646 | } |
| 647 | if (retry_count >= CSMA_MAX_RETRIES) { |
| 648 | *tx_status |= TX_ABORTED_ERRORS; |
| 649 | return -1; |
| 650 | } |
| 651 | if (retry_count > 0) { |
| 652 | *tx_status |= TX_COLLISIONS; |
| 653 | s->collision_events++; |
| 654 | } |
| 655 | |
| 656 | return retry_count; |
| 657 | } |
| 658 | |
| 659 | static void i82596_transmit(I82596State *s, uint32_t addr) |
| 660 | { |
| 661 | struct i82596_tx_descriptor tfd; |
| 662 | hwaddr tfd_addr = addr; |
| 663 | uint16_t tx_status = 0; |
| 664 | int collision_count = 0; |
| 665 | int frame_len; |
| 666 | bool success = true; |
| 667 | bool insert_crc; |
| 668 | |
| 669 | i82596_tx_tfd_read(s, tfd_addr, &tfd); |
| 670 | trace_i82596_tx_tfd(tfd_addr, tfd.status_bits, tfd.command, |
| 671 | tfd.link_addr, tfd.tbd_addr); |
| 672 | |
| 673 | s->current_tx_desc = tfd_addr; |
| 674 | insert_crc = (I596_NOCRC_INS == 0) && ((tfd.command & 0x10) == 0) && |
| 675 | !I596_LOOPBACK; |
| 676 | collision_count = i82596_tx_csma_cd(s, &tx_status); |
| 677 | if (collision_count < 0) { |
| 678 | success = false; |
| 679 | goto tx_complete; |
| 680 | } |
| 681 | frame_len = i82596_tx_copy_buffers(s, tfd_addr, &tfd); |
| 682 | if (frame_len < 0) { |
| 683 | tx_status |= TX_ABORTED_ERRORS; |
| 684 | success = false; |
| 685 | goto tx_complete; |
| 686 | } |
| 687 | frame_len = i82596_tx_process_frame(s, insert_crc); |
| 688 | if (frame_len <= 0) { |
| 689 | tx_status |= TX_ABORTED_ERRORS; |
| 690 | success = false; |
| 691 | goto tx_complete; |
| 692 | } |
| 693 | s->last_tx_len = frame_len; |
| 694 | trace_i82596_transmit(frame_len, addr); |
| 695 | |
| 696 | if (I596_LOOPBACK) { |
| 697 | i82596_receive(qemu_get_queue(s->nic), s->tx_buffer, frame_len); |
| 698 | } else { |
| 699 | if (s->nic) { |
| 700 | qemu_send_packet_raw(qemu_get_queue(s->nic), s->tx_buffer, |
| 701 | frame_len); |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | tx_complete: |
| 706 | i82596_tx_update_status(s, tfd_addr, &tfd, tx_status, collision_count, |
| 707 | success); |
| 708 | i82596_update_statistics(s, true, tx_status, collision_count); |
| 709 | if (tfd.command & CMD_INTR) { |
| 710 | i82596_update_cu_status(s, tfd.status_bits, true); |
| 711 | } |
| 712 | } |
| 713 | |
| 714 | bool i82596_can_receive(NetClientState *nc) |
| 715 | { |
| 716 | I82596State *s = qemu_get_nic_opaque(nc); |
| 717 | |
| 718 | if (I596_LOOPBACK || !s->lnkst) { |
| 719 | return false; |
| 720 | } |
| 721 | |
| 722 | if (s->rx_status == RX_SUSPENDED || s->rx_status == RX_IDLE || |
| 723 | s->rx_status == RX_NO_RESOURCES) { |
| 724 | return true; |
| 725 | } |
| 726 | |
| 727 | if (!s->throttle_state && !I596_FULL_DUPLEX) { |
| 728 | return (s->queue_count < PACKET_QUEUE_SIZE); |
| 729 | } |
| 730 | |
| 731 | return true; |
| 732 | } |
| 733 | |
| 734 | static int i82596_validate_receive_state(I82596State *s, size_t *sz, |
| 735 | bool from_queue) |
| 736 | { |
| 737 | if (*sz < 14 || *sz > PKT_BUF_SZ - 4) { |
| 738 | trace_i82596_receive_analysis(">>> Packet size invalid"); |
| 739 | return -1; |
| 740 | } |
| 741 | |
| 742 | if (!from_queue && s->rx_status == RX_SUSPENDED) { |
| 743 | trace_i82596_receive_analysis(">>> Receiving is suspended"); |
| 744 | return -1; |
| 745 | } |
| 746 | |
| 747 | if (s->rx_status != RX_READY && s->rx_status != RX_SUSPENDED) { |
| 748 | trace_i82596_receive_analysis(">>> RU not ready"); |
| 749 | return -1; |
| 750 | } |
| 751 | |
| 752 | if (!s->lnkst) { |
| 753 | trace_i82596_receive_analysis(">>> Link is down"); |
| 754 | return -1; |
| 755 | } |
| 756 | |
| 757 | return 1; |
| 758 | } |
| 759 | |
| 760 | static bool i82596_check_packet_filter(I82596State *s, const uint8_t *buf, |
| 761 | uint16_t *is_broadcast) |
| 762 | { |
| 763 | static const uint8_t broadcast_macaddr[6] = { |
| 764 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 765 | |
| 766 | if (I596_PROMISC || I596_LOOPBACK) { |
| 767 | trace_i82596_receive_analysis( |
| 768 | ">>> packet received in promiscuous mode"); |
| 769 | return true; |
| 770 | } else { |
| 771 | if (!memcmp(buf, broadcast_macaddr, 6)) { |
| 772 | /* broadcast address */ |
| 773 | if (I596_BC_DISABLE) { |
| 774 | trace_i82596_receive_analysis(">>> broadcast packet rejected"); |
| 775 | return false; |
| 776 | } |
| 777 | trace_i82596_receive_analysis(">>> broadcast packet received"); |
| 778 | *is_broadcast = 1; |
| 779 | return true; |
| 780 | } else if (buf[0] & 0x01) { |
| 781 | /* multicast */ |
| 782 | if (!I596_MC_ALL) { |
| 783 | trace_i82596_receive_analysis(">>> multicast packet rejected"); |
| 784 | return false; |
| 785 | } |
| 786 | |
| 787 | int mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2; |
| 788 | assert(mcast_idx < 8 * sizeof(s->mult)); |
| 789 | |
| 790 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
| 791 | trace_i82596_receive_analysis(">>> multicast address mismatch"); |
| 792 | return false; |
| 793 | } |
| 794 | |
| 795 | trace_i82596_receive_analysis(">>> multicast packet received"); |
| 796 | *is_broadcast = 1; |
| 797 | return true; |
| 798 | } else if (!memcmp(s->conf.macaddr.a, buf, 6)) { |
| 799 | /* match */ |
| 800 | trace_i82596_receive_analysis( |
| 801 | ">>> physical address matching packet received"); |
| 802 | return true; |
| 803 | } else { |
| 804 | trace_i82596_receive_analysis(">>> unknown packet"); |
| 805 | return false; |
| 806 | } |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | /* MONITOR MODE */ |
| 811 | static bool i82596_monitor(I82596State *s, const uint8_t *buf, size_t sz, |
| 812 | bool packet_passes_filter) |
| 813 | { |
| 814 | if (I596_MONITOR_MODE == MONITOR_DISABLED) { |
| 815 | return true; |
| 816 | } |
| 817 | if (sz < I596_MIN_FRAME_LEN) { |
| 818 | s->short_fr_error++; |
| 819 | } |
| 820 | if ((sz % 2) != 0) { |
| 821 | s->align_err++; |
| 822 | } |
| 823 | |
| 824 | switch (I596_MONITOR_MODE) { |
| 825 | case MONITOR_NORMAL: /* No monitor, just add to total frames */ |
| 826 | if (packet_passes_filter) { |
| 827 | s->total_good_frames++; |
| 828 | return true; |
| 829 | } else { |
| 830 | return false; |
| 831 | } |
| 832 | break; |
| 833 | case MONITOR_FILTERED: /* Monitor only filtered packets */ |
| 834 | s->total_frames++; |
| 835 | if (packet_passes_filter) { |
| 836 | s->total_good_frames++; |
| 837 | } |
| 838 | return false; |
| 839 | case MONITOR_ALL: /* Monitor all packets */ |
| 840 | s->total_frames++; |
| 841 | if (packet_passes_filter) { |
| 842 | s->total_good_frames++; |
| 843 | } |
| 844 | return false; |
| 845 | |
| 846 | default: |
| 847 | return true; |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | static void i82596_update_rx_state(I82596State *s, int new_state) |
| 852 | { |
| 853 | if (s->rx_status != new_state) { |
| 854 | trace_i82596_rx_state_change(s->rx_status, new_state); |
| 855 | } |
| 856 | |
| 857 | s->rx_status = new_state; |
| 858 | |
| 859 | switch (new_state) { |
| 860 | case RX_NO_RESOURCES: |
| 861 | if (!s->rnr_signaled) { |
| 862 | s->scb_status |= SCB_STATUS_RNR; |
| 863 | s->rnr_signaled = true; |
| 864 | } |
| 865 | break; |
| 866 | case RX_SUSPENDED: |
| 867 | if (!s->rnr_signaled) { |
| 868 | s->scb_status |= SCB_STATUS_RNR; |
| 869 | s->rnr_signaled = true; |
| 870 | } |
| 871 | |
| 872 | if (s->queue_count > 0 && !s->flushing_queue) { |
| 873 | i82596_flush_packet_queue(s); |
| 874 | if (s->queue_count > 0) { |
| 875 | timer_mod(s->flush_queue_timer, |
| 876 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); |
| 877 | } |
| 878 | } |
| 879 | break; |
| 880 | case RX_READY: |
| 881 | /* When RU becomes ready, flush buffered packets */ |
| 882 | if (s->queue_count > 0) { |
| 883 | i82596_flush_packet_queue(s); |
| 884 | } |
| 885 | break; |
| 886 | default: |
| 887 | break; |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | static void i82596_rx_store_frame_header(I82596State *s, |
| 892 | struct i82596_rx_descriptor *rfd, |
| 893 | const uint8_t *buf, size_t size) |
| 894 | { |
| 895 | memcpy(rfd->dest_addr, buf, 6); |
| 896 | if (size >= 12) { |
| 897 | memcpy(rfd->src_addr, buf + 6, 6); |
| 898 | } |
| 899 | if (size >= 14) { |
| 900 | rfd->length_field = (buf[12] << 8) | buf[13]; |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | static size_t i82596_rx_copy_to_rfd(I82596State *s, hwaddr rfd_addr, |
| 905 | const uint8_t *buf, size_t size, |
| 906 | size_t rfd_size) |
| 907 | { |
| 908 | size_t to_copy = MIN(size, rfd_size); |
| 909 | size_t data_offset = 0x1E; /* Bypassing the header */ |
| 910 | |
| 911 | if (to_copy > 0) { |
| 912 | address_space_write(&address_space_memory, rfd_addr + data_offset, |
| 913 | MEMTXATTRS_UNSPECIFIED, buf, to_copy); |
| 914 | } |
| 915 | return to_copy; |
| 916 | } |
| 917 | |
| 918 | static size_t i82596_rx_copy_to_rbds(I82596State *s, hwaddr rbd_addr, |
| 919 | const uint8_t *buf, size_t size, |
| 920 | bool *out_of_resources, |
| 921 | hwaddr *remaining_rbd) |
| 922 | { |
| 923 | size_t bytes_copied = 0; |
| 924 | hwaddr current_rbd = rbd_addr; |
| 925 | *out_of_resources = false; |
| 926 | *remaining_rbd = I596_NULL; |
| 927 | |
| 928 | while (bytes_copied < size && current_rbd != I596_NULL && |
| 929 | current_rbd != 0) { |
| 930 | struct i82596_rx_buffer_desc rbd; |
| 931 | i82596_rbd_read(s, current_rbd, &rbd); |
| 932 | trace_i82596_rx_rbd(current_rbd, rbd.actual_count, rbd.buffer_addr, |
| 933 | rbd.size); |
| 934 | if (rbd.size & 0x4000) { /* P bit set */ |
| 935 | break; |
| 936 | } |
| 937 | |
| 938 | uint16_t buf_size = rbd.size & 0x3FFF; |
| 939 | |
| 940 | if (buf_size == 0) { |
| 941 | current_rbd = i82596_translate_address(s, rbd.next_rbd_addr, false); |
| 942 | continue; |
| 943 | } |
| 944 | |
| 945 | hwaddr buf_addr = i82596_translate_address(s, rbd.buffer_addr, true); |
| 946 | if (buf_addr == 0 || buf_addr == I596_NULL) { |
| 947 | *out_of_resources = true; |
| 948 | break; |
| 949 | } |
| 950 | size_t remaining = size - bytes_copied; |
| 951 | size_t to_copy = MIN(remaining, buf_size); |
| 952 | if (to_copy > 0) { |
| 953 | address_space_write(&address_space_memory, buf_addr, |
| 954 | MEMTXATTRS_UNSPECIFIED, |
| 955 | buf + bytes_copied, to_copy); |
| 956 | bytes_copied += to_copy; |
| 957 | } |
| 958 | rbd.actual_count = to_copy | 0x4000; /* Set F (filled) bit */ |
| 959 | if (bytes_copied >= size) { |
| 960 | rbd.actual_count |= 0x8000; /* Set EOF bit (bit 15) */ |
| 961 | } |
| 962 | i82596_rbd_write(s, current_rbd, &rbd); |
| 963 | if (rbd.size & CMD_EOL) { /* EL bit */ |
| 964 | if (bytes_copied < size) { |
| 965 | *out_of_resources = true; |
| 966 | } |
| 967 | current_rbd = I596_NULL; |
| 968 | break; |
| 969 | } |
| 970 | current_rbd = i82596_translate_address(s, rbd.next_rbd_addr, false); |
| 971 | } |
| 972 | |
| 973 | *remaining_rbd = current_rbd; |
| 974 | return bytes_copied; |
| 975 | } |
| 976 | |
| 977 | static inline size_t i82596_get_crc_size(I82596State *s) |
| 978 | { |
| 979 | return I596_CRC16_32 ? 4 : 2; |
| 980 | } |
| 981 | |
| 982 | static ssize_t i82596_receive_packet(I82596State *s, const uint8_t *buf, |
| 983 | size_t size, bool from_queue) |
| 984 | { |
| 985 | struct i82596_rx_descriptor rfd; |
| 986 | uint32_t rfd_addr, rbd_addr; |
| 987 | uint16_t rx_status = 0; |
| 988 | uint16_t is_broadcast = 0; |
| 989 | bool packet_completed = true; |
| 990 | bool simplified_mode = false; |
| 991 | size_t frame_size = size; |
| 992 | size_t payload_size = 0; |
| 993 | size_t bytes_copied = 0; |
| 994 | const uint8_t *packet_data = buf; |
| 995 | bool out_of_resources = false; |
| 996 | size_t crc_size = i82596_get_crc_size(s); |
| 997 | |
| 998 | trace_i82596_receive_packet(buf, size); |
| 999 | |
| 1000 | if (i82596_validate_receive_state(s, &size, from_queue) < 0) { |
| 1001 | return -1; |
| 1002 | } |
| 1003 | |
| 1004 | bool passes_filter = i82596_check_packet_filter(s, buf, &is_broadcast); |
| 1005 | |
| 1006 | if (!i82596_monitor(s, buf, size, passes_filter) && (!passes_filter)) { |
| 1007 | return size; |
| 1008 | } |
| 1009 | |
| 1010 | |
| 1011 | rfd_addr = get_uint32(s->scb + 8); |
| 1012 | |
| 1013 | if (rfd_addr == 0 || rfd_addr == I596_NULL) { |
| 1014 | i82596_update_rx_state(s, RX_NO_RESOURCES); |
| 1015 | s->resource_err++; |
| 1016 | set_uint16(s->scb, get_uint16(s->scb) | SCB_STATUS_RNR); |
| 1017 | i82596_update_scb_irq(s, true); |
| 1018 | return -1; |
| 1019 | } |
| 1020 | |
| 1021 | i82596_rx_rfd_read(s, rfd_addr, &rfd); |
| 1022 | trace_i82596_rx_rfd(rfd_addr, rfd.status_bits, rfd.command, |
| 1023 | rfd.link, rfd.rbd_addr); |
| 1024 | |
| 1025 | s->current_rx_desc = rfd_addr; |
| 1026 | |
| 1027 | if (rfd.status_bits & STAT_C) { |
| 1028 | return -1; |
| 1029 | } |
| 1030 | |
| 1031 | /* 0: Simplified Mode 1: Flexible Mode */ |
| 1032 | simplified_mode = !(rfd.command & CMD_FLEX); |
| 1033 | |
| 1034 | set_uint16(rfd_addr, STAT_B); |
| 1035 | |
| 1036 | if (frame_size < 14) { |
| 1037 | trace_i82596_rx_short_frame(frame_size); |
| 1038 | rx_status |= RX_LENGTH_ERRORS; |
| 1039 | i82596_record_error(s, RX_LENGTH_ERRORS, false); |
| 1040 | s->short_fr_error++; |
| 1041 | packet_completed = false; |
| 1042 | goto rx_complete; |
| 1043 | } |
| 1044 | |
| 1045 | payload_size = frame_size; |
| 1046 | do { |
| 1047 | if (simplified_mode && I596_LOOPBACK) { |
| 1048 | uint16_t rfd_size = rfd.size & 0x3FFF; |
| 1049 | |
| 1050 | if (rfd_size % 2 != 0) { |
| 1051 | rx_status |= RX_LENGTH_ERRORS; |
| 1052 | i82596_record_error(s, RX_LENGTH_ERRORS, false); |
| 1053 | s->align_err++; |
| 1054 | packet_completed = false; |
| 1055 | goto rx_complete; |
| 1056 | } |
| 1057 | |
| 1058 | if (payload_size > rfd_size) { |
| 1059 | rx_status |= RFD_STATUS_TRUNC; |
| 1060 | payload_size = rfd_size; |
| 1061 | packet_completed = !SAVE_BAD_FRAMES ? false : true; |
| 1062 | } |
| 1063 | |
| 1064 | if (payload_size > 0) { |
| 1065 | bytes_copied = i82596_rx_copy_to_rfd(s, rfd_addr, packet_data, |
| 1066 | payload_size, rfd_size); |
| 1067 | } |
| 1068 | |
| 1069 | i82596_rx_store_frame_header(s, &rfd, packet_data, frame_size); |
| 1070 | |
| 1071 | } else { |
| 1072 | uint16_t rfd_size = rfd.size & 0x3FFF; /* SIZE_MASK */ |
| 1073 | size_t rfd_frame_size = 0; |
| 1074 | size_t remaining_to_copy = payload_size - bytes_copied; |
| 1075 | if (rfd_size > 0 && remaining_to_copy > 0) { |
| 1076 | size_t data_offset = 0x10; |
| 1077 | |
| 1078 | rfd_frame_size = MIN(remaining_to_copy, rfd_size); |
| 1079 | address_space_write(&address_space_memory, |
| 1080 | rfd_addr + data_offset, |
| 1081 | MEMTXATTRS_UNSPECIFIED, |
| 1082 | packet_data + bytes_copied, |
| 1083 | rfd_frame_size); |
| 1084 | bytes_copied += rfd_frame_size; |
| 1085 | } |
| 1086 | |
| 1087 | if (bytes_copied < payload_size) { |
| 1088 | size_t remaining = payload_size - bytes_copied; |
| 1089 | rbd_addr = i82596_translate_address(s, rfd.rbd_addr, false); |
| 1090 | |
| 1091 | if (rbd_addr == I596_NULL || rbd_addr == 0) { |
| 1092 | rx_status |= RFD_STATUS_TRUNC | RFD_STATUS_NOBUFS; |
| 1093 | i82596_record_error(s, RFD_STATUS_NOBUFS, false); |
| 1094 | packet_completed = true; |
| 1095 | break; |
| 1096 | } else { |
| 1097 | hwaddr remaining_rbd = I596_NULL; |
| 1098 | size_t rbd_bytes = i82596_rx_copy_to_rbds( |
| 1099 | s, rbd_addr, |
| 1100 | packet_data + bytes_copied, |
| 1101 | remaining, |
| 1102 | &out_of_resources, |
| 1103 | &remaining_rbd); |
| 1104 | bytes_copied += rbd_bytes; |
| 1105 | |
| 1106 | uint32_t next_rfd = i82596_translate_address(s, rfd.link, |
| 1107 | false); |
| 1108 | if (next_rfd != I596_NULL && next_rfd != 0) { |
| 1109 | if (remaining_rbd != I596_NULL && remaining_rbd != 0) { |
| 1110 | trace_i82596_rx_rfd_update(next_rfd, remaining_rbd); |
| 1111 | set_uint32(next_rfd + 8, remaining_rbd); |
| 1112 | } else { |
| 1113 | set_uint32(next_rfd + 8, I596_NULL); |
| 1114 | } |
| 1115 | } |
| 1116 | |
| 1117 | if (out_of_resources) { |
| 1118 | trace_i82596_rx_out_of_rbds(); |
| 1119 | i82596_record_error(s, RFD_STATUS_NOBUFS, false); |
| 1120 | rx_status |= RFD_STATUS_TRUNC | RFD_STATUS_NOBUFS; |
| 1121 | packet_completed = true; |
| 1122 | break; |
| 1123 | } |
| 1124 | |
| 1125 | if (bytes_copied < payload_size) { |
| 1126 | trace_i82596_rx_incomplete(bytes_copied, payload_size); |
| 1127 | rx_status |= RFD_STATUS_TRUNC; |
| 1128 | packet_completed = true; |
| 1129 | break; |
| 1130 | } |
| 1131 | } |
| 1132 | } |
| 1133 | } |
| 1134 | |
| 1135 | } while (bytes_copied < payload_size); |
| 1136 | |
| 1137 | rx_complete: |
| 1138 | if (I596_CRCINM && !I596_LOOPBACK && packet_completed) { |
| 1139 | uint8_t crc_data[4]; |
| 1140 | size_t crc_len = crc_size; |
| 1141 | |
| 1142 | if (I596_CRC16_32) { |
| 1143 | uint32_t crc = crc32(~0, packet_data, frame_size); |
| 1144 | crc = cpu_to_be32(crc); |
| 1145 | memcpy(crc_data, &crc, 4); |
| 1146 | } else { |
| 1147 | uint16_t crc = i82596_calculate_crc16(packet_data, frame_size); |
| 1148 | crc = cpu_to_be16(crc); |
| 1149 | memcpy(crc_data, &crc, 2); |
| 1150 | } |
| 1151 | |
| 1152 | if (simplified_mode) { |
| 1153 | address_space_write(&address_space_memory, |
| 1154 | rfd_addr + 0x1E + bytes_copied, |
| 1155 | MEMTXATTRS_UNSPECIFIED, crc_data, crc_len); |
| 1156 | } |
| 1157 | } |
| 1158 | |
| 1159 | if (packet_completed) { |
| 1160 | rx_status |= STAT_C | STAT_OK; |
| 1161 | if (is_broadcast) { |
| 1162 | rx_status |= 0x0001; |
| 1163 | } |
| 1164 | } else { |
| 1165 | rx_status |= STAT_B; |
| 1166 | } |
| 1167 | |
| 1168 | rfd.status_bits = rx_status & ~STAT_B; |
| 1169 | rfd.actual_count = (bytes_copied & 0x3FFF) | 0x4000; |
| 1170 | if (packet_completed) { |
| 1171 | rfd.actual_count |= I596_EOF; |
| 1172 | } |
| 1173 | |
| 1174 | i82596_rx_desc_write(s, rfd_addr, &rfd, (simplified_mode || I596_LOOPBACK)); |
| 1175 | |
| 1176 | if (rfd.command & CMD_SUSP) { |
| 1177 | i82596_update_rx_state(s, RX_SUSPENDED); |
| 1178 | return size; |
| 1179 | } |
| 1180 | |
| 1181 | if (rfd.command & CMD_EOL) { |
| 1182 | i82596_update_rx_state(s, RX_SUSPENDED); |
| 1183 | return size; |
| 1184 | } |
| 1185 | |
| 1186 | if (packet_completed && s->rx_status == RX_READY) { |
| 1187 | uint32_t next_rfd_addr = i82596_translate_address(s, rfd.link, false); |
| 1188 | if (next_rfd_addr != 0 && next_rfd_addr != I596_NULL) { |
| 1189 | set_uint32(s->scb + 8, next_rfd_addr); |
| 1190 | } |
| 1191 | |
| 1192 | s->scb_status |= SCB_STATUS_FR; |
| 1193 | i82596_update_scb_irq(s, true); |
| 1194 | } |
| 1195 | trace_i82596_rx_complete(s->crc_err, s->align_err, s->resource_err); |
| 1196 | return size; |
| 1197 | } |
| 1198 | |
| 1199 | ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
| 1200 | { |
| 1201 | I82596State *s = qemu_get_nic_opaque(nc); |
| 1202 | |
| 1203 | if (!I596_FULL_DUPLEX && !s->throttle_state) { |
| 1204 | if (s->queue_count < PACKET_QUEUE_SIZE) { |
| 1205 | goto queue_packet; |
| 1206 | } |
| 1207 | trace_i82596_receive_suspended(); |
| 1208 | return size; |
| 1209 | } |
| 1210 | |
| 1211 | if (s->rx_status != RX_READY) { |
| 1212 | if (s->queue_count >= PACKET_QUEUE_SIZE) { |
| 1213 | trace_i82596_receive_queue_full(); |
| 1214 | s->over_err++; |
| 1215 | set_uint32(s->scb + 22, s->over_err); |
| 1216 | i82596_record_error(s, RX_OVER_ERRORS, false); |
| 1217 | return size; |
| 1218 | } |
| 1219 | queue_packet: |
| 1220 | if (size <= PKT_BUF_SZ) { |
| 1221 | memcpy(s->packet_queue[s->queue_head], buf, size); |
| 1222 | s->packet_queue_len[s->queue_head] = size; |
| 1223 | s->queue_head = (s->queue_head + 1) % PACKET_QUEUE_SIZE; |
| 1224 | s->queue_count++; |
| 1225 | } |
| 1226 | return size; |
| 1227 | } |
| 1228 | |
| 1229 | return i82596_receive_packet(s, buf, size, false); |
| 1230 | } |
| 1231 | |
| 1232 | ssize_t i82596_receive_iov(NetClientState *nc, const struct iovec *iov, |
| 1233 | int iovcnt) |
| 1234 | { |
| 1235 | size_t sz = 0; |
| 1236 | uint8_t *buf; |
| 1237 | int i; |
| 1238 | for (i = 0; i < iovcnt; i++) { |
| 1239 | sz += iov[i].iov_len; |
| 1240 | } |
| 1241 | trace_i82596_receive_iov(sz, iovcnt); |
| 1242 | if (sz == 0) { |
| 1243 | return -1; |
| 1244 | } |
| 1245 | buf = g_malloc(sz); |
| 1246 | if (!buf) { |
| 1247 | return -1; |
| 1248 | } |
| 1249 | size_t offset = 0; |
| 1250 | for (i = 0; i < iovcnt; i++) { |
| 1251 | if (iov[i].iov_base == NULL) { |
| 1252 | g_free(buf); |
| 1253 | return -1; |
| 1254 | } |
| 1255 | memcpy(buf + offset, iov[i].iov_base, iov[i].iov_len); |
| 1256 | offset += iov[i].iov_len; |
| 1257 | } |
| 1258 | i82596_receive(nc, buf, sz); |
| 1259 | g_free(buf); |
| 1260 | return sz; |
| 1261 | } |
| 1262 | |
| 1263 | static void set_individual_address(I82596State *s, uint32_t addr) |
| 1264 | { |
| 1265 | NetClientState *nc; |
| 1266 | uint8_t *m; |
| 1267 | |
| 1268 | nc = qemu_get_queue(s->nic); |
| 1269 | m = s->conf.macaddr.a; |
| 1270 | address_space_read(&address_space_memory, addr + 8, |
| 1271 | MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN); |
| 1272 | qemu_format_nic_info_str(nc, m); |
| 1273 | trace_i82596_new_mac(nc->info_str); |
| 1274 | } |
| 1275 | |
| 1276 | static void set_multicast_list(I82596State *s, uint32_t addr) |
| 1277 | { |
| 1278 | uint16_t mc_count, i; |
| 1279 | |
| 1280 | memset(&s->mult[0], 0, sizeof(s->mult)); |
| 1281 | mc_count = get_uint16(addr + 8) / ETH_ALEN; |
| 1282 | addr += 10; |
| 1283 | if (mc_count > MAX_MC_CNT) { |
| 1284 | mc_count = MAX_MC_CNT; |
| 1285 | } |
| 1286 | for (i = 0; i < mc_count; i++) { |
| 1287 | uint8_t multicast_addr[ETH_ALEN]; |
| 1288 | address_space_read(&address_space_memory, addr + i * ETH_ALEN, |
| 1289 | MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN); |
| 1290 | unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & |
| 1291 | BITS(7, 2)) >> 2; |
| 1292 | assert(mcast_idx < 8 * sizeof(s->mult)); |
| 1293 | s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); |
| 1294 | } |
| 1295 | trace_i82596_set_multicast(mc_count); |
| 1296 | } |
| 1297 | |
| 1298 | void i82596_set_link_status(NetClientState *nc) |
| 1299 | { |
| 1300 | I82596State *s = qemu_get_nic_opaque(nc); |
| 1301 | bool was_up = s->lnkst != 0; |
| 1302 | |
| 1303 | s->lnkst = nc->link_down ? 0 : 0x8000; |
| 1304 | bool is_up = s->lnkst != 0; |
| 1305 | |
| 1306 | if (!was_up && is_up && s->rx_status == RX_READY) { |
| 1307 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 1308 | } |
| 1309 | } |
| 1310 | |
| 1311 | static bool i82596_check_medium_status(I82596State *s) |
| 1312 | { |
| 1313 | if (I596_FULL_DUPLEX) { |
| 1314 | return true; |
| 1315 | } |
| 1316 | |
| 1317 | if (!s->throttle_state) { |
| 1318 | return false; |
| 1319 | } |
| 1320 | |
| 1321 | if (!I596_LOOPBACK && (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) % 100 < 5)) { |
| 1322 | s->collision_events++; |
| 1323 | return false; |
| 1324 | } |
| 1325 | |
| 1326 | return true; |
| 1327 | } |
| 1328 | |
| 1329 | static int i82596_csma_backoff(I82596State *s, int retry_count) |
| 1330 | { |
| 1331 | int backoff_factor, slot_count, backoff_time; |
| 1332 | |
| 1333 | backoff_factor = MIN(retry_count + 1, CSMA_BACKOFF_LIMIT); |
| 1334 | slot_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) % (1 << backoff_factor); |
| 1335 | backoff_time = slot_count * CSMA_SLOT_TIME; |
| 1336 | |
| 1337 | return backoff_time; |
| 1338 | } |
| 1339 | |
| 1340 | static uint16_t i82596_calculate_crc16(const uint8_t *data, size_t len) |
| 1341 | { |
| 1342 | uint16_t crc = 0xFFFF; |
| 1343 | size_t i, j; |
| 1344 | |
| 1345 | for (i = 0; i < len; i++) { |
| 1346 | crc ^= data[i] << 8; |
| 1347 | for (j = 0; j < 8; j++) { |
| 1348 | if (crc & 0x8000) { |
| 1349 | crc = (crc << 1) ^ 0x1021; |
| 1350 | } else { |
| 1351 | crc <<= 1; |
| 1352 | } |
| 1353 | } |
| 1354 | } |
| 1355 | return crc; |
| 1356 | } |
| 1357 | |
| 1358 | static size_t i82596_append_crc(I82596State *s, uint8_t *buffer, size_t len) |
| 1359 | { |
| 1360 | if (len + 4 > PKT_BUF_SZ) { |
| 1361 | return len; |
| 1362 | } |
| 1363 | |
| 1364 | if (I596_CRC16_32) { |
| 1365 | uint32_t crc = crc32(~0, buffer, len); |
| 1366 | crc = cpu_to_be32(crc); |
| 1367 | memcpy(&buffer[len], &crc, sizeof(crc)); |
| 1368 | return len + sizeof(crc); |
| 1369 | } else { |
| 1370 | uint16_t crc = i82596_calculate_crc16(buffer, len); |
| 1371 | crc = cpu_to_be16(crc); |
| 1372 | memcpy(&buffer[len], &crc, sizeof(crc)); |
| 1373 | return len + sizeof(crc); |
| 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | static void i82596_update_statistics(I82596State *s, bool is_tx, |
| 1378 | uint16_t error_flags, |
| 1379 | uint16_t collision_count) |
| 1380 | { |
| 1381 | if (is_tx) { |
| 1382 | if (collision_count > 0) { |
| 1383 | s->tx_collisions += collision_count; |
| 1384 | s->collision_events++; |
| 1385 | s->total_collisions += collision_count; |
| 1386 | set_uint32(s->scb + 32, s->tx_collisions); |
| 1387 | } |
| 1388 | if (error_flags) { |
| 1389 | i82596_record_error(s, error_flags, true); |
| 1390 | } |
| 1391 | if (!(error_flags & (TX_ABORTED_ERRORS | TX_CARRIER_ERRORS))) { |
| 1392 | s->tx_good_frames++; |
| 1393 | set_uint32(s->scb + 36, s->tx_good_frames); |
| 1394 | } |
| 1395 | } else { |
| 1396 | s->total_frames++; |
| 1397 | set_uint32(s->scb + 40, s->total_frames); |
| 1398 | if (error_flags) { |
| 1399 | i82596_record_error(s, error_flags, false); |
| 1400 | } else { |
| 1401 | s->total_good_frames++; |
| 1402 | set_uint32(s->scb + 44, s->total_good_frames); |
| 1403 | } |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | /* Bus Throttle Functionality */ |
| 1408 | static void i82596_bus_throttle_timer(void *opaque) |
| 1409 | { |
| 1410 | I82596State *s = opaque; |
| 1411 | |
| 1412 | if (s->throttle_state) { |
| 1413 | s->throttle_state = false; |
| 1414 | if (s->t_off > 0) { |
| 1415 | timer_mod(s->throttle_timer, |
| 1416 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 1417 | s->t_off * NANOSECONDS_PER_MICROSECOND); |
| 1418 | } else { |
| 1419 | s->throttle_state = true; |
| 1420 | } |
| 1421 | } else { |
| 1422 | s->throttle_state = true; |
| 1423 | if (s->t_on > 0 && s->t_on != 0xFFFF) { |
| 1424 | timer_mod(s->throttle_timer, |
| 1425 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 1426 | s->t_on * NANOSECONDS_PER_MICROSECOND); |
| 1427 | } |
| 1428 | } |
| 1429 | } |
| 1430 | |
| 1431 | static void i82596_load_throttle_timers(I82596State *s, bool start_now) |
| 1432 | { |
| 1433 | uint16_t previous_t_on = s->t_on; |
| 1434 | uint16_t previous_t_off = s->t_off; |
| 1435 | s->t_on = get_uint16(s->scb + 36); |
| 1436 | s->t_off = get_uint16(s->scb + 38); |
| 1437 | |
| 1438 | bool values_changed = (s->t_on != previous_t_on || |
| 1439 | s->t_off != previous_t_off); |
| 1440 | if (start_now || (values_changed && s->throttle_timer)) { |
| 1441 | timer_del(s->throttle_timer); |
| 1442 | s->throttle_state = true; |
| 1443 | if (s->t_on > 0 && s->t_on != 0xFFFF && !I596_FULL_DUPLEX) { |
| 1444 | timer_mod(s->throttle_timer, |
| 1445 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 1446 | s->t_on * NANOSECONDS_PER_MICROSECOND); |
| 1447 | } |
| 1448 | } |
| 1449 | } |
| 1450 | |
| 1451 | static void write_uint16(uint8_t *buffer, int offset, uint16_t value) |
| 1452 | { |
| 1453 | buffer[offset] = value >> 8; |
| 1454 | buffer[offset + 1] = value & 0xFF; |
| 1455 | } |
| 1456 | static void write_uint32(uint8_t *buffer, int offset, uint32_t value) |
| 1457 | { |
| 1458 | write_uint16(buffer, offset, value >> 16); |
| 1459 | write_uint16(buffer, offset + 2, value & 0xFFFF); |
| 1460 | } |
| 1461 | |
| 1462 | static void i82596_init_dump_area(I82596State *s, uint8_t *buffer) |
| 1463 | { |
| 1464 | memset(buffer, 0, DUMP_BUF_SZ); |
| 1465 | |
| 1466 | printf("This is the dump area function for i82596 QEMU side\n" |
| 1467 | "If you are seeing this message, please contact:\n" |
| 1468 | "Soumyajyotii Sarkar <soumyajyotisarkar23@gmail.com>\n" |
| 1469 | "With the process in which you encountered this issue:\n" |
| 1470 | "This still needs developement so,\n" |
| 1471 | "I will be more than delighted to help you out!\n" |
| 1472 | ); |
| 1473 | |
| 1474 | write_uint16(buffer, 0x00, (s->config[5] << 8) | s->config[4]); |
| 1475 | write_uint16(buffer, 0x02, (s->config[3] << 8) | s->config[2]); |
| 1476 | write_uint16(buffer, 0x04, (s->config[9] << 8) | s->config[8]); |
| 1477 | write_uint16(buffer, 0x06, (s->config[7] << 8) | s->config[6]); |
| 1478 | write_uint16(buffer, 0x08, (s->config[13] << 8) | s->config[12]); |
| 1479 | write_uint16(buffer, 0x0A, (s->config[11] << 8) | s->config[10]); |
| 1480 | |
| 1481 | buffer[0x0C] = s->conf.macaddr.a[0]; |
| 1482 | buffer[0x0D] = s->conf.macaddr.a[1]; |
| 1483 | buffer[0x10] = s->conf.macaddr.a[2]; |
| 1484 | buffer[0x11] = s->conf.macaddr.a[3]; |
| 1485 | buffer[0x12] = s->conf.macaddr.a[4]; |
| 1486 | buffer[0x13] = s->conf.macaddr.a[5]; |
| 1487 | |
| 1488 | if (s->last_tx_len > 0) { |
| 1489 | uint32_t tx_crc = crc32(~0, s->tx_buffer, s->last_tx_len); |
| 1490 | write_uint16(buffer, 0x14, tx_crc & 0xFFFF); |
| 1491 | write_uint16(buffer, 0x16, tx_crc >> 16); |
| 1492 | } |
| 1493 | |
| 1494 | memcpy(&buffer[0x24], s->mult, sizeof(s->mult)); |
| 1495 | |
| 1496 | buffer[0xB0] = s->cu_status; |
| 1497 | buffer[0xB1] = s->rx_status; |
| 1498 | |
| 1499 | write_uint32(buffer, 0xB4, s->crc_err); |
| 1500 | write_uint32(buffer, 0xB8, s->align_err); |
| 1501 | write_uint32(buffer, 0xBC, s->resource_err); |
| 1502 | write_uint32(buffer, 0xC0, s->over_err); |
| 1503 | |
| 1504 | write_uint32(buffer, 0xC4, s->short_fr_error); |
| 1505 | write_uint32(buffer, 0xC8, s->total_frames); |
| 1506 | write_uint32(buffer, 0xCC, s->total_good_frames); |
| 1507 | |
| 1508 | buffer[0xD0] = I596_PROMISC ? 1 : 0; |
| 1509 | buffer[0xD1] = I596_BC_DISABLE ? 1 : 0; |
| 1510 | buffer[0xD2] = I596_FULL_DUPLEX ? 1 : 0; |
| 1511 | buffer[0xD3] = I596_LOOPBACK; |
| 1512 | |
| 1513 | uint8_t mc_count = 0; |
| 1514 | for (int i = 0; i < sizeof(s->mult); i++) { |
| 1515 | uint8_t byte = s->mult[i]; |
| 1516 | while (byte) { |
| 1517 | if (byte & 0x01) { |
| 1518 | mc_count++; |
| 1519 | } |
| 1520 | byte >>= 1; |
| 1521 | } |
| 1522 | } |
| 1523 | buffer[0xD4] = mc_count; |
| 1524 | buffer[0xD5] = I596_NOCRC_INS ? 1 : 0; |
| 1525 | buffer[0xD6] = I596_CRC16_32 ? 1 : 0; |
| 1526 | |
| 1527 | write_uint16(buffer, 0xD8, s->lnkst); |
| 1528 | buffer[0xDA] = I596_MONITOR_MODE; |
| 1529 | write_uint32(buffer, 0xDC, s->collision_events); |
| 1530 | |
| 1531 | write_uint16(buffer, 0x110, s->t_on); |
| 1532 | write_uint16(buffer, 0x112, s->t_off); |
| 1533 | write_uint16(buffer, 0x114, s->throttle_state ? 0x0001 : 0x0000); |
| 1534 | write_uint16(buffer, 0x120, s->sysbus); |
| 1535 | write_uint16(buffer, 0x128, s->scb_status); |
| 1536 | write_uint32(buffer, 0, 0xFFFF0000); |
| 1537 | } |
| 1538 | |
| 1539 | static void i82596_port_dump(I82596State *s, uint32_t dump_addr) |
| 1540 | { |
| 1541 | uint8_t dump_buffer[DUMP_BUF_SZ]; |
| 1542 | |
| 1543 | i82596_init_dump_area(s, dump_buffer); |
| 1544 | |
| 1545 | address_space_write(&address_space_memory, dump_addr, |
| 1546 | MEMTXATTRS_UNSPECIFIED, dump_buffer, sizeof(dump_buffer)); |
| 1547 | |
| 1548 | set_uint32(dump_addr, 0xFFFF0000); |
| 1549 | s->scb_status |= SCB_STATUS_CX; |
| 1550 | s->send_irq = 1; |
| 1551 | } |
| 1552 | |
| 1553 | static void i82596_command_dump(I82596State *s, uint32_t cmd_addr) |
| 1554 | { |
| 1555 | uint32_t dump_addr; |
| 1556 | uint8_t dump_buffer[DUMP_BUF_SZ]; |
| 1557 | uint16_t cmd = get_uint16(cmd_addr + 2); |
| 1558 | uint16_t status; |
| 1559 | |
| 1560 | dump_addr = get_uint32(cmd_addr + 8); |
| 1561 | |
| 1562 | i82596_init_dump_area(s, dump_buffer); |
| 1563 | address_space_write(&address_space_memory, dump_addr, |
| 1564 | MEMTXATTRS_UNSPECIFIED, dump_buffer, sizeof(dump_buffer)); |
| 1565 | status = STAT_C | STAT_OK; |
| 1566 | set_uint16(cmd_addr, status); |
| 1567 | if (cmd & CMD_INTR) { |
| 1568 | s->scb_status |= SCB_STATUS_CX; |
| 1569 | s->send_irq = 1; |
| 1570 | } |
| 1571 | if (cmd & CMD_SUSP) { |
| 1572 | s->cu_status = CU_SUSPENDED; |
| 1573 | s->scb_status |= SCB_STATUS_CNA; |
| 1574 | } |
| 1575 | } |
| 1576 | |
| 1577 | static void i82596_configure(I82596State *s, uint32_t addr) |
| 1578 | { |
| 1579 | uint8_t byte_cnt; |
| 1580 | byte_cnt = get_byte(addr + 8) & 0x0f; |
| 1581 | byte_cnt = MAX(byte_cnt, 4); |
| 1582 | byte_cnt = MIN(byte_cnt, sizeof(s->config)); |
| 1583 | s->config[2] &= 0x82; /* mask valid bits */ |
| 1584 | s->config[2] |= 0x40; |
| 1585 | s->config[7] &= 0xf7; /* clear zero bit */ |
| 1586 | |
| 1587 | address_space_read(&address_space_memory, addr + 8, |
| 1588 | MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); |
| 1589 | |
| 1590 | if (byte_cnt > 12) { |
| 1591 | s->config[12] &= 0x40; |
| 1592 | |
| 1593 | if (byte_cnt > 11) { |
| 1594 | uint8_t monitor_mode = I596_MONITOR_MODE; |
| 1595 | s->config[11] &= ~0xC0; /* Clear bits 6-7 */ |
| 1596 | s->config[11] |= (monitor_mode << 6); /* Set monitor mode */ |
| 1597 | } |
| 1598 | } |
| 1599 | |
| 1600 | if (s->rx_status == RX_READY) { |
| 1601 | timer_mod(s->flush_queue_timer, |
| 1602 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 100000000); |
| 1603 | } |
| 1604 | |
| 1605 | s->scb_status |= SCB_STATUS_CNA; |
| 1606 | s->config[13] |= 0x3f; |
| 1607 | qemu_set_irq(s->irq, 1); |
| 1608 | } |
| 1609 | |
| 1610 | static void i82596_update_scb_irq(I82596State *s, bool trigger) |
| 1611 | { |
| 1612 | update_scb_status(s); |
| 1613 | |
| 1614 | if (trigger) { |
| 1615 | s->send_irq = 1; |
| 1616 | qemu_set_irq(s->irq, 1); |
| 1617 | } |
| 1618 | } |
| 1619 | |
| 1620 | static void i82596_update_cu_status(I82596State *s, uint16_t cmd_status, |
| 1621 | bool generate_interrupt) |
| 1622 | { |
| 1623 | if (cmd_status & STAT_C) { |
| 1624 | if (cmd_status & STAT_OK) { |
| 1625 | if (s->cu_status == CU_ACTIVE && s->cmd_p == I596_NULL) { |
| 1626 | s->cu_status = CU_IDLE; |
| 1627 | s->scb_status |= SCB_STATUS_CNA; |
| 1628 | } |
| 1629 | } else { |
| 1630 | s->cu_status = CU_IDLE; |
| 1631 | s->scb_status |= SCB_STATUS_CNA; |
| 1632 | } |
| 1633 | |
| 1634 | if (generate_interrupt) { |
| 1635 | s->scb_status |= SCB_STATUS_CX; |
| 1636 | i82596_update_scb_irq(s, true); |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | update_scb_status(s); |
| 1641 | } |
| 1642 | |
| 1643 | /** |
| 1644 | * Update SCB Status |
| 1645 | * Synchronizes device state with SCB status word and statistics counters. |
| 1646 | * This function is called frequently to keep the kernel driver updated. |
| 1647 | */ |
| 1648 | static void update_scb_status(I82596State *s) |
| 1649 | { |
| 1650 | s->scb_status = (s->scb_status & 0xf000) |
| 1651 | | (s->cu_status << 8) | (s->rx_status << 4) | (s->lnkst >> 8); |
| 1652 | set_uint16(s->scb, s->scb_status); |
| 1653 | |
| 1654 | set_uint32(s->scb + 28, s->tx_aborted_errors); |
| 1655 | set_uint32(s->scb + 32, s->tx_collisions); |
| 1656 | set_uint32(s->scb + 36, s->tx_good_frames); |
| 1657 | |
| 1658 | set_uint32(s->scb + 16, s->crc_err); |
| 1659 | set_uint32(s->scb + 18, s->align_err); |
| 1660 | set_uint32(s->scb + 20, s->resource_err); |
| 1661 | set_uint32(s->scb + 22, s->over_err); |
| 1662 | set_uint32(s->scb + 24, s->rcvdt_err); |
| 1663 | set_uint32(s->scb + 26, s->short_fr_error); |
| 1664 | } |
| 1665 | |
| 1666 | static void command_loop(I82596State *s) |
| 1667 | { |
| 1668 | while (s->cu_status == CU_ACTIVE && s->cmd_p != I596_NULL && |
| 1669 | s->cmd_p != 0) { |
| 1670 | uint16_t status = get_uint16(s->cmd_p); |
| 1671 | if (status & (STAT_C | STAT_B)) { |
| 1672 | uint32_t next = get_uint32(s->cmd_p + 4); |
| 1673 | if (next == 0 || next == s->cmd_p) { |
| 1674 | s->cmd_p = I596_NULL; |
| 1675 | s->cu_status = CU_IDLE; |
| 1676 | s->scb_status |= SCB_STATUS_CNA; |
| 1677 | break; |
| 1678 | } |
| 1679 | s->cmd_p = i82596_translate_address(s, next, false); |
| 1680 | continue; |
| 1681 | } |
| 1682 | set_uint16(s->cmd_p, STAT_B); |
| 1683 | uint16_t cmd = get_uint16(s->cmd_p + 2); |
| 1684 | uint32_t next_addr = get_uint32(s->cmd_p + 4); |
| 1685 | next_addr = (next_addr == 0) ? I596_NULL : |
| 1686 | i82596_translate_address(s, next_addr, false); |
| 1687 | switch (cmd & CMD_MASK) { |
| 1688 | case CmdNOp: |
| 1689 | break; |
| 1690 | case CmdSASetup: |
| 1691 | set_individual_address(s, s->cmd_p); |
| 1692 | break; |
| 1693 | case CmdConfigure: |
| 1694 | i82596_configure(s, s->cmd_p); |
| 1695 | break; |
| 1696 | case CmdTDR: |
| 1697 | set_uint32(s->cmd_p + 8, s->lnkst); |
| 1698 | break; |
| 1699 | case CmdTx: |
| 1700 | i82596_transmit(s, s->cmd_p); |
| 1701 | goto skip_status_update; |
| 1702 | case CmdMulticastList: |
| 1703 | set_multicast_list(s, s->cmd_p); |
| 1704 | break; |
| 1705 | case CmdDump: |
| 1706 | i82596_command_dump(s, s->cmd_p); |
| 1707 | break; |
| 1708 | case CmdDiagnose: |
| 1709 | break; |
| 1710 | default: |
| 1711 | printf("CMD_LOOP: Unknown command %d\n", cmd & CMD_MASK); |
| 1712 | break; |
| 1713 | } |
| 1714 | |
| 1715 | status = get_uint16(s->cmd_p); |
| 1716 | if (!(status & STAT_C)) { |
| 1717 | set_uint16(s->cmd_p, STAT_C | STAT_OK); |
| 1718 | } |
| 1719 | |
| 1720 | skip_status_update: |
| 1721 | if (cmd & CMD_INTR) { |
| 1722 | s->scb_status |= SCB_STATUS_CX; |
| 1723 | s->send_irq = 1; |
| 1724 | } |
| 1725 | |
| 1726 | bool stop = false; |
| 1727 | |
| 1728 | if (cmd & CMD_SUSP) { |
| 1729 | s->cu_status = CU_SUSPENDED; |
| 1730 | s->scb_status |= SCB_STATUS_CNA; |
| 1731 | stop = true; |
| 1732 | } |
| 1733 | |
| 1734 | if (cmd & CMD_EOL) { |
| 1735 | s->cmd_p = I596_NULL; |
| 1736 | s->cu_status = CU_IDLE; |
| 1737 | s->scb_status |= SCB_STATUS_CNA; |
| 1738 | stop = true; |
| 1739 | } else if (!stop) { |
| 1740 | if (next_addr == 0 || next_addr == I596_NULL || |
| 1741 | next_addr == s->cmd_p) { |
| 1742 | s->cmd_p = I596_NULL; |
| 1743 | s->cu_status = CU_IDLE; |
| 1744 | s->scb_status |= SCB_STATUS_CNA; |
| 1745 | stop = true; |
| 1746 | } else { |
| 1747 | s->cmd_p = next_addr; |
| 1748 | } |
| 1749 | } |
| 1750 | |
| 1751 | update_scb_status(s); |
| 1752 | |
| 1753 | if (stop || s->cu_status != CU_ACTIVE) { |
| 1754 | break; |
| 1755 | } |
| 1756 | } |
| 1757 | |
| 1758 | update_scb_status(s); |
| 1759 | |
| 1760 | if (s->rx_status == RX_READY && s->nic) { |
| 1761 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 1762 | } |
| 1763 | |
| 1764 | } |
| 1765 | |
| 1766 | static void examine_scb(I82596State *s) |
| 1767 | { |
| 1768 | uint16_t command = get_uint16(s->scb + 2); |
| 1769 | uint8_t cuc = (command >> 8) & 0x7; |
| 1770 | uint8_t ruc = (command >> 4) & 0x7; |
| 1771 | |
| 1772 | trace_i82596_scb_command(cuc, ruc); |
| 1773 | |
| 1774 | set_uint16(s->scb + 2, 0); |
| 1775 | s->scb_status &= ~(command & SCB_ACK_MASK); |
| 1776 | |
| 1777 | if (command & SCB_STATUS_RNR) { |
| 1778 | s->rnr_signaled = false; |
| 1779 | } |
| 1780 | |
| 1781 | /* Process Command Unit (CU) commands */ |
| 1782 | switch (cuc) { |
| 1783 | case SCB_CUC_NOP: |
| 1784 | break; |
| 1785 | |
| 1786 | case SCB_CUC_START: { |
| 1787 | uint32_t cmd_ptr = get_uint32(s->scb + 4); |
| 1788 | s->cmd_p = i82596_translate_address(s, cmd_ptr, false); |
| 1789 | s->cu_status = CU_ACTIVE; |
| 1790 | break; |
| 1791 | } |
| 1792 | |
| 1793 | case SCB_CUC_RESUME: |
| 1794 | if (s->cu_status == CU_SUSPENDED) { |
| 1795 | s->cu_status = CU_ACTIVE; |
| 1796 | } |
| 1797 | break; |
| 1798 | |
| 1799 | case SCB_CUC_SUSPEND: |
| 1800 | s->cu_status = CU_SUSPENDED; |
| 1801 | s->scb_status |= SCB_STATUS_CNA; |
| 1802 | break; |
| 1803 | |
| 1804 | case SCB_CUC_ABORT: |
| 1805 | s->cu_status = CU_IDLE; |
| 1806 | s->scb_status |= SCB_STATUS_CNA; |
| 1807 | break; |
| 1808 | |
| 1809 | case SCB_CUC_LOAD_THROTTLE: { |
| 1810 | bool external_trigger = (s->sysbus & I82586_MODE); |
| 1811 | i82596_load_throttle_timers(s, !external_trigger); |
| 1812 | break; |
| 1813 | } |
| 1814 | |
| 1815 | case SCB_CUC_LOAD_START: |
| 1816 | i82596_load_throttle_timers(s, true); |
| 1817 | break; |
| 1818 | } |
| 1819 | |
| 1820 | /* Process Receive Unit (RU) commands */ |
| 1821 | switch (ruc) { |
| 1822 | case SCB_RUC_NOP: |
| 1823 | break; |
| 1824 | |
| 1825 | case SCB_RUC_START: { |
| 1826 | uint32_t rfd_log = get_uint32(s->scb + 8); |
| 1827 | hwaddr rfd = i82596_translate_address(s, rfd_log, false); |
| 1828 | |
| 1829 | if (rfd == 0 || rfd == I596_NULL) { |
| 1830 | s->rx_status = RX_NO_RESOURCES; |
| 1831 | s->scb_status |= SCB_STATUS_RNR; |
| 1832 | break; |
| 1833 | } |
| 1834 | |
| 1835 | /* Find first usable RFD with valid RBD */ |
| 1836 | struct i82596_rx_descriptor test_rfd; |
| 1837 | hwaddr test_rfd_addr = rfd; |
| 1838 | uint32_t test_rfd_log = rfd_log; |
| 1839 | hwaddr first_usable_rfd = 0; |
| 1840 | uint32_t first_usable_rfd_log = 0; |
| 1841 | bool found = false; |
| 1842 | |
| 1843 | for (int i = 0; i < 10 && test_rfd_addr != 0 && |
| 1844 | test_rfd_addr != I596_NULL; i++) { |
| 1845 | i82596_rx_rfd_read(s, test_rfd_addr, &test_rfd); |
| 1846 | |
| 1847 | if (test_rfd.command & CMD_FLEX) { |
| 1848 | hwaddr rbd = i82596_translate_address(s, test_rfd.rbd_addr, |
| 1849 | false); |
| 1850 | if (rbd != I596_NULL && rbd != 0) { |
| 1851 | first_usable_rfd = test_rfd_addr; |
| 1852 | first_usable_rfd_log = test_rfd_log; |
| 1853 | found = true; |
| 1854 | break; |
| 1855 | } |
| 1856 | } |
| 1857 | |
| 1858 | test_rfd_log = test_rfd.link; |
| 1859 | test_rfd_addr = i82596_translate_address(s, test_rfd.link, false); |
| 1860 | } |
| 1861 | |
| 1862 | if (found) { |
| 1863 | s->current_rx_desc = first_usable_rfd; |
| 1864 | s->last_good_rfa = first_usable_rfd_log; |
| 1865 | i82596_update_rx_state(s, RX_READY); |
| 1866 | |
| 1867 | if (first_usable_rfd != rfd) { |
| 1868 | set_uint32(s->scb + 8, first_usable_rfd_log); |
| 1869 | } |
| 1870 | |
| 1871 | if (s->queue_count > 0) { |
| 1872 | trace_i82596_flush_queue(s->queue_count); |
| 1873 | i82596_flush_packet_queue(s); |
| 1874 | } |
| 1875 | |
| 1876 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 1877 | } else { |
| 1878 | s->rx_status = RX_NO_RESOURCES; |
| 1879 | s->scb_status |= SCB_STATUS_RNR; |
| 1880 | } |
| 1881 | break; |
| 1882 | } |
| 1883 | |
| 1884 | case SCB_RUC_RESUME: |
| 1885 | if (s->rx_status == RX_SUSPENDED) { |
| 1886 | i82596_update_rx_state(s, RX_READY); |
| 1887 | if (s->queue_count > 0) { |
| 1888 | trace_i82596_flush_queue(s->queue_count); |
| 1889 | i82596_flush_packet_queue(s); |
| 1890 | } |
| 1891 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 1892 | } |
| 1893 | break; |
| 1894 | |
| 1895 | case SCB_RUC_SUSPEND: |
| 1896 | s->rx_status = RX_SUSPENDED; |
| 1897 | s->scb_status |= SCB_STATUS_RNR; |
| 1898 | break; |
| 1899 | |
| 1900 | case SCB_RUC_ABORT: |
| 1901 | s->rx_status = RX_IDLE; |
| 1902 | s->scb_status |= SCB_STATUS_RNR; |
| 1903 | break; |
| 1904 | } |
| 1905 | |
| 1906 | if (command & 0x80) { |
| 1907 | i82596_s_reset(s); |
| 1908 | return; |
| 1909 | } |
| 1910 | if (s->cu_status == CU_ACTIVE) { |
| 1911 | if (s->cmd_p == I596_NULL) { |
| 1912 | s->cmd_p = get_uint32(s->scb + 4); |
| 1913 | } |
| 1914 | update_scb_status(s); |
| 1915 | command_loop(s); |
| 1916 | } else { |
| 1917 | update_scb_status(s); |
| 1918 | } |
| 1919 | } |
| 1920 | |
| 1921 | static void signal_ca(I82596State *s) |
| 1922 | { |
| 1923 | if (s->scp) { |
| 1924 | /* CA after reset -> initialize with new SCP */ |
| 1925 | s->sysbus = get_byte(s->scp + 3); |
| 1926 | s->mode = (s->sysbus >> 1) & 0x03; /* Extract mode bits (m0, m1) */ |
| 1927 | s->iscp = get_uint32(s->scp + 8); |
| 1928 | |
| 1929 | s->scb = get_uint32(s->iscp + 4); |
| 1930 | |
| 1931 | s->scb_base = (s->mode == I82596_MODE_LINEAR) ? 0 : |
| 1932 | get_uint32(s->iscp + 8); |
| 1933 | s->scb = i82596_translate_address(s, s->scb, false); |
| 1934 | trace_i82596_ca_init(s->scb, s->mode, s->scb_base); |
| 1935 | |
| 1936 | /* |
| 1937 | * Complete initialization sequence: |
| 1938 | * - Clear BUSY flag in ISCP |
| 1939 | * - Set CX and CNA in SCB status |
| 1940 | * - Clear SCB command word |
| 1941 | * - Signal interrupt |
| 1942 | */ |
| 1943 | set_byte(s->iscp + 1, 0); |
| 1944 | s->scb_status |= SCB_STATUS_CX | SCB_STATUS_CNA; |
| 1945 | update_scb_status(s); |
| 1946 | set_uint16(s->scb + 2, 0); |
| 1947 | s->scp = 0; |
| 1948 | qemu_set_irq(s->irq, 1); |
| 1949 | return; |
| 1950 | } |
| 1951 | |
| 1952 | if (s->ca_active) { |
| 1953 | s->ca++; |
| 1954 | return; |
| 1955 | } |
| 1956 | s->ca_active = 1; |
| 1957 | s->ca++; |
| 1958 | |
| 1959 | while (s->ca > 0) { |
| 1960 | s->ca--; |
| 1961 | examine_scb(s); |
| 1962 | } |
| 1963 | |
| 1964 | s->ca_active = 0; |
| 1965 | |
| 1966 | if (s->send_irq) { |
| 1967 | s->send_irq = 0; |
| 1968 | qemu_set_irq(s->irq, 1); |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | static void i82596_self_test(I82596State *s, uint32_t val) |
| 1973 | { |
| 1974 | /* |
| 1975 | * The documentation for the self test is a bit unclear, |
| 1976 | * we are currently doing this and it seems to work. |
| 1977 | */ |
| 1978 | set_uint32(val, 0xFFC00000); |
| 1979 | set_uint32(val + 4, 0); |
| 1980 | |
| 1981 | s->scb_status &= ~SCB_STATUS_CNA; |
| 1982 | s->scb_status |= SCB_STATUS_CNA; |
| 1983 | |
| 1984 | qemu_set_irq(s->irq, 1); |
| 1985 | update_scb_status(s); |
| 1986 | } |
| 1987 | |
| 1988 | /* |
| 1989 | * LASI specific interfaces |
| 1990 | */ |
| 1991 | static uint32_t bit_align_16(uint32_t val) |
| 1992 | { |
| 1993 | return val & ~0x0f; |
| 1994 | } |
| 1995 | |
| 1996 | uint32_t i82596_ioport_readw(void *opaque, uint32_t addr) |
| 1997 | { |
| 1998 | return -1; |
| 1999 | } |
| 2000 | |
| 2001 | void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
| 2002 | { |
| 2003 | I82596State *s = opaque; |
| 2004 | trace_i82596_ioport_write(addr, val); |
| 2005 | switch (addr) { |
| 2006 | case PORT_RESET: |
| 2007 | i82596_s_reset(s); |
| 2008 | break; |
| 2009 | case PORT_SELFTEST: |
| 2010 | val = bit_align_16(val); |
| 2011 | i82596_self_test(s, val); |
| 2012 | break; |
| 2013 | case PORT_ALTSCP: |
| 2014 | s->scp = bit_align_16(val); |
| 2015 | break; |
| 2016 | case PORT_ALTDUMP: |
| 2017 | trace_i82596_dump(val); |
| 2018 | i82596_port_dump(s, bit_align_16(val)); |
| 2019 | break; |
| 2020 | case PORT_CA: |
| 2021 | signal_ca(s); |
| 2022 | break; |
| 2023 | } |
| 2024 | } |
| 2025 | |
| 2026 | void i82596_poll(NetClientState *nc, bool enable) |
| 2027 | { |
| 2028 | I82596State *s = qemu_get_nic_opaque(nc); |
| 2029 | |
| 2030 | if (!enable) { |
| 2031 | return; |
| 2032 | } |
| 2033 | |
| 2034 | if (s->send_irq) { |
| 2035 | qemu_set_irq(s->irq, 1); |
| 2036 | } |
| 2037 | |
| 2038 | if (s->rx_status == RX_NO_RESOURCES) { |
| 2039 | if (s->cmd_p != I596_NULL) { |
| 2040 | i82596_update_rx_state(s, RX_READY); |
| 2041 | update_scb_status(s); |
| 2042 | } |
| 2043 | } |
| 2044 | |
| 2045 | if (s->cu_status == CU_ACTIVE && s->cmd_p != I596_NULL) { |
| 2046 | examine_scb(s); |
| 2047 | } |
| 2048 | qemu_set_irq(s->irq, 0); |
| 2049 | } |
| 2050 | |
| 2051 | const VMStateDescription vmstate_i82596 = { |
| 2052 | .name = "i82596", |
| 2053 | .version_id = 1, |
| 2054 | .minimum_version_id = 1, |
| 2055 | .fields = (VMStateField[]) { |
| 2056 | VMSTATE_UINT8(mode, I82596State), |
| 2057 | VMSTATE_UINT16(t_on, I82596State), |
| 2058 | VMSTATE_UINT16(t_off, I82596State), |
| 2059 | VMSTATE_BOOL(throttle_state, I82596State), |
| 2060 | VMSTATE_UINT32(iscp, I82596State), |
| 2061 | VMSTATE_UINT8(sysbus, I82596State), |
| 2062 | VMSTATE_UINT32(scb, I82596State), |
| 2063 | VMSTATE_UINT32(scb_base, I82596State), |
| 2064 | VMSTATE_UINT16(scb_status, I82596State), |
| 2065 | VMSTATE_UINT8(cu_status, I82596State), |
| 2066 | VMSTATE_UINT8(rx_status, I82596State), |
| 2067 | VMSTATE_UINT16(lnkst, I82596State), |
| 2068 | VMSTATE_UINT32(cmd_p, I82596State), |
| 2069 | VMSTATE_INT32(ca, I82596State), |
| 2070 | VMSTATE_INT32(ca_active, I82596State), |
| 2071 | VMSTATE_INT32(send_irq, I82596State), |
| 2072 | VMSTATE_BUFFER(mult, I82596State), |
| 2073 | VMSTATE_BUFFER(config, I82596State), |
| 2074 | VMSTATE_BUFFER(tx_buffer, I82596State), |
| 2075 | VMSTATE_UINT32(tx_retry_addr, I82596State), |
| 2076 | VMSTATE_INT32(tx_retry_count, I82596State), |
| 2077 | VMSTATE_UINT32(tx_good_frames, I82596State), |
| 2078 | VMSTATE_UINT32(tx_collisions, I82596State), |
| 2079 | VMSTATE_UINT32(tx_aborted_errors, I82596State), |
| 2080 | VMSTATE_UINT32(last_tx_len, I82596State), |
| 2081 | VMSTATE_UINT32(collision_events, I82596State), |
| 2082 | VMSTATE_UINT32(total_collisions, I82596State), |
| 2083 | VMSTATE_UINT32(crc_err, I82596State), |
| 2084 | VMSTATE_UINT32(align_err, I82596State), |
| 2085 | VMSTATE_UINT32(resource_err, I82596State), |
| 2086 | VMSTATE_UINT32(over_err, I82596State), |
| 2087 | VMSTATE_UINT32(rcvdt_err, I82596State), |
| 2088 | VMSTATE_UINT32(short_fr_error, I82596State), |
| 2089 | VMSTATE_UINT32(total_frames, I82596State), |
| 2090 | VMSTATE_UINT32(total_good_frames, I82596State), |
| 2091 | VMSTATE_BUFFER(rx_buffer, I82596State), |
| 2092 | VMSTATE_UINT16(tx_frame_len, I82596State), |
| 2093 | VMSTATE_UINT16(rx_frame_len, I82596State), |
| 2094 | VMSTATE_UINT64(current_tx_desc, I82596State), |
| 2095 | VMSTATE_UINT64(current_rx_desc, I82596State), |
| 2096 | VMSTATE_UINT32(last_good_rfa, I82596State), |
| 2097 | VMSTATE_INT32(queue_head, I82596State), |
| 2098 | VMSTATE_INT32(queue_tail, I82596State), |
| 2099 | VMSTATE_INT32(queue_count, I82596State), |
| 2100 | VMSTATE_BOOL(rnr_signaled, I82596State), |
| 2101 | VMSTATE_BOOL(flushing_queue, I82596State), |
| 2102 | VMSTATE_END_OF_LIST() |
| 2103 | } |
| 2104 | }; |
| 2105 | |
| 2106 | static int i82596_flush_packet_queue(I82596State *s) |
| 2107 | { |
| 2108 | if (s->flushing_queue) { |
| 2109 | return 0; |
| 2110 | } |
| 2111 | |
| 2112 | s->flushing_queue = true; |
| 2113 | int processed = 0; |
| 2114 | |
| 2115 | while (s->queue_count > 0) { |
| 2116 | int tail = s->queue_tail; |
| 2117 | size_t len = s->packet_queue_len[tail]; |
| 2118 | |
| 2119 | ssize_t ret = i82596_receive_packet(s, s->packet_queue[tail], len, |
| 2120 | true); |
| 2121 | |
| 2122 | if (ret < 0) { |
| 2123 | break; |
| 2124 | } |
| 2125 | |
| 2126 | s->queue_tail = (s->queue_tail + 1) % PACKET_QUEUE_SIZE; |
| 2127 | s->queue_count--; |
| 2128 | processed++; |
| 2129 | } |
| 2130 | |
| 2131 | s->flushing_queue = false; |
| 2132 | trace_i82596_flush_queue(processed); |
| 2133 | |
| 2134 | return processed; |
| 2135 | } |
| 2136 | |
| 2137 | static void i82596_flush_queue_timer(void *opaque) |
| 2138 | { |
| 2139 | I82596State *s = opaque; |
| 2140 | |
| 2141 | if (s->queue_count == 0) { |
| 2142 | return; |
| 2143 | } |
| 2144 | |
| 2145 | int processed = i82596_flush_packet_queue(s); |
| 2146 | |
| 2147 | if (processed > 0 && s->rx_status == RX_READY) { |
| 2148 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 2149 | } |
| 2150 | |
| 2151 | if (s->queue_count > 0 && s->rx_status != RX_READY) { |
| 2152 | timer_mod(s->flush_queue_timer, |
| 2153 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); |
| 2154 | } |
| 2155 | } |
| 2156 | |
| 2157 | void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info) |
| 2158 | { |
| 2159 | if (s->conf.macaddr.a[0] == 0) { |
| 2160 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 2161 | } |
| 2162 | s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), |
| 2163 | dev->id, &dev->mem_reentrancy_guard, s); |
| 2164 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
| 2165 | |
| 2166 | if (USE_TIMER) { |
| 2167 | if (!s->flush_queue_timer) { |
| 2168 | s->flush_queue_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 2169 | i82596_flush_queue_timer, s); |
| 2170 | } |
| 2171 | if (!s->throttle_timer) { |
| 2172 | s->throttle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 2173 | i82596_bus_throttle_timer, s); |
| 2174 | } |
| 2175 | } |
| 2176 | |
| 2177 | s->lnkst = 0x8000; /* initial link state: up */ |
| 2178 | } |