@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
h 146 lines 3.58 KB
Raw
1 /*
2 * Core code for QEMU igb emulation
3 *
4 * Datasheet:
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
6 *
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
10 *
11 * Authors:
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
18 *
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
38 */
39
40 #ifndef HW_NET_IGB_CORE_H
41 #define HW_NET_IGB_CORE_H
42
43 #define E1000E_MAC_SIZE (0x8000)
44 #define IGB_EEPROM_SIZE (1024)
45
46 #define IGB_INTR_NUM (25)
47 #define IGB_MSIX_VEC_NUM (10)
48 #define IGBVF_MSIX_VEC_NUM (3)
49 #define IGB_NUM_QUEUES (16)
50 #define IGB_NUM_VM_POOLS (8)
51
52 typedef struct IGBCore IGBCore;
53
54 enum { PHY_R = BIT(0),
55 PHY_W = BIT(1),
56 PHY_RW = PHY_R | PHY_W };
57
58 typedef struct IGBIntrDelayTimer_st {
59 QEMUTimer *timer;
60 bool running;
61 uint32_t delay_reg;
62 uint32_t delay_resolution_ns;
63 IGBCore *core;
64 } IGBIntrDelayTimer;
65
66 struct IGBCore {
67 uint32_t mac[E1000E_MAC_SIZE];
68 uint16_t phy[MAX_PHY_REG_ADDRESS + 1];
69 uint16_t eeprom[IGB_EEPROM_SIZE];
70
71 uint8_t rx_desc_len;
72
73 QEMUTimer *autoneg_timer;
74
75 struct igb_tx {
76 struct e1000_adv_tx_context_desc ctx[2];
77 uint32_t first_cmd_type_len;
78 uint32_t first_olinfo_status;
79
80 bool first;
81 bool skip_cp;
82
83 struct NetTxPkt *tx_pkt;
84 } tx[IGB_NUM_QUEUES];
85
86 struct NetRxPkt *rx_pkt;
87
88 bool has_vnet;
89 int max_queue_num;
90
91 IGBIntrDelayTimer eitr[IGB_INTR_NUM];
92
93 uint32_t eitr_guest_value[IGB_INTR_NUM];
94
95 uint8_t permanent_mac[ETH_ALEN];
96
97 NICState *owner_nic;
98 PCIDevice *owner;
99 void (*owner_start_recv)(PCIDevice *d);
100
101 int64_t timadj;
102 };
103
104 void
105 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size);
106
107 uint64_t
108 igb_core_read(IGBCore *core, hwaddr addr, unsigned size);
109
110 void
111 igb_core_pci_realize(IGBCore *regs,
112 const uint16_t *eeprom_templ,
113 uint32_t eeprom_size,
114 const uint8_t *macaddr);
115
116 void
117 igb_core_reset(IGBCore *core);
118
119 void
120 igb_core_pre_save(IGBCore *core);
121
122 int
123 igb_core_post_load(IGBCore *core);
124
125 void
126 igb_core_set_link_status(IGBCore *core);
127
128 void
129 igb_core_pci_uninit(IGBCore *core);
130
131 void
132 igb_core_vf_reset(IGBCore *core, uint16_t vfn);
133
134 bool
135 igb_can_receive(IGBCore *core);
136
137 ssize_t
138 igb_receive(IGBCore *core, const uint8_t *buf, size_t size);
139
140 ssize_t
141 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt);
142
143 void
144 igb_start_recv(IGBCore *core);
145
146 #endif