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1 /*
2 * ColdFire Fast Ethernet Controller emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
6 * This code is licensed under the GPL
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "system/physmem.h"
12 #include "hw/core/irq.h"
13 #include "net/net.h"
14 #include "qemu/module.h"
15 #include "hw/m68k/mcf.h"
16 #include "hw/m68k/mcf_fec.h"
17 #include "hw/net/mii.h"
18 #include "hw/core/qdev-properties.h"
19 #include "hw/core/sysbus.h"
20 #include "exec/cpu-common.h"
21 #include <zlib.h> /* for crc32 */
22
23 //#define DEBUG_FEC 1
24
25 #ifdef DEBUG_FEC
26 #define DPRINTF(fmt, ...) \
27 do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
28 #else
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #endif
31
32 #define FEC_MAX_DESC 1024
33 #define FEC_MAX_FRAME_SIZE 2032
34 #define FEC_MIB_SIZE 64
35
36 struct mcf_fec_state {
37 SysBusDevice parent_obj;
38
39 MemoryRegion iomem;
40 qemu_irq irq[FEC_NUM_IRQ];
41 NICState *nic;
42 NICConf conf;
43 uint32_t irq_state;
44 uint32_t eir;
45 uint32_t eimr;
46 int rx_enabled;
47 uint32_t rx_descriptor;
48 uint32_t tx_descriptor;
49 uint32_t ecr;
50 uint32_t mmfr;
51 uint32_t mscr;
52 uint32_t rcr;
53 uint32_t tcr;
54 uint32_t tfwr;
55 uint32_t rfsr;
56 uint32_t erdsr;
57 uint32_t etdsr;
58 uint32_t emrbr;
59 uint32_t mib[FEC_MIB_SIZE];
60 };
61
62 #define FEC_INT_HB 0x80000000
63 #define FEC_INT_BABR 0x40000000
64 #define FEC_INT_BABT 0x20000000
65 #define FEC_INT_GRA 0x10000000
66 #define FEC_INT_TXF 0x08000000
67 #define FEC_INT_TXB 0x04000000
68 #define FEC_INT_RXF 0x02000000
69 #define FEC_INT_RXB 0x01000000
70 #define FEC_INT_MII 0x00800000
71 #define FEC_INT_EB 0x00400000
72 #define FEC_INT_LC 0x00200000
73 #define FEC_INT_RL 0x00100000
74 #define FEC_INT_UN 0x00080000
75
76 #define FEC_EN 2
77 #define FEC_RESET 1
78
79 /* Map interrupt flags onto IRQ lines. */
80 static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
81 FEC_INT_TXF,
82 FEC_INT_TXB,
83 FEC_INT_UN,
84 FEC_INT_RL,
85 FEC_INT_RXF,
86 FEC_INT_RXB,
87 FEC_INT_MII,
88 FEC_INT_LC,
89 FEC_INT_HB,
90 FEC_INT_GRA,
91 FEC_INT_EB,
92 FEC_INT_BABT,
93 FEC_INT_BABR
94 };
95
96 /* Buffer Descriptor. */
97 typedef struct {
98 uint16_t flags;
99 uint16_t length;
100 uint32_t data;
101 } mcf_fec_bd;
102
103 #define FEC_BD_R 0x8000
104 #define FEC_BD_E 0x8000
105 #define FEC_BD_O1 0x4000
106 #define FEC_BD_W 0x2000
107 #define FEC_BD_O2 0x1000
108 #define FEC_BD_L 0x0800
109 #define FEC_BD_TC 0x0400
110 #define FEC_BD_ABC 0x0200
111 #define FEC_BD_M 0x0100
112 #define FEC_BD_BC 0x0080
113 #define FEC_BD_MC 0x0040
114 #define FEC_BD_LG 0x0020
115 #define FEC_BD_NO 0x0010
116 #define FEC_BD_CR 0x0004
117 #define FEC_BD_OV 0x0002
118 #define FEC_BD_TR 0x0001
119
120 #define MIB_RMON_T_DROP 0
121 #define MIB_RMON_T_PACKETS 1
122 #define MIB_RMON_T_BC_PKT 2
123 #define MIB_RMON_T_MC_PKT 3
124 #define MIB_RMON_T_CRC_ALIGN 4
125 #define MIB_RMON_T_UNDERSIZE 5
126 #define MIB_RMON_T_OVERSIZE 6
127 #define MIB_RMON_T_FRAG 7
128 #define MIB_RMON_T_JAB 8
129 #define MIB_RMON_T_COL 9
130 #define MIB_RMON_T_P64 10
131 #define MIB_RMON_T_P65TO127 11
132 #define MIB_RMON_T_P128TO255 12
133 #define MIB_RMON_T_P256TO511 13
134 #define MIB_RMON_T_P512TO1023 14
135 #define MIB_RMON_T_P1024TO2047 15
136 #define MIB_RMON_T_P_GTE2048 16
137 #define MIB_RMON_T_OCTETS 17
138 #define MIB_IEEE_T_DROP 18
139 #define MIB_IEEE_T_FRAME_OK 19
140 #define MIB_IEEE_T_1COL 20
141 #define MIB_IEEE_T_MCOL 21
142 #define MIB_IEEE_T_DEF 22
143 #define MIB_IEEE_T_LCOL 23
144 #define MIB_IEEE_T_EXCOL 24
145 #define MIB_IEEE_T_MACERR 25
146 #define MIB_IEEE_T_CSERR 26
147 #define MIB_IEEE_T_SQE 27
148 #define MIB_IEEE_T_FDXFC 28
149 #define MIB_IEEE_T_OCTETS_OK 29
150
151 #define MIB_RMON_R_DROP 32
152 #define MIB_RMON_R_PACKETS 33
153 #define MIB_RMON_R_BC_PKT 34
154 #define MIB_RMON_R_MC_PKT 35
155 #define MIB_RMON_R_CRC_ALIGN 36
156 #define MIB_RMON_R_UNDERSIZE 37
157 #define MIB_RMON_R_OVERSIZE 38
158 #define MIB_RMON_R_FRAG 39
159 #define MIB_RMON_R_JAB 40
160 #define MIB_RMON_R_RESVD_0 41
161 #define MIB_RMON_R_P64 42
162 #define MIB_RMON_R_P65TO127 43
163 #define MIB_RMON_R_P128TO255 44
164 #define MIB_RMON_R_P256TO511 45
165 #define MIB_RMON_R_P512TO1023 46
166 #define MIB_RMON_R_P1024TO2047 47
167 #define MIB_RMON_R_P_GTE2048 48
168 #define MIB_RMON_R_OCTETS 49
169 #define MIB_IEEE_R_DROP 50
170 #define MIB_IEEE_R_FRAME_OK 51
171 #define MIB_IEEE_R_CRC 52
172 #define MIB_IEEE_R_ALIGN 53
173 #define MIB_IEEE_R_MACERR 54
174 #define MIB_IEEE_R_FDXFC 55
175 #define MIB_IEEE_R_OCTETS_OK 56
176
177 static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
178 {
179 physical_memory_read(addr, bd, sizeof(*bd));
180 be16_to_cpus(&bd->flags);
181 be16_to_cpus(&bd->length);
182 be32_to_cpus(&bd->data);
183 }
184
185 static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
186 {
187 mcf_fec_bd tmp;
188 tmp.flags = cpu_to_be16(bd->flags);
189 tmp.length = cpu_to_be16(bd->length);
190 tmp.data = cpu_to_be32(bd->data);
191 physical_memory_write(addr, &tmp, sizeof(tmp));
192 }
193
194 static void mcf_fec_update(mcf_fec_state *s)
195 {
196 uint32_t active;
197 uint32_t changed;
198 uint32_t mask;
199 int i;
200
201 active = s->eir & s->eimr;
202 changed = active ^s->irq_state;
203 for (i = 0; i < FEC_NUM_IRQ; i++) {
204 mask = mcf_fec_irq_map[i];
205 if (changed & mask) {
206 DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
207 qemu_set_irq(s->irq[i], (active & mask) != 0);
208 }
209 }
210 s->irq_state = active;
211 }
212
213 static void mcf_fec_tx_stats(mcf_fec_state *s, int size)
214 {
215 s->mib[MIB_RMON_T_PACKETS]++;
216 s->mib[MIB_RMON_T_OCTETS] += size;
217 if (size < 64) {
218 s->mib[MIB_RMON_T_FRAG]++;
219 } else if (size == 64) {
220 s->mib[MIB_RMON_T_P64]++;
221 } else if (size < 128) {
222 s->mib[MIB_RMON_T_P65TO127]++;
223 } else if (size < 256) {
224 s->mib[MIB_RMON_T_P128TO255]++;
225 } else if (size < 512) {
226 s->mib[MIB_RMON_T_P256TO511]++;
227 } else if (size < 1024) {
228 s->mib[MIB_RMON_T_P512TO1023]++;
229 } else if (size < 2048) {
230 s->mib[MIB_RMON_T_P1024TO2047]++;
231 } else {
232 s->mib[MIB_RMON_T_P_GTE2048]++;
233 }
234 s->mib[MIB_IEEE_T_FRAME_OK]++;
235 s->mib[MIB_IEEE_T_OCTETS_OK] += size;
236 }
237
238 static void mcf_fec_do_tx(mcf_fec_state *s)
239 {
240 uint32_t addr;
241 mcf_fec_bd bd;
242 int frame_size;
243 int len, descnt = 0;
244 uint8_t frame[FEC_MAX_FRAME_SIZE];
245 uint8_t *ptr;
246
247 DPRINTF("do_tx\n");
248 ptr = frame;
249 frame_size = 0;
250 addr = s->tx_descriptor;
251 while (descnt++ < FEC_MAX_DESC) {
252 mcf_fec_read_bd(&bd, addr);
253 DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
254 addr, bd.flags, bd.length, bd.data);
255 if ((bd.flags & FEC_BD_R) == 0) {
256 /* Run out of descriptors to transmit. */
257 break;
258 }
259 len = bd.length;
260 if (frame_size + len > FEC_MAX_FRAME_SIZE) {
261 len = FEC_MAX_FRAME_SIZE - frame_size;
262 s->eir |= FEC_INT_BABT;
263 }
264 physical_memory_read(bd.data, ptr, len);
265 ptr += len;
266 frame_size += len;
267 if (bd.flags & FEC_BD_L) {
268 /* Last buffer in frame. */
269 DPRINTF("Sending packet\n");
270 qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
271 mcf_fec_tx_stats(s, frame_size);
272 ptr = frame;
273 frame_size = 0;
274 s->eir |= FEC_INT_TXF;
275 }
276 s->eir |= FEC_INT_TXB;
277 bd.flags &= ~FEC_BD_R;
278 /* Write back the modified descriptor. */
279 mcf_fec_write_bd(&bd, addr);
280 /* Advance to the next descriptor. */
281 if ((bd.flags & FEC_BD_W) != 0) {
282 addr = s->etdsr;
283 } else {
284 addr += 8;
285 }
286 }
287 s->tx_descriptor = addr;
288 }
289
290 static void mcf_fec_enable_rx(mcf_fec_state *s)
291 {
292 NetClientState *nc = qemu_get_queue(s->nic);
293 mcf_fec_bd bd;
294
295 mcf_fec_read_bd(&bd, s->rx_descriptor);
296 s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
297 if (s->rx_enabled) {
298 qemu_flush_queued_packets(nc);
299 }
300 }
301
302 static void mcf_fec_reset(DeviceState *dev)
303 {
304 mcf_fec_state *s = MCF_FEC_NET(dev);
305
306 s->eir = 0;
307 s->eimr = 0;
308 s->rx_enabled = 0;
309 s->ecr = 0;
310 s->mscr = 0;
311 s->rcr = 0x05ee0001;
312 s->tcr = 0;
313 s->tfwr = 0;
314 s->rfsr = 0x500;
315 }
316
317 #define MMFR_WRITE_OP (1 << 28)
318 #define MMFR_READ_OP (2 << 28)
319 #define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
320 #define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
321
322 static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
323 {
324 uint64_t v;
325
326 if (s->mmfr & MMFR_WRITE_OP)
327 return s->mmfr;
328 if (MMFR_PHYADDR(s->mmfr) != 1)
329 return s->mmfr |= 0xffff;
330
331 switch (MMFR_REGNUM(s->mmfr)) {
332 case MII_BMCR:
333 v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
334 break;
335 case MII_BMSR:
336 v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
337 MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
338 MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
339 break;
340 case MII_PHYID1:
341 v = DP83848_PHYID1;
342 break;
343 case MII_PHYID2:
344 v = DP83848_PHYID2;
345 break;
346 case MII_ANAR:
347 v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
348 MII_ANAR_10 | MII_ANAR_CSMACD;
349 break;
350 case MII_ANLPAR:
351 v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
352 MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
353 break;
354 default:
355 v = 0xffff;
356 break;
357 }
358 s->mmfr = (s->mmfr & ~0xffff) | v;
359 return s->mmfr;
360 }
361
362 static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
363 unsigned size)
364 {
365 mcf_fec_state *s = (mcf_fec_state *)opaque;
366 switch (addr & 0x3ff) {
367 case 0x004: return s->eir;
368 case 0x008: return s->eimr;
369 case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
370 case 0x014: return 0; /* TDAR */
371 case 0x024: return s->ecr;
372 case 0x040: return mcf_fec_read_mdio(s);
373 case 0x044: return s->mscr;
374 case 0x064: return 0; /* MIBC */
375 case 0x084: return s->rcr;
376 case 0x0c4: return s->tcr;
377 case 0x0e4: /* PALR */
378 return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
379 | (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
380 break;
381 case 0x0e8: /* PAUR */
382 return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
383 case 0x0ec: return 0x10000; /* OPD */
384 case 0x118: return 0;
385 case 0x11c: return 0;
386 case 0x120: return 0;
387 case 0x124: return 0;
388 case 0x144: return s->tfwr;
389 case 0x14c: return 0x600;
390 case 0x150: return s->rfsr;
391 case 0x180: return s->erdsr;
392 case 0x184: return s->etdsr;
393 case 0x188: return s->emrbr;
394 case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4];
395 default:
396 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
397 __func__, addr);
398 return 0;
399 }
400 }
401
402 static void mcf_fec_write(void *opaque, hwaddr addr,
403 uint64_t value, unsigned size)
404 {
405 mcf_fec_state *s = (mcf_fec_state *)opaque;
406 switch (addr & 0x3ff) {
407 case 0x004:
408 s->eir &= ~value;
409 break;
410 case 0x008:
411 s->eimr = value;
412 break;
413 case 0x010: /* RDAR */
414 if ((s->ecr & FEC_EN) && !s->rx_enabled) {
415 DPRINTF("RX enable\n");
416 mcf_fec_enable_rx(s);
417 }
418 break;
419 case 0x014: /* TDAR */
420 if (s->ecr & FEC_EN) {
421 mcf_fec_do_tx(s);
422 }
423 break;
424 case 0x024:
425 s->ecr = value;
426 if (value & FEC_RESET) {
427 DPRINTF("Reset\n");
428 mcf_fec_reset(opaque);
429 }
430 if ((s->ecr & FEC_EN) == 0) {
431 s->rx_enabled = 0;
432 }
433 break;
434 case 0x040:
435 s->mmfr = value;
436 s->eir |= FEC_INT_MII;
437 break;
438 case 0x044:
439 s->mscr = value & 0xfe;
440 break;
441 case 0x064:
442 /* TODO: Implement MIB. */
443 break;
444 case 0x084:
445 s->rcr = value & 0x07ff003f;
446 /* TODO: Implement LOOP mode. */
447 break;
448 case 0x0c4: /* TCR */
449 /* We transmit immediately, so raise GRA immediately. */
450 s->tcr = value;
451 if (value & 1)
452 s->eir |= FEC_INT_GRA;
453 break;
454 case 0x0e4: /* PALR */
455 s->conf.macaddr.a[0] = value >> 24;
456 s->conf.macaddr.a[1] = value >> 16;
457 s->conf.macaddr.a[2] = value >> 8;
458 s->conf.macaddr.a[3] = value;
459 break;
460 case 0x0e8: /* PAUR */
461 s->conf.macaddr.a[4] = value >> 24;
462 s->conf.macaddr.a[5] = value >> 16;
463 break;
464 case 0x0ec:
465 /* OPD */
466 break;
467 case 0x118:
468 case 0x11c:
469 case 0x120:
470 case 0x124:
471 /* TODO: implement MAC hash filtering. */
472 break;
473 case 0x144:
474 s->tfwr = value & 3;
475 break;
476 case 0x14c:
477 /* FRBR writes ignored. */
478 break;
479 case 0x150:
480 s->rfsr = (value & 0x3fc) | 0x400;
481 break;
482 case 0x180:
483 s->erdsr = value & ~3;
484 s->rx_descriptor = s->erdsr;
485 break;
486 case 0x184:
487 s->etdsr = value & ~3;
488 s->tx_descriptor = s->etdsr;
489 break;
490 case 0x188:
491 s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0;
492 break;
493 case 0x200 ... 0x2e0:
494 s->mib[(addr & 0x1ff) / 4] = value;
495 break;
496 default:
497 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
498 __func__, addr);
499 return;
500 }
501 mcf_fec_update(s);
502 }
503
504 static void mcf_fec_rx_stats(mcf_fec_state *s, int size)
505 {
506 s->mib[MIB_RMON_R_PACKETS]++;
507 s->mib[MIB_RMON_R_OCTETS] += size;
508 if (size < 64) {
509 s->mib[MIB_RMON_R_FRAG]++;
510 } else if (size == 64) {
511 s->mib[MIB_RMON_R_P64]++;
512 } else if (size < 128) {
513 s->mib[MIB_RMON_R_P65TO127]++;
514 } else if (size < 256) {
515 s->mib[MIB_RMON_R_P128TO255]++;
516 } else if (size < 512) {
517 s->mib[MIB_RMON_R_P256TO511]++;
518 } else if (size < 1024) {
519 s->mib[MIB_RMON_R_P512TO1023]++;
520 } else if (size < 2048) {
521 s->mib[MIB_RMON_R_P1024TO2047]++;
522 } else {
523 s->mib[MIB_RMON_R_P_GTE2048]++;
524 }
525 s->mib[MIB_IEEE_R_FRAME_OK]++;
526 s->mib[MIB_IEEE_R_OCTETS_OK] += size;
527 }
528
529 static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want)
530 {
531 mcf_fec_bd bd;
532 uint32_t addr;
533
534 /* Walk descriptor list to determine if we have enough buffer */
535 addr = s->rx_descriptor;
536 while (want > 0) {
537 mcf_fec_read_bd(&bd, addr);
538 if ((bd.flags & FEC_BD_E) == 0) {
539 return 0;
540 }
541 if (want < s->emrbr) {
542 return 1;
543 }
544 want -= s->emrbr;
545 /* Advance to the next descriptor. */
546 if ((bd.flags & FEC_BD_W) != 0) {
547 addr = s->erdsr;
548 } else {
549 addr += 8;
550 }
551 }
552 return 0;
553 }
554
555 static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
556 {
557 mcf_fec_state *s = qemu_get_nic_opaque(nc);
558 mcf_fec_bd bd;
559 uint32_t flags = 0;
560 uint32_t addr;
561 uint32_t crc;
562 uint32_t buf_addr;
563 uint8_t *crc_ptr;
564 unsigned int buf_len;
565 size_t retsize;
566
567 DPRINTF("do_rx len %d\n", size);
568 if (!s->rx_enabled) {
569 return -1;
570 }
571 /* 4 bytes for the CRC. */
572 size += 4;
573 crc = cpu_to_be32(crc32(~0, buf, size));
574 crc_ptr = (uint8_t *)&crc;
575 /* Huge frames are truncated. */
576 if (size > FEC_MAX_FRAME_SIZE) {
577 size = FEC_MAX_FRAME_SIZE;
578 flags |= FEC_BD_TR | FEC_BD_LG;
579 }
580 /* Frames larger than the user limit just set error flags. */
581 if (size > (s->rcr >> 16)) {
582 flags |= FEC_BD_LG;
583 }
584 /* Check if we have enough space in current descriptors */
585 if (!mcf_fec_have_receive_space(s, size)) {
586 return 0;
587 }
588 addr = s->rx_descriptor;
589 retsize = size;
590 while (size > 0) {
591 mcf_fec_read_bd(&bd, addr);
592 buf_len = (size <= s->emrbr) ? size: s->emrbr;
593 bd.length = buf_len;
594 size -= buf_len;
595 DPRINTF("rx_bd %x length %d\n", addr, bd.length);
596 /* The last 4 bytes are the CRC. */
597 if (size < 4)
598 buf_len += size - 4;
599 buf_addr = bd.data;
600 physical_memory_write(buf_addr, buf, buf_len);
601 buf += buf_len;
602 if (size < 4) {
603 physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
604 crc_ptr += 4 - size;
605 }
606 bd.flags &= ~FEC_BD_E;
607 if (size == 0) {
608 /* Last buffer in frame. */
609 bd.flags |= flags | FEC_BD_L;
610 DPRINTF("rx frame flags %04x\n", bd.flags);
611 s->eir |= FEC_INT_RXF;
612 } else {
613 s->eir |= FEC_INT_RXB;
614 }
615 mcf_fec_write_bd(&bd, addr);
616 /* Advance to the next descriptor. */
617 if ((bd.flags & FEC_BD_W) != 0) {
618 addr = s->erdsr;
619 } else {
620 addr += 8;
621 }
622 }
623 s->rx_descriptor = addr;
624 mcf_fec_rx_stats(s, retsize);
625 mcf_fec_enable_rx(s);
626 mcf_fec_update(s);
627 return retsize;
628 }
629
630 static const MemoryRegionOps mcf_fec_ops = {
631 .read = mcf_fec_read,
632 .write = mcf_fec_write,
633 .endianness = DEVICE_NATIVE_ENDIAN,
634 };
635
636 static NetClientInfo net_mcf_fec_info = {
637 .type = NET_CLIENT_DRIVER_NIC,
638 .size = sizeof(NICState),
639 .receive = mcf_fec_receive,
640 };
641
642 static void mcf_fec_realize(DeviceState *dev, Error **errp)
643 {
644 mcf_fec_state *s = MCF_FEC_NET(dev);
645
646 s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf,
647 object_get_typename(OBJECT(dev)), dev->id,
648 &dev->mem_reentrancy_guard, s);
649 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
650 }
651
652 static void mcf_fec_instance_init(Object *obj)
653 {
654 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
655 mcf_fec_state *s = MCF_FEC_NET(obj);
656 int i;
657
658 memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400);
659 sysbus_init_mmio(sbd, &s->iomem);
660 for (i = 0; i < FEC_NUM_IRQ; i++) {
661 sysbus_init_irq(sbd, &s->irq[i]);
662 }
663 }
664
665 static const Property mcf_fec_properties[] = {
666 DEFINE_NIC_PROPERTIES(mcf_fec_state, conf),
667 };
668
669 static void mcf_fec_class_init(ObjectClass *oc, const void *data)
670 {
671 DeviceClass *dc = DEVICE_CLASS(oc);
672
673 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
674 dc->realize = mcf_fec_realize;
675 dc->desc = "MCF Fast Ethernet Controller network device";
676 device_class_set_legacy_reset(dc, mcf_fec_reset);
677 device_class_set_props(dc, mcf_fec_properties);
678 }
679
680 static const TypeInfo mcf_fec_info = {
681 .name = TYPE_MCF_FEC_NET,
682 .parent = TYPE_SYS_BUS_DEVICE,
683 .instance_size = sizeof(mcf_fec_state),
684 .instance_init = mcf_fec_instance_init,
685 .class_init = mcf_fec_class_init,
686 };
687
688 static void mcf_fec_register_types(void)
689 {
690 type_register_static(&mcf_fec_info);
691 }
692
693 type_init(mcf_fec_register_types)