| 1 | /* |
| 2 | * Rocker switch hardware register and descriptor definitions. |
| 3 | * |
| 4 | * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com> |
| 5 | * Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #ifndef ROCKER_HW_H |
| 10 | #define ROCKER_HW_H |
| 11 | |
| 12 | /* |
| 13 | * Return codes |
| 14 | */ |
| 15 | |
| 16 | enum { |
| 17 | ROCKER_OK = 0, |
| 18 | ROCKER_ENOENT = 2, |
| 19 | ROCKER_ENXIO = 6, |
| 20 | ROCKER_ENOMEM = 12, |
| 21 | ROCKER_EEXIST = 17, |
| 22 | ROCKER_EINVAL = 22, |
| 23 | ROCKER_EMSGSIZE = 90, |
| 24 | ROCKER_ENOTSUP = 95, |
| 25 | ROCKER_ENOBUFS = 105, |
| 26 | }; |
| 27 | |
| 28 | /* |
| 29 | * PCI configuration space |
| 30 | */ |
| 31 | |
| 32 | #define ROCKER_PCI_REVISION 0x1 |
| 33 | #define ROCKER_PCI_BAR0_IDX 0 |
| 34 | #define ROCKER_PCI_BAR0_SIZE 0x2000 |
| 35 | #define ROCKER_PCI_MSIX_BAR_IDX 1 |
| 36 | #define ROCKER_PCI_MSIX_BAR_SIZE 0x2000 |
| 37 | #define ROCKER_PCI_MSIX_TABLE_OFFSET 0x0000 |
| 38 | #define ROCKER_PCI_MSIX_PBA_OFFSET 0x1000 |
| 39 | |
| 40 | /* |
| 41 | * MSI-X vectors |
| 42 | */ |
| 43 | |
| 44 | enum { |
| 45 | ROCKER_MSIX_VEC_CMD, |
| 46 | ROCKER_MSIX_VEC_EVENT, |
| 47 | ROCKER_MSIX_VEC_TEST, |
| 48 | ROCKER_MSIX_VEC_RESERVED0, |
| 49 | __ROCKER_MSIX_VEC_TX, |
| 50 | __ROCKER_MSIX_VEC_RX, |
| 51 | #define ROCKER_MSIX_VEC_TX(port) \ |
| 52 | (__ROCKER_MSIX_VEC_TX + ((port) * 2)) |
| 53 | #define ROCKER_MSIX_VEC_RX(port) \ |
| 54 | (__ROCKER_MSIX_VEC_RX + ((port) * 2)) |
| 55 | #define ROCKER_MSIX_VEC_COUNT(portcnt) \ |
| 56 | (ROCKER_MSIX_VEC_RX((portcnt) - 1) + 1) |
| 57 | }; |
| 58 | |
| 59 | /* |
| 60 | * Rocker bogus registers |
| 61 | */ |
| 62 | #define ROCKER_BOGUS_REG0 0x0000 |
| 63 | #define ROCKER_BOGUS_REG1 0x0004 |
| 64 | #define ROCKER_BOGUS_REG2 0x0008 |
| 65 | #define ROCKER_BOGUS_REG3 0x000c |
| 66 | |
| 67 | /* |
| 68 | * Rocker test registers |
| 69 | */ |
| 70 | #define ROCKER_TEST_REG 0x0010 |
| 71 | #define ROCKER_TEST_REG64 0x0018 /* 8-byte */ |
| 72 | #define ROCKER_TEST_IRQ 0x0020 |
| 73 | #define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */ |
| 74 | #define ROCKER_TEST_DMA_SIZE 0x0030 |
| 75 | #define ROCKER_TEST_DMA_CTRL 0x0034 |
| 76 | |
| 77 | /* |
| 78 | * Rocker test register ctrl |
| 79 | */ |
| 80 | #define ROCKER_TEST_DMA_CTRL_CLEAR (1 << 0) |
| 81 | #define ROCKER_TEST_DMA_CTRL_FILL (1 << 1) |
| 82 | #define ROCKER_TEST_DMA_CTRL_INVERT (1 << 2) |
| 83 | |
| 84 | /* |
| 85 | * Rocker DMA ring register offsets |
| 86 | */ |
| 87 | #define ROCKER_DMA_DESC_BASE 0x1000 |
| 88 | #define ROCKER_DMA_DESC_SIZE 32 |
| 89 | #define ROCKER_DMA_DESC_MASK 0x1F |
| 90 | #define ROCKER_DMA_DESC_TOTAL_SIZE \ |
| 91 | (ROCKER_DMA_DESC_SIZE * 64) /* 62 ports + event + cmd */ |
| 92 | #define ROCKER_DMA_DESC_ADDR_OFFSET 0x00 /* 8-byte */ |
| 93 | #define ROCKER_DMA_DESC_SIZE_OFFSET 0x08 |
| 94 | #define ROCKER_DMA_DESC_HEAD_OFFSET 0x0c |
| 95 | #define ROCKER_DMA_DESC_TAIL_OFFSET 0x10 |
| 96 | #define ROCKER_DMA_DESC_CTRL_OFFSET 0x14 |
| 97 | #define ROCKER_DMA_DESC_CREDITS_OFFSET 0x18 |
| 98 | #define ROCKER_DMA_DESC_RSVD_OFFSET 0x1c |
| 99 | |
| 100 | /* |
| 101 | * Rocker dma ctrl register bits |
| 102 | */ |
| 103 | #define ROCKER_DMA_DESC_CTRL_RESET (1 << 0) |
| 104 | |
| 105 | /* |
| 106 | * Rocker ring indices |
| 107 | */ |
| 108 | #define ROCKER_RING_CMD 0 |
| 109 | #define ROCKER_RING_EVENT 1 |
| 110 | |
| 111 | /* |
| 112 | * Helper macro to do convert a dma ring register |
| 113 | * to its index. Based on the fact that the register |
| 114 | * group stride is 32 bytes. |
| 115 | */ |
| 116 | #define ROCKER_RING_INDEX(reg) ((reg >> 5) & 0x7F) |
| 117 | |
| 118 | /* |
| 119 | * Rocker DMA Descriptor |
| 120 | */ |
| 121 | |
| 122 | typedef struct rocker_desc { |
| 123 | uint64_t buf_addr; |
| 124 | uint64_t cookie; |
| 125 | uint16_t buf_size; |
| 126 | uint16_t tlv_size; |
| 127 | uint16_t rsvd[5]; /* pad to 32 bytes */ |
| 128 | uint16_t comp_err; |
| 129 | } __attribute__((packed, aligned(8))) RockerDesc; |
| 130 | |
| 131 | /* |
| 132 | * Rocker TLV type fields |
| 133 | */ |
| 134 | |
| 135 | typedef struct rocker_tlv { |
| 136 | uint32_t type; |
| 137 | uint16_t len; |
| 138 | uint16_t rsvd; |
| 139 | } __attribute__((packed, aligned(8))) RockerTlv; |
| 140 | |
| 141 | /* cmd msg */ |
| 142 | enum { |
| 143 | ROCKER_TLV_CMD_UNSPEC, |
| 144 | ROCKER_TLV_CMD_TYPE, /* u16 */ |
| 145 | ROCKER_TLV_CMD_INFO, /* nest */ |
| 146 | |
| 147 | __ROCKER_TLV_CMD_MAX, |
| 148 | ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1, |
| 149 | }; |
| 150 | |
| 151 | enum { |
| 152 | ROCKER_TLV_CMD_TYPE_UNSPEC, |
| 153 | ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS, |
| 154 | ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS, |
| 155 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD, |
| 156 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD, |
| 157 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL, |
| 158 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS, |
| 159 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD, |
| 160 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD, |
| 161 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL, |
| 162 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS, |
| 163 | |
| 164 | __ROCKER_TLV_CMD_TYPE_MAX, |
| 165 | ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1, |
| 166 | }; |
| 167 | |
| 168 | /* cmd info nested for set/get port settings */ |
| 169 | enum { |
| 170 | ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC, |
| 171 | ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */ |
| 172 | ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */ |
| 173 | ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */ |
| 174 | ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */ |
| 175 | ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */ |
| 176 | ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */ |
| 177 | ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */ |
| 178 | ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME, /* binary */ |
| 179 | |
| 180 | __ROCKER_TLV_CMD_PORT_SETTINGS_MAX, |
| 181 | ROCKER_TLV_CMD_PORT_SETTINGS_MAX = __ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1, |
| 182 | }; |
| 183 | |
| 184 | enum { |
| 185 | ROCKER_PORT_MODE_OF_DPA, |
| 186 | }; |
| 187 | |
| 188 | /* event msg */ |
| 189 | enum { |
| 190 | ROCKER_TLV_EVENT_UNSPEC, |
| 191 | ROCKER_TLV_EVENT_TYPE, /* u16 */ |
| 192 | ROCKER_TLV_EVENT_INFO, /* nest */ |
| 193 | |
| 194 | __ROCKER_TLV_EVENT_MAX, |
| 195 | ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1, |
| 196 | }; |
| 197 | |
| 198 | enum { |
| 199 | ROCKER_TLV_EVENT_TYPE_UNSPEC, |
| 200 | ROCKER_TLV_EVENT_TYPE_LINK_CHANGED, |
| 201 | ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN, |
| 202 | |
| 203 | __ROCKER_TLV_EVENT_TYPE_MAX, |
| 204 | ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1, |
| 205 | }; |
| 206 | |
| 207 | /* event info nested for link changed */ |
| 208 | enum { |
| 209 | ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC, |
| 210 | ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */ |
| 211 | ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */ |
| 212 | |
| 213 | __ROCKER_TLV_EVENT_LINK_CHANGED_MAX, |
| 214 | ROCKER_TLV_EVENT_LINK_CHANGED_MAX = __ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1, |
| 215 | }; |
| 216 | |
| 217 | /* event info nested for MAC/VLAN */ |
| 218 | enum { |
| 219 | ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC, |
| 220 | ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */ |
| 221 | ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */ |
| 222 | ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */ |
| 223 | |
| 224 | __ROCKER_TLV_EVENT_MAC_VLAN_MAX, |
| 225 | ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1, |
| 226 | }; |
| 227 | |
| 228 | /* Rx msg */ |
| 229 | enum { |
| 230 | ROCKER_TLV_RX_UNSPEC, |
| 231 | ROCKER_TLV_RX_FLAGS, /* u16, see RX_FLAGS_ */ |
| 232 | ROCKER_TLV_RX_CSUM, /* u16 */ |
| 233 | ROCKER_TLV_RX_FRAG_ADDR, /* u64 */ |
| 234 | ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */ |
| 235 | ROCKER_TLV_RX_FRAG_LEN, /* u16 */ |
| 236 | |
| 237 | __ROCKER_TLV_RX_MAX, |
| 238 | ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1, |
| 239 | }; |
| 240 | |
| 241 | #define ROCKER_RX_FLAGS_IPV4 (1 << 0) |
| 242 | #define ROCKER_RX_FLAGS_IPV6 (1 << 1) |
| 243 | #define ROCKER_RX_FLAGS_CSUM_CALC (1 << 2) |
| 244 | #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD (1 << 3) |
| 245 | #define ROCKER_RX_FLAGS_IP_FRAG (1 << 4) |
| 246 | #define ROCKER_RX_FLAGS_TCP (1 << 5) |
| 247 | #define ROCKER_RX_FLAGS_UDP (1 << 6) |
| 248 | #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD (1 << 7) |
| 249 | #define ROCKER_RX_FLAGS_FWD_OFFLOAD (1 << 8) |
| 250 | |
| 251 | /* Tx msg */ |
| 252 | enum { |
| 253 | ROCKER_TLV_TX_UNSPEC, |
| 254 | ROCKER_TLV_TX_OFFLOAD, /* u8, see TX_OFFLOAD_ */ |
| 255 | ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */ |
| 256 | ROCKER_TLV_TX_TSO_MSS, /* u16 */ |
| 257 | ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */ |
| 258 | ROCKER_TLV_TX_FRAGS, /* array */ |
| 259 | |
| 260 | __ROCKER_TLV_TX_MAX, |
| 261 | ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1, |
| 262 | }; |
| 263 | |
| 264 | #define ROCKER_TX_OFFLOAD_NONE 0 |
| 265 | #define ROCKER_TX_OFFLOAD_IP_CSUM 1 |
| 266 | #define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2 |
| 267 | #define ROCKER_TX_OFFLOAD_L3_CSUM 3 |
| 268 | #define ROCKER_TX_OFFLOAD_TSO 4 |
| 269 | |
| 270 | #define ROCKER_TX_FRAGS_MAX 16 |
| 271 | |
| 272 | enum { |
| 273 | ROCKER_TLV_TX_FRAG_UNSPEC, |
| 274 | ROCKER_TLV_TX_FRAG, /* nest */ |
| 275 | |
| 276 | __ROCKER_TLV_TX_FRAG_MAX, |
| 277 | ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1, |
| 278 | }; |
| 279 | |
| 280 | enum { |
| 281 | ROCKER_TLV_TX_FRAG_ATTR_UNSPEC, |
| 282 | ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */ |
| 283 | ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */ |
| 284 | |
| 285 | __ROCKER_TLV_TX_FRAG_ATTR_MAX, |
| 286 | ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1, |
| 287 | }; |
| 288 | |
| 289 | /* |
| 290 | * cmd info nested for OF-DPA msgs |
| 291 | */ |
| 292 | |
| 293 | enum { |
| 294 | ROCKER_TLV_OF_DPA_UNSPEC, |
| 295 | ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */ |
| 296 | ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */ |
| 297 | ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */ |
| 298 | ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */ |
| 299 | ROCKER_TLV_OF_DPA_COOKIE, /* u64 */ |
| 300 | ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */ |
| 301 | ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */ |
| 302 | ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */ |
| 303 | ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */ |
| 304 | ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */ |
| 305 | ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */ |
| 306 | ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */ |
| 307 | ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */ |
| 308 | ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */ |
| 309 | ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */ |
| 310 | ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */ |
| 311 | ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */ |
| 312 | ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */ |
| 313 | ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */ |
| 314 | ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */ |
| 315 | ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */ |
| 316 | ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */ |
| 317 | ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */ |
| 318 | ROCKER_TLV_OF_DPA_DST_MAC, /* binary */ |
| 319 | ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */ |
| 320 | ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */ |
| 321 | ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */ |
| 322 | ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */ |
| 323 | ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */ |
| 324 | ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */ |
| 325 | ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */ |
| 326 | ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */ |
| 327 | ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */ |
| 328 | ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */ |
| 329 | ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */ |
| 330 | ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */ |
| 331 | ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */ |
| 332 | ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */ |
| 333 | ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */ |
| 334 | ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */ |
| 335 | ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */ |
| 336 | ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */ |
| 337 | ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */ |
| 338 | ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */ |
| 339 | ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */ |
| 340 | ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */ |
| 341 | ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */ |
| 342 | ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */ |
| 343 | ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */ |
| 344 | ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */ |
| 345 | ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */ |
| 346 | ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */ |
| 347 | ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */ |
| 348 | ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */ |
| 349 | ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */ |
| 350 | ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */ |
| 351 | ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */ |
| 352 | ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */ |
| 353 | ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */ |
| 354 | ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */ |
| 355 | ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */ |
| 356 | |
| 357 | __ROCKER_TLV_OF_DPA_MAX, |
| 358 | ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1, |
| 359 | }; |
| 360 | |
| 361 | /* |
| 362 | * OF-DPA table IDs |
| 363 | */ |
| 364 | |
| 365 | enum rocker_of_dpa_table_id { |
| 366 | ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0, |
| 367 | ROCKER_OF_DPA_TABLE_ID_VLAN = 10, |
| 368 | ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20, |
| 369 | ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30, |
| 370 | ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40, |
| 371 | ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50, |
| 372 | ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60, |
| 373 | }; |
| 374 | |
| 375 | /* |
| 376 | * OF-DPA flow stats |
| 377 | */ |
| 378 | |
| 379 | enum { |
| 380 | ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC, |
| 381 | ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */ |
| 382 | ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */ |
| 383 | ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */ |
| 384 | |
| 385 | __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX, |
| 386 | ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1, |
| 387 | }; |
| 388 | |
| 389 | /* |
| 390 | * OF-DPA group types |
| 391 | */ |
| 392 | |
| 393 | enum rocker_of_dpa_group_type { |
| 394 | ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0, |
| 395 | ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE, |
| 396 | ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST, |
| 397 | ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST, |
| 398 | ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD, |
| 399 | ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE, |
| 400 | ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST, |
| 401 | ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP, |
| 402 | ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY, |
| 403 | }; |
| 404 | |
| 405 | /* |
| 406 | * OF-DPA group L2 overlay types |
| 407 | */ |
| 408 | |
| 409 | enum rocker_of_dpa_overlay_type { |
| 410 | ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0, |
| 411 | ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST, |
| 412 | ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST, |
| 413 | ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST, |
| 414 | }; |
| 415 | |
| 416 | /* |
| 417 | * OF-DPA group ID encoding |
| 418 | */ |
| 419 | |
| 420 | #define ROCKER_GROUP_TYPE_SHIFT 28 |
| 421 | #define ROCKER_GROUP_TYPE_MASK 0xf0000000 |
| 422 | #define ROCKER_GROUP_VLAN_ID_SHIFT 16 |
| 423 | #define ROCKER_GROUP_VLAN_ID_MASK 0x0fff0000 |
| 424 | #define ROCKER_GROUP_PORT_SHIFT 0 |
| 425 | #define ROCKER_GROUP_PORT_MASK 0x0000ffff |
| 426 | #define ROCKER_GROUP_TUNNEL_ID_SHIFT 12 |
| 427 | #define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000 |
| 428 | #define ROCKER_GROUP_SUBTYPE_SHIFT 10 |
| 429 | #define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00 |
| 430 | #define ROCKER_GROUP_INDEX_SHIFT 0 |
| 431 | #define ROCKER_GROUP_INDEX_MASK 0x0000ffff |
| 432 | #define ROCKER_GROUP_INDEX_LONG_SHIFT 0 |
| 433 | #define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff |
| 434 | |
| 435 | #define ROCKER_GROUP_TYPE_GET(group_id) \ |
| 436 | (((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT) |
| 437 | #define ROCKER_GROUP_TYPE_SET(type) \ |
| 438 | (((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK) |
| 439 | #define ROCKER_GROUP_VLAN_GET(group_id) \ |
| 440 | (((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT) |
| 441 | #define ROCKER_GROUP_VLAN_SET(vlan_id) \ |
| 442 | (((vlan_id) << ROCKER_GROUP_VLAN_ID_SHIFT) & ROCKER_GROUP_VLAN_ID_MASK) |
| 443 | #define ROCKER_GROUP_PORT_GET(group_id) \ |
| 444 | (((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT) |
| 445 | #define ROCKER_GROUP_PORT_SET(port) \ |
| 446 | (((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK) |
| 447 | #define ROCKER_GROUP_INDEX_GET(group_id) \ |
| 448 | (((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT) |
| 449 | #define ROCKER_GROUP_INDEX_SET(index) \ |
| 450 | (((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK) |
| 451 | #define ROCKER_GROUP_INDEX_LONG_GET(group_id) \ |
| 452 | (((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \ |
| 453 | ROCKER_GROUP_INDEX_LONG_SHIFT) |
| 454 | #define ROCKER_GROUP_INDEX_LONG_SET(index) \ |
| 455 | (((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \ |
| 456 | ROCKER_GROUP_INDEX_LONG_MASK) |
| 457 | |
| 458 | #define ROCKER_GROUP_NONE 0 |
| 459 | #define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \ |
| 460 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\ |
| 461 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port)) |
| 462 | #define ROCKER_GROUP_L2_REWRITE(index) \ |
| 463 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\ |
| 464 | ROCKER_GROUP_INDEX_LONG_SET(index)) |
| 465 | #define ROCKER_GROUP_L2_MCAST(vlan_id, index) \ |
| 466 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\ |
| 467 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) |
| 468 | #define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \ |
| 469 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\ |
| 470 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) |
| 471 | #define ROCKER_GROUP_L3_UNICAST(index) \ |
| 472 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\ |
| 473 | ROCKER_GROUP_INDEX_LONG_SET(index)) |
| 474 | |
| 475 | /* |
| 476 | * Rocker general purpose registers |
| 477 | */ |
| 478 | #define ROCKER_CONTROL 0x0300 |
| 479 | #define ROCKER_PORT_PHYS_COUNT 0x0304 |
| 480 | #define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */ |
| 481 | #define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */ |
| 482 | #define ROCKER_SWITCH_ID 0x0320 /* 8-byte */ |
| 483 | |
| 484 | /* |
| 485 | * Rocker control bits |
| 486 | */ |
| 487 | #define ROCKER_CONTROL_RESET (1 << 0) |
| 488 | |
| 489 | #endif /* ROCKER_HW_H */ |