rtl8139.c · samitouri/QOSamiQemu · siGit Code & Deploy

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1	/**
2	* QEMU RTL8139 emulation
3	*
4	* Copyright (c) 2006 Igor Kovalenko
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23
24	* Modifications:
25	* 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26	*
27	* 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28	* HW revision ID changes for FreeBSD driver
29	*
30	* 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31	* Corrected packet transfer reassembly routine for 8139C+ mode
32	* Rearranged debugging print statements
33	* Implemented PCI timer interrupt (disabled by default)
34	* Implemented Tally Counters, increased VM load/save version
35	* Implemented IP/TCP/UDP checksum task offloading
36	*
37	* 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38	* Fixed MTU=1500 for produced ethernet frames
39	*
40	* 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41	* segmentation offloading
42	* Removed slirp.h dependency
43	* Added rx/tx buffer reset when enabling rx/tx operation
44	*
45	* 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46	* when strictly needed (required for
47	* Darwin)
48	* 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49	*/
50
51	#include "qemu/osdep.h"
52	#include <zlib.h> /* for crc32 */
53
54	#include "hw/pci/pci_device.h"
55	#include "hw/core/qdev-properties.h"
56	#include "migration/vmstate.h"
57	#include "system/dma.h"
58	#include "qemu/module.h"
59	#include "qemu/timer.h"
60	#include "qemu/bswap.h"
61	#include "net/net.h"
62	#include "net/eth.h"
63	#include "system/system.h"
64	#include "qom/object.h"
65
66	/* debug RTL8139 card */
67	//#define DEBUG_RTL8139 1
68
69	#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
70
71	#define SET_MASKED(input, mask, curr) \
72	( ( (input) & ~(mask) ) \| ( (curr) & (mask) ) )
73
74	/* arg % size for size which is a power of 2 */
75	#define MOD2(input, size) \
76	( ( input ) & ( size - 1 ) )
77
78	#define ETHER_TYPE_LEN 2
79
80	#define VLAN_TCI_LEN 2
81	#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
82
83	#if defined (DEBUG_RTL8139)
84	# define DPRINTF(fmt, ...) \
85	do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
86	#else
87	static inline G_GNUC_PRINTF(1, 2) int DPRINTF(const char *fmt, ...)
88	{
89	return 0;
90	}
91	#endif
92
93	#define TYPE_RTL8139 "rtl8139"
94
95	OBJECT_DECLARE_SIMPLE_TYPE(RTL8139State, RTL8139)
96
97	/* Symbolic offsets to registers. */
98	enum RTL8139_registers {
99	MAC0 = 0, /* Ethernet hardware address. */
100	MAR0 = 8, /* Multicast filter. */
101	TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
102	/* Dump Tally Counter control register(64bit). C+ mode only */
103	TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
104	RxBuf = 0x30,
105	ChipCmd = 0x37,
106	RxBufPtr = 0x38,
107	RxBufAddr = 0x3A,
108	IntrMask = 0x3C,
109	IntrStatus = 0x3E,
110	TxConfig = 0x40,
111	RxConfig = 0x44,
112	Timer = 0x48, /* A general-purpose counter. */
113	RxMissed = 0x4C, /* 24 bits valid, write clears. */
114	Cfg9346 = 0x50,
115	Config0 = 0x51,
116	Config1 = 0x52,
117	FlashReg = 0x54,
118	MediaStatus = 0x58,
119	Config3 = 0x59,
120	Config4 = 0x5A, /* absent on RTL-8139A */
121	HltClk = 0x5B,
122	MultiIntr = 0x5C,
123	PCIRevisionID = 0x5E,
124	TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
125	BasicModeCtrl = 0x62,
126	BasicModeStatus = 0x64,
127	NWayAdvert = 0x66,
128	NWayLPAR = 0x68,
129	NWayExpansion = 0x6A,
130	/* Undocumented registers, but required for proper operation. */
131	FIFOTMS = 0x70, /* FIFO Control and test. */
132	CSCR = 0x74, /* Chip Status and Configuration Register. */
133	PARA78 = 0x78,
134	PARA7c = 0x7c, /* Magic transceiver parameter register. */
135	Config5 = 0xD8, /* absent on RTL-8139A */
136	/* C+ mode */
137	TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
138	RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
139	CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
140	IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
141	RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
142	RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
143	TxThresh = 0xEC, /* Early Tx threshold */
144	};
145
146	enum ClearBitMasks {
147	MultiIntrClear = 0xF000,
148	ChipCmdClear = 0xE2,
149	Config1Clear = (1<<7)\|(1<<6)\|(1<<3)\|(1<<2)\|(1<<1),
150	};
151
152	enum ChipCmdBits {
153	CmdReset = 0x10,
154	CmdRxEnb = 0x08,
155	CmdTxEnb = 0x04,
156	RxBufEmpty = 0x01,
157	};
158
159	/* C+ mode */
160	enum CplusCmdBits {
161	CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
162	CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
163	CPlusRxEnb = 0x0002,
164	CPlusTxEnb = 0x0001,
165	};
166
167	/* Interrupt register bits, using my own meaningful names. */
168	enum IntrStatusBits {
169	PCIErr = 0x8000,
170	PCSTimeout = 0x4000,
171	RxFIFOOver = 0x40,
172	RxUnderrun = 0x20, /* Packet Underrun / Link Change */
173	RxOverflow = 0x10,
174	TxErr = 0x08,
175	TxOK = 0x04,
176	RxErr = 0x02,
177	RxOK = 0x01,
178
179	RxAckBits = RxFIFOOver \| RxOverflow \| RxOK,
180	};
181
182	enum TxStatusBits {
183	TxHostOwns = 0x2000,
184	TxUnderrun = 0x4000,
185	TxStatOK = 0x8000,
186	TxOutOfWindow = 0x20000000,
187	TxAborted = 0x40000000,
188	TxCarrierLost = 0x80000000,
189	};
190	enum RxStatusBits {
191	RxMulticast = 0x8000,
192	RxPhysical = 0x4000,
193	RxBroadcast = 0x2000,
194	RxBadSymbol = 0x0020,
195	RxRunt = 0x0010,
196	RxTooLong = 0x0008,
197	RxCRCErr = 0x0004,
198	RxBadAlign = 0x0002,
199	RxStatusOK = 0x0001,
200	};
201
202	/* Bits in RxConfig. */
203	enum rx_mode_bits {
204	AcceptErr = 0x20,
205	AcceptRunt = 0x10,
206	AcceptBroadcast = 0x08,
207	AcceptMulticast = 0x04,
208	AcceptMyPhys = 0x02,
209	AcceptAllPhys = 0x01,
210	};
211
212	/* Bits in TxConfig. */
213	enum tx_config_bits {
214
215	/* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
216	TxIFGShift = 24,
217	TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
218	TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
219	TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
220	TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
221
222	TxLoopBack = (1 << 18) \| (1 << 17), /* enable loopback test mode */
223	TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
224	TxClearAbt = (1 << 0), /* Clear abort (WO) */
225	TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
226	TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227
228	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
229	};
230
231
232	/* Transmit Status of All Descriptors (TSAD) Register */
233	enum TSAD_bits {
234	TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
235	TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
236	TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
237	TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
238	TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
239	TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
240	TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
241	TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
242	TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
243	TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
244	TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
245	TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
246	TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
247	TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
248	TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
249	TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
250	};
251
252
253	/* Bits in Config1 */
254	enum Config1Bits {
255	Cfg1_PM_Enable = 0x01,
256	Cfg1_VPD_Enable = 0x02,
257	Cfg1_PIO = 0x04,
258	Cfg1_MMIO = 0x08,
259	LWAKE = 0x10, /* not on 8139, 8139A */
260	Cfg1_Driver_Load = 0x20,
261	Cfg1_LED0 = 0x40,
262	Cfg1_LED1 = 0x80,
263	SLEEP = (1 << 1), /* only on 8139, 8139A */
264	PWRDN = (1 << 0), /* only on 8139, 8139A */
265	};
266
267	/* Bits in Config3 */
268	enum Config3Bits {
269	Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
270	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
271	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
272	Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
273	Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
274	Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
275	Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
276	Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
277	};
278
279	/* Bits in Config4 */
280	enum Config4Bits {
281	LWPTN = (1 << 2), /* not on 8139, 8139A */
282	};
283
284	/* Bits in Config5 */
285	enum Config5Bits {
286	Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
287	Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
288	Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
289	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
290	Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
291	Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
292	Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
293	};
294
295	enum RxConfigBits {
296	/* rx fifo threshold */
297	RxCfgFIFOShift = 13,
298	RxCfgFIFONone = (7 << RxCfgFIFOShift),
299
300	/* Max DMA burst */
301	RxCfgDMAShift = 8,
302	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
303
304	/* rx ring buffer length */
305	RxCfgRcv8K = 0,
306	RxCfgRcv16K = (1 << 11),
307	RxCfgRcv32K = (1 << 12),
308	RxCfgRcv64K = (1 << 11) \| (1 << 12),
309
310	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
311	RxNoWrap = (1 << 7),
312	};
313
314	/* Twister tuning parameters from RealTek.
315	Completely undocumented, but required to tune bad links on some boards. */
316	/*
317	enum CSCRBits {
318	CSCR_LinkOKBit = 0x0400,
319	CSCR_LinkChangeBit = 0x0800,
320	CSCR_LinkStatusBits = 0x0f000,
321	CSCR_LinkDownOffCmd = 0x003c0,
322	CSCR_LinkDownCmd = 0x0f3c0,
323	*/
324	enum CSCRBits {
325	CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
326	CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
327	CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
328	CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
329	CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
330	CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
331	CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
332	CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
333	CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
334	};
335
336	enum Cfg9346Bits {
337	Cfg9346_Normal = 0x00,
338	Cfg9346_Autoload = 0x40,
339	Cfg9346_Programming = 0x80,
340	Cfg9346_ConfigWrite = 0xC0,
341	};
342
343	typedef enum {
344	CH_8139 = 0,
345	CH_8139_K,
346	CH_8139A,
347	CH_8139A_G,
348	CH_8139B,
349	CH_8130,
350	CH_8139C,
351	CH_8100,
352	CH_8100B_8139D,
353	CH_8101,
354	} chip_t;
355
356	enum chip_flags {
357	HasHltClk = (1 << 0),
358	HasLWake = (1 << 1),
359	};
360
361	#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
362	(b30<<30 \| b29<<29 \| b28<<28 \| b27<<27 \| b26<<26 \| b23<<23 \| b22<<22)
363	#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
364
365	#define RTL8139_PCI_REVID_8139 0x10
366	#define RTL8139_PCI_REVID_8139CPLUS 0x20
367
368	#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
369
370	/* Size is 64 * 16bit words */
371	#define EEPROM_9346_ADDR_BITS 6
372	#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
373	#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
374
375	enum Chip9346Operation
376	{
377	Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
378	Chip9346_op_read = 0x80, /* 10 AAAAAA */
379	Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
380	Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
381	Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
382	Chip9346_op_write_all = 0x10, /* 00 01zzzz */
383	Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
384	};
385
386	enum Chip9346Mode
387	{
388	Chip9346_none = 0,
389	Chip9346_enter_command_mode,
390	Chip9346_read_command,
391	Chip9346_data_read, /* from output register */
392	Chip9346_data_write, /* to input register, then to contents at specified address */
393	Chip9346_data_write_all, /* to input register, then filling contents */
394	};
395
396	typedef struct EEprom9346
397	{
398	uint16_t contents[EEPROM_9346_SIZE];
399	int mode;
400	uint32_t tick;
401	uint8_t address;
402	uint16_t input;
403	uint16_t output;
404
405	uint8_t eecs;
406	uint8_t eesk;
407	uint8_t eedi;
408	uint8_t eedo;
409	} EEprom9346;
410
411	typedef struct RTL8139TallyCounters
412	{
413	/* Tally counters */
414	uint64_t TxOk;
415	uint64_t RxOk;
416	uint64_t TxERR;
417	uint32_t RxERR;
418	uint16_t MissPkt;
419	uint16_t FAE;
420	uint32_t Tx1Col;
421	uint32_t TxMCol;
422	uint64_t RxOkPhy;
423	uint64_t RxOkBrd;
424	uint32_t RxOkMul;
425	uint16_t TxAbt;
426	uint16_t TxUndrn;
427	} RTL8139TallyCounters;
428
429	/* Clears all tally counters */
430	static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
431
432	struct RTL8139State {
433	/< private >/
434	PCIDevice parent_obj;
435	/< public >/
436
437	uint8_t phys[8]; /* mac address */
438	uint8_t mult[8]; /* multicast mask array */
439
440	uint32_t TxStatus[4]; /* TxStatus0 in C mode/ / also DTCCR[0] and DTCCR[1] in C+ mode */
441	uint32_t TxAddr[4]; /* TxAddr0 */
442	uint32_t RxBuf; /* Receive buffer */
443	uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
444	uint32_t RxBufPtr;
445	uint32_t RxBufAddr;
446
447	uint16_t IntrStatus;
448	uint16_t IntrMask;
449
450	uint32_t TxConfig;
451	uint32_t RxConfig;
452	uint32_t RxMissed;
453
454	uint16_t CSCR;
455
456	uint8_t Cfg9346;
457	uint8_t Config0;
458	uint8_t Config1;
459	uint8_t Config3;
460	uint8_t Config4;
461	uint8_t Config5;
462
463	uint8_t clock_enabled;
464	uint8_t bChipCmdState;
465
466	uint16_t MultiIntr;
467
468	uint16_t BasicModeCtrl;
469	uint16_t BasicModeStatus;
470	uint16_t NWayAdvert;
471	uint16_t NWayLPAR;
472	uint16_t NWayExpansion;
473
474	uint16_t CpCmd;
475	uint8_t TxThresh;
476
477	NICState *nic;
478	NICConf conf;
479
480	/* C ring mode */
481	uint32_t currTxDesc;
482
483	/* C+ mode */
484	uint32_t cplus_enabled;
485
486	uint32_t currCPlusRxDesc;
487	uint32_t currCPlusTxDesc;
488
489	uint32_t RxRingAddrLO;
490	uint32_t RxRingAddrHI;
491
492	EEprom9346 eeprom;
493
494	uint32_t TCTR;
495	uint32_t TimerInt;
496	int64_t TCTR_base;
497
498	/* Tally counters */
499	RTL8139TallyCounters tally_counters;
500
501	/* Non-persistent data */
502	uint8_t *cplus_txbuffer;
503	int cplus_txbuffer_len;
504	int cplus_txbuffer_offset;
505
506	/* PCI interrupt timer */
507	QEMUTimer *timer;
508
509	MemoryRegion bar_io;
510	MemoryRegion bar_mem;
511
512	/* Support migration to/from old versions */
513	int rtl8139_mmio_io_addr_dummy;
514	};
515
516	/* Writes tally counters to memory via DMA */
517	static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
518
519	static void rtl8139_set_next_tctr_time(RTL8139State *s);
520
521	static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
522	{
523	DPRINTF("eeprom command 0x%02x\n", command);
524
525	switch (command & Chip9346_op_mask)
526	{
527	case Chip9346_op_read:
528	{
529	eeprom->address = command & EEPROM_9346_ADDR_MASK;
530	eeprom->output = eeprom->contents[eeprom->address];
531	eeprom->eedo = 0;
532	eeprom->tick = 0;
533	eeprom->mode = Chip9346_data_read;
534	DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
535	eeprom->address, eeprom->output);
536	}
537	break;
538
539	case Chip9346_op_write:
540	{
541	eeprom->address = command & EEPROM_9346_ADDR_MASK;
542	eeprom->input = 0;
543	eeprom->tick = 0;
544	eeprom->mode = Chip9346_none; /* Chip9346_data_write */
545	DPRINTF("eeprom begin write to address 0x%02x\n",
546	eeprom->address);
547	}
548	break;
549	default:
550	eeprom->mode = Chip9346_none;
551	switch (command & Chip9346_op_ext_mask)
552	{
553	case Chip9346_op_write_enable:
554	DPRINTF("eeprom write enabled\n");
555	break;
556	case Chip9346_op_write_all:
557	DPRINTF("eeprom begin write all\n");
558	break;
559	case Chip9346_op_write_disable:
560	DPRINTF("eeprom write disabled\n");
561	break;
562	}
563	break;
564	}
565	}
566
567	static void prom9346_shift_clock(EEprom9346 *eeprom)
568	{
569	int bit = eeprom->eedi?1:0;
570
571	++ eeprom->tick;
572
573	DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
574	eeprom->eedo);
575
576	switch (eeprom->mode)
577	{
578	case Chip9346_enter_command_mode:
579	if (bit)
580	{
581	eeprom->mode = Chip9346_read_command;
582	eeprom->tick = 0;
583	eeprom->input = 0;
584	DPRINTF("eeprom: +++ synchronized, begin command read\n");
585	}
586	break;
587
588	case Chip9346_read_command:
589	eeprom->input = (eeprom->input << 1) \| (bit & 1);
590	if (eeprom->tick == 8)
591	{
592	prom9346_decode_command(eeprom, eeprom->input & 0xff);
593	}
594	break;
595
596	case Chip9346_data_read:
597	eeprom->eedo = (eeprom->output & 0x8000)?1:0;
598	eeprom->output <<= 1;
599	if (eeprom->tick == 16)
600	{
601	#if 1
602	// the FreeBSD drivers (rl and re) don't explicitly toggle
603	// CS between reads (or does setting Cfg9346 to 0 count too?),
604	// so we need to enter wait-for-command state here
605	eeprom->mode = Chip9346_enter_command_mode;
606	eeprom->input = 0;
607	eeprom->tick = 0;
608
609	DPRINTF("eeprom: +++ end of read, awaiting next command\n");
610	#else
611	// original behaviour
612	++eeprom->address;
613	eeprom->address &= EEPROM_9346_ADDR_MASK;
614	eeprom->output = eeprom->contents[eeprom->address];
615	eeprom->tick = 0;
616
617	DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
618	eeprom->address, eeprom->output);
619	#endif
620	}
621	break;
622
623	case Chip9346_data_write:
624	eeprom->input = (eeprom->input << 1) \| (bit & 1);
625	if (eeprom->tick == 16)
626	{
627	DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
628	eeprom->address, eeprom->input);
629
630	eeprom->contents[eeprom->address] = eeprom->input;
631	eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
632	eeprom->tick = 0;
633	eeprom->input = 0;
634	}
635	break;
636
637	case Chip9346_data_write_all:
638	eeprom->input = (eeprom->input << 1) \| (bit & 1);
639	if (eeprom->tick == 16)
640	{
641	int i;
642	for (i = 0; i < EEPROM_9346_SIZE; i++)
643	{
644	eeprom->contents[i] = eeprom->input;
645	}
646	DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
647
648	eeprom->mode = Chip9346_enter_command_mode;
649	eeprom->tick = 0;
650	eeprom->input = 0;
651	}
652	break;
653
654	default:
655	break;
656	}
657	}
658
659	static int prom9346_get_wire(RTL8139State *s)
660	{
661	EEprom9346 *eeprom = &s->eeprom;
662	if (!eeprom->eecs)
663	return 0;
664
665	return eeprom->eedo;
666	}
667
668	/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
669	static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
670	{
671	EEprom9346 *eeprom = &s->eeprom;
672	uint8_t old_eecs = eeprom->eecs;
673	uint8_t old_eesk = eeprom->eesk;
674
675	eeprom->eecs = eecs;
676	eeprom->eesk = eesk;
677	eeprom->eedi = eedi;
678
679	DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
680	eeprom->eesk, eeprom->eedi, eeprom->eedo);
681
682	if (!old_eecs && eecs)
683	{
684	/* Synchronize start */
685	eeprom->tick = 0;
686	eeprom->input = 0;
687	eeprom->output = 0;
688	eeprom->mode = Chip9346_enter_command_mode;
689
690	DPRINTF("=== eeprom: begin access, enter command mode\n");
691	}
692
693	if (!eecs)
694	{
695	DPRINTF("=== eeprom: end access\n");
696	return;
697	}
698
699	if (!old_eesk && eesk)
700	{
701	/* SK front rules */
702	prom9346_shift_clock(eeprom);
703	}
704	}
705
706	static void rtl8139_update_irq(RTL8139State *s)
707	{
708	PCIDevice *d = PCI_DEVICE(s);
709	int isr;
710	isr = (s->IntrStatus & s->IntrMask) & 0xffff;
711
712	DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
713	s->IntrMask);
714
715	pci_set_irq(d, (isr != 0));
716	}
717
718	static int rtl8139_RxWrap(RTL8139State *s)
719	{
720	/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
721	return (s->RxConfig & (1 << 7));
722	}
723
724	static int rtl8139_receiver_enabled(RTL8139State *s)
725	{
726	return s->bChipCmdState & CmdRxEnb;
727	}
728
729	static int rtl8139_transmitter_enabled(RTL8139State *s)
730	{
731	return s->bChipCmdState & CmdTxEnb;
732	}
733
734	static int rtl8139_cp_receiver_enabled(RTL8139State *s)
735	{
736	return s->CpCmd & CPlusRxEnb;
737	}
738
739	static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
740	{
741	return s->CpCmd & CPlusTxEnb;
742	}
743
744	static void rtl8139_write_buffer(RTL8139State s, const void buf, int size)
745	{
746	PCIDevice *d = PCI_DEVICE(s);
747
748	if (s->RxBufAddr + size > s->RxBufferSize)
749	{
750	int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
751
752	/* write packet data */
753	if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
754	{
755	DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
756
757	if (size > wrapped)
758	{
759	pci_dma_write(d, s->RxBuf + s->RxBufAddr,
760	buf, size-wrapped);
761	}
762
763	/* reset buffer pointer */
764	s->RxBufAddr = 0;
765
766	pci_dma_write(d, s->RxBuf + s->RxBufAddr,
767	buf + (size-wrapped), wrapped);
768
769	s->RxBufAddr = wrapped;
770
771	return;
772	}
773	}
774
775	/* non-wrapping path or overwrapping enabled */
776	pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
777
778	s->RxBufAddr += size;
779	}
780
781	static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
782	{
783	return low \| ((uint64_t)high << 32);
784	}
785
786	/* Workaround for buggy guest driver such as linux who allocates rx
787	* rings after the receiver were enabled. */
788	static bool rtl8139_cp_rx_valid(RTL8139State *s)
789	{
790	return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
791	}
792
793	static bool rtl8139_can_receive(NetClientState *nc)
794	{
795	RTL8139State *s = qemu_get_nic_opaque(nc);
796	int avail;
797
798	/* Receive (drop) packets if card is disabled. */
799	if (!s->clock_enabled) {
800	return true;
801	}
802	if (!rtl8139_receiver_enabled(s)) {
803	return true;
804	}
805
806	if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
807	/* ??? Flow control not implemented in c+ mode.
808	This is a hack to work around slirp deficiencies anyway. */
809	return true;
810	}
811
812	avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
813	s->RxBufferSize);
814	return avail == 0 \|\| avail >= 1514 \|\| (s->IntrMask & RxOverflow);
815	}
816
817	static ssize_t rtl8139_receive(NetClientState *nc,
818	const uint8_t *buf, size_t size_)
819	{
820	RTL8139State *s = qemu_get_nic_opaque(nc);
821	PCIDevice *d = PCI_DEVICE(s);
822	/* size is the length of the buffer passed to the driver */
823	size_t size = size_;
824	const uint8_t *dot1q_buf = NULL;
825
826	uint32_t packet_header = 0;
827
828	static const uint8_t broadcast_macaddr[6] =
829	{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
830
831	DPRINTF(">>> received len=%zu\n", size);
832
833	/* test if board clock is stopped */
834	if (!s->clock_enabled)
835	{
836	DPRINTF("stopped ==========================\n");
837	return -1;
838	}
839
840	/* first check if receiver is enabled */
841
842	if (!rtl8139_receiver_enabled(s))
843	{
844	DPRINTF("receiver disabled ================\n");
845	return -1;
846	}
847
848	/* XXX: check this */
849	if (s->RxConfig & AcceptAllPhys) {
850	/* promiscuous: receive all */
851	DPRINTF(">>> packet received in promiscuous mode\n");
852
853	} else {
854	if (!memcmp(buf, broadcast_macaddr, 6)) {
855	/* broadcast address */
856	if (!(s->RxConfig & AcceptBroadcast))
857	{
858	DPRINTF(">>> broadcast packet rejected\n");
859
860	/* update tally counter */
861	++s->tally_counters.RxERR;
862
863	return size;
864	}
865
866	packet_header \|= RxBroadcast;
867
868	DPRINTF(">>> broadcast packet received\n");
869
870	/* update tally counter */
871	++s->tally_counters.RxOkBrd;
872
873	} else if (buf[0] & 0x01) {
874	/* multicast */
875	if (!(s->RxConfig & AcceptMulticast))
876	{
877	DPRINTF(">>> multicast packet rejected\n");
878
879	/* update tally counter */
880	++s->tally_counters.RxERR;
881
882	return size;
883	}
884
885	int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
886
887	if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
888	{
889	DPRINTF(">>> multicast address mismatch\n");
890
891	/* update tally counter */
892	++s->tally_counters.RxERR;
893
894	return size;
895	}
896
897	packet_header \|= RxMulticast;
898
899	DPRINTF(">>> multicast packet received\n");
900
901	/* update tally counter */
902	++s->tally_counters.RxOkMul;
903
904	} else if (s->phys[0] == buf[0] &&
905	s->phys[1] == buf[1] &&
906	s->phys[2] == buf[2] &&
907	s->phys[3] == buf[3] &&
908	s->phys[4] == buf[4] &&
909	s->phys[5] == buf[5]) {
910	/* match */
911	if (!(s->RxConfig & AcceptMyPhys))
912	{
913	DPRINTF(">>> rejecting physical address matching packet\n");
914
915	/* update tally counter */
916	++s->tally_counters.RxERR;
917
918	return size;
919	}
920
921	packet_header \|= RxPhysical;
922
923	DPRINTF(">>> physical address matching packet received\n");
924
925	/* update tally counter */
926	++s->tally_counters.RxOkPhy;
927
928	} else {
929
930	DPRINTF(">>> unknown packet\n");
931
932	/* update tally counter */
933	++s->tally_counters.RxERR;
934
935	return size;
936	}
937	}
938
939	if (rtl8139_cp_receiver_enabled(s))
940	{
941	if (!rtl8139_cp_rx_valid(s)) {
942	return size;
943	}
944
945	DPRINTF("in C+ Rx mode ================\n");
946
947	/* begin C+ receiver mode */
948
949	/* w0 ownership flag */
950	#define CP_RX_OWN (1<<31)
951	/* w0 end of ring flag */
952	#define CP_RX_EOR (1<<30)
953	/* w0 bits 0...12 : buffer size */
954	#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
955	/* w1 tag available flag */
956	#define CP_RX_TAVA (1<<16)
957	/* w1 bits 0...15 : VLAN tag */
958	#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
959	/* w2 low 32bit of Rx buffer ptr */
960	/* w3 high 32bit of Rx buffer ptr */
961
962	int descriptor = s->currCPlusRxDesc;
963	dma_addr_t cplus_rx_ring_desc;
964
965	cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
966	cplus_rx_ring_desc += 16 * descriptor;
967
968	DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
969	"%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
970	s->RxRingAddrLO, cplus_rx_ring_desc);
971
972	uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
973
974	pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
975	rxdw0 = le32_to_cpu(val);
976	pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
977	rxdw1 = le32_to_cpu(val);
978	pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
979	rxbufLO = le32_to_cpu(val);
980	pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
981	rxbufHI = le32_to_cpu(val);
982
983	DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
984	descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
985
986	if (!(rxdw0 & CP_RX_OWN))
987	{
988	DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
989	descriptor);
990
991	s->IntrStatus \|= RxOverflow;
992	++s->RxMissed;
993
994	/* update tally counter */
995	++s->tally_counters.RxERR;
996	++s->tally_counters.MissPkt;
997
998	rtl8139_update_irq(s);
999	return size_;
1000	}
1001
1002	uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1003
1004	/* write VLAN info to descriptor variables. */
1005	if (s->CpCmd & CPlusRxVLAN &&
1006	lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) {
1007	dot1q_buf = &buf[ETH_ALEN * 2];
1008	size -= VLAN_HLEN;
1009
1010	rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1011	/* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1012	rxdw1 \|= CP_RX_TAVA \| lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]);
1013
1014	DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1015	lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN]));
1016	} else {
1017	/* reset VLAN tag flag */
1018	rxdw1 &= ~CP_RX_TAVA;
1019	}
1020
1021	/* TODO: scatter the packet over available receive ring descriptors space */
1022
1023	if (size+4 > rx_space)
1024	{
1025	DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n",
1026	descriptor, rx_space, size);
1027
1028	s->IntrStatus \|= RxOverflow;
1029	++s->RxMissed;
1030
1031	/* update tally counter */
1032	++s->tally_counters.RxERR;
1033	++s->tally_counters.MissPkt;
1034
1035	rtl8139_update_irq(s);
1036	return size_;
1037	}
1038
1039	dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1040
1041	/* receive/copy to target memory */
1042	if (dot1q_buf) {
1043	pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN);
1044	pci_dma_write(d, rx_addr + 2 * ETH_ALEN,
1045	buf + 2 * ETH_ALEN + VLAN_HLEN,
1046	size - 2 * ETH_ALEN);
1047	} else {
1048	pci_dma_write(d, rx_addr, buf, size);
1049	}
1050
1051	if (s->CpCmd & CPlusRxChkSum)
1052	{
1053	/* do some packet checksumming */
1054	}
1055
1056	/* write checksum */
1057	val = cpu_to_le32(crc32(0, buf, size_));
1058	pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
1059
1060	/* first segment of received packet flag */
1061	#define CP_RX_STATUS_FS (1<<29)
1062	/* last segment of received packet flag */
1063	#define CP_RX_STATUS_LS (1<<28)
1064	/* multicast packet flag */
1065	#define CP_RX_STATUS_MAR (1<<26)
1066	/* physical-matching packet flag */
1067	#define CP_RX_STATUS_PAM (1<<25)
1068	/* broadcast packet flag */
1069	#define CP_RX_STATUS_BAR (1<<24)
1070	/* runt packet flag */
1071	#define CP_RX_STATUS_RUNT (1<<19)
1072	/* crc error flag */
1073	#define CP_RX_STATUS_CRC (1<<18)
1074	/* IP checksum error flag */
1075	#define CP_RX_STATUS_IPF (1<<15)
1076	/* UDP checksum error flag */
1077	#define CP_RX_STATUS_UDPF (1<<14)
1078	/* TCP checksum error flag */
1079	#define CP_RX_STATUS_TCPF (1<<13)
1080
1081	/* transfer ownership to target */
1082	rxdw0 &= ~CP_RX_OWN;
1083
1084	/* set first segment bit */
1085	rxdw0 \|= CP_RX_STATUS_FS;
1086
1087	/* set last segment bit */
1088	rxdw0 \|= CP_RX_STATUS_LS;
1089
1090	/* set received packet type flags */
1091	if (packet_header & RxBroadcast)
1092	rxdw0 \|= CP_RX_STATUS_BAR;
1093	if (packet_header & RxMulticast)
1094	rxdw0 \|= CP_RX_STATUS_MAR;
1095	if (packet_header & RxPhysical)
1096	rxdw0 \|= CP_RX_STATUS_PAM;
1097
1098	/* set received size */
1099	rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1100	rxdw0 \|= (size+4);
1101
1102	/* update ring data */
1103	val = cpu_to_le32(rxdw0);
1104	pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1105	val = cpu_to_le32(rxdw1);
1106	pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1107
1108	/* update tally counter */
1109	++s->tally_counters.RxOk;
1110
1111	/* seek to next Rx descriptor */
1112	if (rxdw0 & CP_RX_EOR)
1113	{
1114	s->currCPlusRxDesc = 0;
1115	}
1116	else
1117	{
1118	++s->currCPlusRxDesc;
1119	}
1120
1121	DPRINTF("done C+ Rx mode ----------------\n");
1122
1123	}
1124	else
1125	{
1126	DPRINTF("in ring Rx mode ================\n");
1127
1128	/* begin ring receiver mode */
1129	int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1130
1131	/* if receiver buffer is empty then avail == 0 */
1132
1133	#define RX_ALIGN(x) (((x) + 3) & ~0x3)
1134
1135	if (avail != 0 && RX_ALIGN(size + 8) >= avail)
1136	{
1137	DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1138	"read 0x%04x === available 0x%04x need 0x%04zx\n",
1139	s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1140
1141	s->IntrStatus \|= RxOverflow;
1142	++s->RxMissed;
1143	rtl8139_update_irq(s);
1144	return 0;
1145	}
1146
1147	packet_header \|= RxStatusOK;
1148
1149	packet_header \|= (((size+4) << 16) & 0xffff0000);
1150
1151	/* write header */
1152	uint32_t val = cpu_to_le32(packet_header);
1153
1154	rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1155
1156	rtl8139_write_buffer(s, buf, size);
1157
1158	/* write checksum */
1159	val = cpu_to_le32(crc32(0, buf, size));
1160	rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1161
1162	/* correct buffer write pointer */
1163	s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
1164
1165	/* now we can signal we have received something */
1166
1167	DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1168	s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1169	}
1170
1171	s->IntrStatus \|= RxOK;
1172	rtl8139_update_irq(s);
1173
1174	return size_;
1175	}
1176
1177	static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1178	{
1179	s->RxBufferSize = bufferSize;
1180	s->RxBufPtr = 0;
1181	s->RxBufAddr = 0;
1182	}
1183
1184	static void rtl8139_reset_phy(RTL8139State *s)
1185	{
1186	s->BasicModeStatus = 0x7809;
1187	s->BasicModeStatus \|= 0x0020; /* autonegotiation completed */
1188	/* preserve link state */
1189	s->BasicModeStatus \|= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1190
1191	s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1192	s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1193	s->NWayExpansion = 0x0001; /* autonegotiation supported */
1194
1195	s->CSCR = CSCR_F_LINK_100 \| CSCR_HEART_BIT \| CSCR_LD;
1196	}
1197
1198	static void rtl8139_reset(DeviceState *d)
1199	{
1200	RTL8139State *s = RTL8139(d);
1201	int i;
1202
1203	/* restore MAC address */
1204	memcpy(s->phys, s->conf.macaddr.a, 6);
1205	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
1206
1207	/* reset interrupt mask */
1208	s->IntrStatus = 0;
1209	s->IntrMask = 0;
1210
1211	rtl8139_update_irq(s);
1212
1213	/* mark all status registers as owned by host */
1214	for (i = 0; i < 4; ++i)
1215	{
1216	s->TxStatus[i] = TxHostOwns;
1217	}
1218
1219	s->currTxDesc = 0;
1220	s->currCPlusRxDesc = 0;
1221	s->currCPlusTxDesc = 0;
1222
1223	s->RxRingAddrLO = 0;
1224	s->RxRingAddrHI = 0;
1225
1226	s->RxBuf = 0;
1227
1228	rtl8139_reset_rxring(s, 8192);
1229
1230	/* ACK the reset */
1231	s->TxConfig = 0;
1232
1233	#if 0
1234	// s->TxConfig \|= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1235	s->clock_enabled = 0;
1236	#else
1237	s->TxConfig \|= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1238	s->clock_enabled = 1;
1239	#endif
1240
1241	s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1242
1243	/* set initial state data */
1244	s->Config0 = 0x0; /* No boot ROM */
1245	s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1246	s->Config3 = 0x1; /* fast back-to-back compatible */
1247	s->Config5 = 0x0;
1248
1249	s->CpCmd = 0x0; /* reset C+ mode */
1250	s->cplus_enabled = 0;
1251
1252	// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1253	// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1254	s->BasicModeCtrl = 0x1000; // autonegotiation
1255
1256	rtl8139_reset_phy(s);
1257
1258	/* also reset timer and disable timer interrupt */
1259	s->TCTR = 0;
1260	s->TimerInt = 0;
1261	s->TCTR_base = 0;
1262	rtl8139_set_next_tctr_time(s);
1263
1264	/* reset tally counters */
1265	RTL8139TallyCounters_clear(&s->tally_counters);
1266	}
1267
1268	static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1269	{
1270	counters->TxOk = 0;
1271	counters->RxOk = 0;
1272	counters->TxERR = 0;
1273	counters->RxERR = 0;
1274	counters->MissPkt = 0;
1275	counters->FAE = 0;
1276	counters->Tx1Col = 0;
1277	counters->TxMCol = 0;
1278	counters->RxOkPhy = 0;
1279	counters->RxOkBrd = 0;
1280	counters->RxOkMul = 0;
1281	counters->TxAbt = 0;
1282	counters->TxUndrn = 0;
1283	}
1284
1285	static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1286	{
1287	PCIDevice *d = PCI_DEVICE(s);
1288	RTL8139TallyCounters *tally_counters = &s->tally_counters;
1289	uint16_t val16;
1290	uint32_t val32;
1291	uint64_t val64;
1292
1293	val64 = cpu_to_le64(tally_counters->TxOk);
1294	pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1295
1296	val64 = cpu_to_le64(tally_counters->RxOk);
1297	pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1298
1299	val64 = cpu_to_le64(tally_counters->TxERR);
1300	pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1301
1302	val32 = cpu_to_le32(tally_counters->RxERR);
1303	pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1304
1305	val16 = cpu_to_le16(tally_counters->MissPkt);
1306	pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1307
1308	val16 = cpu_to_le16(tally_counters->FAE);
1309	pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1310
1311	val32 = cpu_to_le32(tally_counters->Tx1Col);
1312	pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1313
1314	val32 = cpu_to_le32(tally_counters->TxMCol);
1315	pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1316
1317	val64 = cpu_to_le64(tally_counters->RxOkPhy);
1318	pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1319
1320	val64 = cpu_to_le64(tally_counters->RxOkBrd);
1321	pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1322
1323	val32 = cpu_to_le32(tally_counters->RxOkMul);
1324	pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1325
1326	val16 = cpu_to_le16(tally_counters->TxAbt);
1327	pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1328
1329	val16 = cpu_to_le16(tally_counters->TxUndrn);
1330	pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1331	}
1332
1333	static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1334	{
1335	DeviceState *d = DEVICE(s);
1336
1337	val &= 0xff;
1338
1339	DPRINTF("ChipCmd write val=0x%08x\n", val);
1340
1341	if (val & CmdReset)
1342	{
1343	DPRINTF("ChipCmd reset\n");
1344	rtl8139_reset(d);
1345	}
1346	if (val & CmdRxEnb)
1347	{
1348	DPRINTF("ChipCmd enable receiver\n");
1349
1350	s->currCPlusRxDesc = 0;
1351	}
1352	if (val & CmdTxEnb)
1353	{
1354	DPRINTF("ChipCmd enable transmitter\n");
1355
1356	s->currCPlusTxDesc = 0;
1357	}
1358
1359	/* mask unwritable bits */
1360	val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1361
1362	/* Deassert reset pin before next read */
1363	val &= ~CmdReset;
1364
1365	s->bChipCmdState = val;
1366	}
1367
1368	static int rtl8139_RxBufferEmpty(RTL8139State *s)
1369	{
1370	int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1371
1372	if (unread != 0)
1373	{
1374	DPRINTF("receiver buffer data available 0x%04x\n", unread);
1375	return 0;
1376	}
1377
1378	DPRINTF("receiver buffer is empty\n");
1379
1380	return 1;
1381	}
1382
1383	static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1384	{
1385	uint32_t ret = s->bChipCmdState;
1386
1387	if (rtl8139_RxBufferEmpty(s))
1388	ret \|= RxBufEmpty;
1389
1390	DPRINTF("ChipCmd read val=0x%04x\n", ret);
1391
1392	return ret;
1393	}
1394
1395	static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1396	{
1397	val &= 0xffff;
1398
1399	DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1400
1401	s->cplus_enabled = 1;
1402
1403	/* mask unwritable bits */
1404	val = SET_MASKED(val, 0xff84, s->CpCmd);
1405
1406	s->CpCmd = val;
1407	}
1408
1409	static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1410	{
1411	uint32_t ret = s->CpCmd;
1412
1413	DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1414
1415	return ret;
1416	}
1417
1418	static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1419	{
1420	DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1421	}
1422
1423	static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1424	{
1425	uint32_t ret = 0;
1426
1427	DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1428
1429	return ret;
1430	}
1431
1432	static int rtl8139_config_writable(RTL8139State *s)
1433	{
1434	if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1435	{
1436	return 1;
1437	}
1438
1439	DPRINTF("Configuration registers are write-protected\n");
1440
1441	return 0;
1442	}
1443
1444	static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1445	{
1446	val &= 0xffff;
1447
1448	DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1449
1450	/* mask unwritable bits */
1451	uint32_t mask = 0xccff;
1452
1453	if (1 \|\| !rtl8139_config_writable(s))
1454	{
1455	/* Speed setting and autonegotiation enable bits are read-only */
1456	mask \|= 0x3000;
1457	/* Duplex mode setting is read-only */
1458	mask \|= 0x0100;
1459	}
1460
1461	if (val & 0x8000) {
1462	/* Reset PHY */
1463	rtl8139_reset_phy(s);
1464	}
1465
1466	val = SET_MASKED(val, mask, s->BasicModeCtrl);
1467
1468	s->BasicModeCtrl = val;
1469	}
1470
1471	static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1472	{
1473	uint32_t ret = s->BasicModeCtrl;
1474
1475	DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1476
1477	return ret;
1478	}
1479
1480	static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1481	{
1482	val &= 0xffff;
1483
1484	DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1485
1486	/* mask unwritable bits */
1487	val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1488
1489	s->BasicModeStatus = val;
1490	}
1491
1492	static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1493	{
1494	uint32_t ret = s->BasicModeStatus;
1495
1496	DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1497
1498	return ret;
1499	}
1500
1501	static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1502	{
1503	DeviceState *d = DEVICE(s);
1504
1505	val &= 0xff;
1506
1507	DPRINTF("Cfg9346 write val=0x%02x\n", val);
1508
1509	/* mask unwritable bits */
1510	val = SET_MASKED(val, 0x31, s->Cfg9346);
1511
1512	uint32_t opmode = val & 0xc0;
1513	uint32_t eeprom_val = val & 0xf;
1514
1515	if (opmode == 0x80) {
1516	/* eeprom access */
1517	int eecs = (eeprom_val & 0x08)?1:0;
1518	int eesk = (eeprom_val & 0x04)?1:0;
1519	int eedi = (eeprom_val & 0x02)?1:0;
1520	prom9346_set_wire(s, eecs, eesk, eedi);
1521	} else if (opmode == 0x40) {
1522	/* Reset. */
1523	val = 0;
1524	rtl8139_reset(d);
1525	}
1526
1527	s->Cfg9346 = val;
1528	}
1529
1530	static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1531	{
1532	uint32_t ret = s->Cfg9346;
1533
1534	uint32_t opmode = ret & 0xc0;
1535
1536	if (opmode == 0x80)
1537	{
1538	/* eeprom access */
1539	int eedo = prom9346_get_wire(s);
1540	if (eedo)
1541	{
1542	ret \|= 0x01;
1543	}
1544	else
1545	{
1546	ret &= ~0x01;
1547	}
1548	}
1549
1550	DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1551
1552	return ret;
1553	}
1554
1555	static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1556	{
1557	val &= 0xff;
1558
1559	DPRINTF("Config0 write val=0x%02x\n", val);
1560
1561	if (!rtl8139_config_writable(s)) {
1562	return;
1563	}
1564
1565	/* mask unwritable bits */
1566	val = SET_MASKED(val, 0xf8, s->Config0);
1567
1568	s->Config0 = val;
1569	}
1570
1571	static uint32_t rtl8139_Config0_read(RTL8139State *s)
1572	{
1573	uint32_t ret = s->Config0;
1574
1575	DPRINTF("Config0 read val=0x%02x\n", ret);
1576
1577	return ret;
1578	}
1579
1580	static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1581	{
1582	val &= 0xff;
1583
1584	DPRINTF("Config1 write val=0x%02x\n", val);
1585
1586	if (!rtl8139_config_writable(s)) {
1587	return;
1588	}
1589
1590	/* mask unwritable bits */
1591	val = SET_MASKED(val, 0xC, s->Config1);
1592
1593	s->Config1 = val;
1594	}
1595
1596	static uint32_t rtl8139_Config1_read(RTL8139State *s)
1597	{
1598	uint32_t ret = s->Config1;
1599
1600	DPRINTF("Config1 read val=0x%02x\n", ret);
1601
1602	return ret;
1603	}
1604
1605	static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1606	{
1607	val &= 0xff;
1608
1609	DPRINTF("Config3 write val=0x%02x\n", val);
1610
1611	if (!rtl8139_config_writable(s)) {
1612	return;
1613	}
1614
1615	/* mask unwritable bits */
1616	val = SET_MASKED(val, 0x8F, s->Config3);
1617
1618	s->Config3 = val;
1619	}
1620
1621	static uint32_t rtl8139_Config3_read(RTL8139State *s)
1622	{
1623	uint32_t ret = s->Config3;
1624
1625	DPRINTF("Config3 read val=0x%02x\n", ret);
1626
1627	return ret;
1628	}
1629
1630	static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1631	{
1632	val &= 0xff;
1633
1634	DPRINTF("Config4 write val=0x%02x\n", val);
1635
1636	if (!rtl8139_config_writable(s)) {
1637	return;
1638	}
1639
1640	/* mask unwritable bits */
1641	val = SET_MASKED(val, 0x0a, s->Config4);
1642
1643	s->Config4 = val;
1644	}
1645
1646	static uint32_t rtl8139_Config4_read(RTL8139State *s)
1647	{
1648	uint32_t ret = s->Config4;
1649
1650	DPRINTF("Config4 read val=0x%02x\n", ret);
1651
1652	return ret;
1653	}
1654
1655	static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1656	{
1657	val &= 0xff;
1658
1659	DPRINTF("Config5 write val=0x%02x\n", val);
1660
1661	/* mask unwritable bits */
1662	val = SET_MASKED(val, 0x80, s->Config5);
1663
1664	s->Config5 = val;
1665	}
1666
1667	static uint32_t rtl8139_Config5_read(RTL8139State *s)
1668	{
1669	uint32_t ret = s->Config5;
1670
1671	DPRINTF("Config5 read val=0x%02x\n", ret);
1672
1673	return ret;
1674	}
1675
1676	static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1677	{
1678	if (!rtl8139_transmitter_enabled(s))
1679	{
1680	DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1681	return;
1682	}
1683
1684	DPRINTF("TxConfig write val=0x%08x\n", val);
1685
1686	val = SET_MASKED(val, TxVersionMask \| 0x8070f80f, s->TxConfig);
1687
1688	s->TxConfig = val;
1689	}
1690
1691	static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1692	{
1693	DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1694
1695	uint32_t tc = s->TxConfig;
1696	tc &= 0xFFFFFF00;
1697	tc \|= (val & 0x000000FF);
1698	rtl8139_TxConfig_write(s, tc);
1699	}
1700
1701	static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1702	{
1703	uint32_t ret = s->TxConfig;
1704
1705	DPRINTF("TxConfig read val=0x%04x\n", ret);
1706
1707	return ret;
1708	}
1709
1710	static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1711	{
1712	DPRINTF("RxConfig write val=0x%08x\n", val);
1713
1714	/* mask unwritable bits */
1715	val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1716
1717	s->RxConfig = val;
1718
1719	/* reset buffer size and read/write pointers */
1720	rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1721
1722	DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1723	}
1724
1725	static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1726	{
1727	uint32_t ret = s->RxConfig;
1728
1729	DPRINTF("RxConfig read val=0x%08x\n", ret);
1730
1731	return ret;
1732	}
1733
1734	static void rtl8139_transfer_frame(RTL8139State s, uint8_t buf, int size,
1735	const uint8_t *dot1q_buf)
1736	{
1737	struct iovec *iov = NULL;
1738	struct iovec vlan_iov[3];
1739
1740	if (!size)
1741	{
1742	DPRINTF("+++ empty ethernet frame\n");
1743	return;
1744	}
1745
1746	if (dot1q_buf && size >= ETH_ALEN * 2) {
1747	iov = (struct iovec[3]) {
1748	{ .iov_base = buf, .iov_len = ETH_ALEN * 2 },
1749	{ .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1750	{ .iov_base = buf + ETH_ALEN * 2,
1751	.iov_len = size - ETH_ALEN * 2 },
1752	};
1753
1754	memcpy(vlan_iov, iov, sizeof(vlan_iov));
1755	iov = vlan_iov;
1756	}
1757
1758	if (TxLoopBack == (s->TxConfig & TxLoopBack))
1759	{
1760	size_t buf2_size;
1761	uint8_t *buf2;
1762
1763	if (iov) {
1764	buf2_size = iov_size(iov, 3);
1765	buf2 = g_malloc(buf2_size);
1766	iov_to_buf(iov, 3, 0, buf2, buf2_size);
1767	buf = buf2;
1768	size = buf2_size;
1769	}
1770
1771	DPRINTF("+++ transmit loopback mode\n");
1772	qemu_receive_packet(qemu_get_queue(s->nic), buf, size);
1773
1774	if (iov) {
1775	g_free(buf2);
1776	}
1777	}
1778	else
1779	{
1780	if (iov) {
1781	qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
1782	} else {
1783	qemu_send_packet(qemu_get_queue(s->nic), buf, size);
1784	}
1785	}
1786	}
1787
1788	static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1789	{
1790	if (!rtl8139_transmitter_enabled(s))
1791	{
1792	DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1793	"disabled\n", descriptor);
1794	return 0;
1795	}
1796
1797	if (s->TxStatus[descriptor] & TxHostOwns)
1798	{
1799	DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1800	"(%08x)\n", descriptor, s->TxStatus[descriptor]);
1801	return 0;
1802	}
1803
1804	DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1805
1806	PCIDevice *d = PCI_DEVICE(s);
1807	int txsize = s->TxStatus[descriptor] & 0x1fff;
1808	QEMU_UNINITIALIZED uint8_t txbuffer[0x2000];
1809
1810	DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1811	txsize, s->TxAddr[descriptor]);
1812
1813	pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1814
1815	/* Mark descriptor as transferred */
1816	s->TxStatus[descriptor] \|= TxHostOwns;
1817	s->TxStatus[descriptor] \|= TxStatOK;
1818
1819	rtl8139_transfer_frame(s, txbuffer, txsize, NULL);
1820
1821	DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1822	descriptor);
1823
1824	/* update interrupt */
1825	s->IntrStatus \|= TxOK;
1826	rtl8139_update_irq(s);
1827
1828	return 1;
1829	}
1830
1831	#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1832
1833	/* produces ones' complement sum of data */
1834	static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1835	{
1836	uint32_t result = 0;
1837
1838	for (; len > 1; data+=2, len-=2)
1839	{
1840	result += (uint16_t)data;
1841	}
1842
1843	/* add the remainder byte */
1844	if (len)
1845	{
1846	uint8_t odd[2] = {*data, 0};
1847	result += (uint16_t)odd;
1848	}
1849
1850	while (result>>16)
1851	result = (result & 0xffff) + (result >> 16);
1852
1853	return result;
1854	}
1855
1856	static uint16_t ip_checksum(void *data, size_t len)
1857	{
1858	return ~ones_complement_sum((uint8_t*)data, len);
1859	}
1860
1861	static int rtl8139_cplus_transmit_one(RTL8139State *s)
1862	{
1863	if (!rtl8139_transmitter_enabled(s))
1864	{
1865	DPRINTF("+++ C+ mode: transmitter disabled\n");
1866	return 0;
1867	}
1868
1869	if (!rtl8139_cp_transmitter_enabled(s))
1870	{
1871	DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1872	return 0 ;
1873	}
1874
1875	PCIDevice *d = PCI_DEVICE(s);
1876	int descriptor = s->currCPlusTxDesc;
1877
1878	dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1879
1880	/* Normal priority ring */
1881	cplus_tx_ring_desc += 16 * descriptor;
1882
1883	DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1884	"%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1885	s->TxAddr[0], cplus_tx_ring_desc);
1886
1887	uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1888
1889	pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1890	txdw0 = le32_to_cpu(val);
1891	pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1892	txdw1 = le32_to_cpu(val);
1893	pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1894	txbufLO = le32_to_cpu(val);
1895	pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1896	txbufHI = le32_to_cpu(val);
1897
1898	DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1899	txdw0, txdw1, txbufLO, txbufHI);
1900
1901	/* w0 ownership flag */
1902	#define CP_TX_OWN (1<<31)
1903	/* w0 end of ring flag */
1904	#define CP_TX_EOR (1<<30)
1905	/* first segment of received packet flag */
1906	#define CP_TX_FS (1<<29)
1907	/* last segment of received packet flag */
1908	#define CP_TX_LS (1<<28)
1909	/* large send packet flag */
1910	#define CP_TX_LGSEN (1<<27)
1911	/* large send MSS mask, bits 16...26 */
1912	#define CP_TC_LGSEN_MSS_SHIFT 16
1913	#define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1)
1914
1915	/* IP checksum offload flag */
1916	#define CP_TX_IPCS (1<<18)
1917	/* UDP checksum offload flag */
1918	#define CP_TX_UDPCS (1<<17)
1919	/* TCP checksum offload flag */
1920	#define CP_TX_TCPCS (1<<16)
1921
1922	/* w0 bits 0...15 : buffer size */
1923	#define CP_TX_BUFFER_SIZE (1<<16)
1924	#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1925	/* w1 add tag flag */
1926	#define CP_TX_TAGC (1<<17)
1927	/* w1 bits 0...15 : VLAN tag (big endian) */
1928	#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1929	/* w2 low 32bit of Rx buffer ptr */
1930	/* w3 high 32bit of Rx buffer ptr */
1931
1932	/* set after transmission */
1933	/* FIFO underrun flag */
1934	#define CP_TX_STATUS_UNF (1<<25)
1935	/* transmit error summary flag, valid if set any of three below */
1936	#define CP_TX_STATUS_TES (1<<23)
1937	/* out-of-window collision flag */
1938	#define CP_TX_STATUS_OWC (1<<22)
1939	/* link failure flag */
1940	#define CP_TX_STATUS_LNKF (1<<21)
1941	/* excessive collisions flag */
1942	#define CP_TX_STATUS_EXC (1<<20)
1943
1944	if (!(txdw0 & CP_TX_OWN))
1945	{
1946	DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
1947	return 0 ;
1948	}
1949
1950	DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
1951
1952	if (txdw0 & CP_TX_FS)
1953	{
1954	DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1955	"descriptor\n", descriptor);
1956
1957	/* reset internal buffer offset */
1958	s->cplus_txbuffer_offset = 0;
1959	}
1960
1961	int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1962	dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1963
1964	/* make sure we have enough space to assemble the packet */
1965	if (!s->cplus_txbuffer)
1966	{
1967	s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1968	s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
1969	s->cplus_txbuffer_offset = 0;
1970
1971	DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
1972	s->cplus_txbuffer_len);
1973	}
1974
1975	if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1976	{
1977	/* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
1978	txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
1979	DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
1980	"length to %d\n", txsize);
1981	}
1982
1983	/* append more data to the packet */
1984
1985	DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
1986	DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
1987	s->cplus_txbuffer_offset);
1988
1989	pci_dma_read(d, tx_addr,
1990	s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
1991	s->cplus_txbuffer_offset += txsize;
1992
1993	/* seek to next Rx descriptor */
1994	if (txdw0 & CP_TX_EOR)
1995	{
1996	s->currCPlusTxDesc = 0;
1997	}
1998	else
1999	{
2000	++s->currCPlusTxDesc;
2001	if (s->currCPlusTxDesc >= 64)
2002	s->currCPlusTxDesc = 0;
2003	}
2004
2005	/* Build the Tx Status Descriptor */
2006	uint32_t tx_status = txdw0;
2007
2008	/* transfer ownership to target */
2009	tx_status &= ~CP_TX_OWN;
2010
2011	/* reset error indicator bits */
2012	tx_status &= ~CP_TX_STATUS_UNF;
2013	tx_status &= ~CP_TX_STATUS_TES;
2014	tx_status &= ~CP_TX_STATUS_OWC;
2015	tx_status &= ~CP_TX_STATUS_LNKF;
2016	tx_status &= ~CP_TX_STATUS_EXC;
2017
2018	/* update ring data */
2019	val = cpu_to_le32(tx_status);
2020	pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2021
2022	/* Now decide if descriptor being processed is holding the last segment of packet */
2023	if (txdw0 & CP_TX_LS)
2024	{
2025	uint8_t dot1q_buffer_space[VLAN_HLEN];
2026	uint16_t *dot1q_buffer;
2027
2028	DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2029	descriptor);
2030
2031	/* can transfer fully assembled packet */
2032
2033	uint8_t *saved_buffer = s->cplus_txbuffer;
2034	int saved_size = s->cplus_txbuffer_offset;
2035	int saved_buffer_len = s->cplus_txbuffer_len;
2036
2037	/* create vlan tag */
2038	if (txdw1 & CP_TX_TAGC) {
2039	/* the vlan tag is in BE byte order in the descriptor
2040	* BE + le_to_cpu() + ~swap()~ = cpu */
2041	DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2042	bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2043
2044	dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2045	dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN);
2046	/* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2047	dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2048	} else {
2049	dot1q_buffer = NULL;
2050	}
2051
2052	/* reset the card space to protect from recursive call */
2053	s->cplus_txbuffer = NULL;
2054	s->cplus_txbuffer_offset = 0;
2055	s->cplus_txbuffer_len = 0;
2056
2057	if (txdw0 & (CP_TX_IPCS \| CP_TX_UDPCS \| CP_TX_TCPCS \| CP_TX_LGSEN))
2058	{
2059	DPRINTF("+++ C+ mode offloaded task checksum\n");
2060
2061	/* Large enough for Ethernet and IP headers? */
2062	if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
2063	goto skip_offload;
2064	}
2065
2066	/* ip packet header */
2067	struct ip_header *ip = NULL;
2068	int hlen = 0;
2069	uint8_t ip_protocol = 0;
2070	uint16_t ip_data_len = 0;
2071
2072	uint8_t *eth_payload_data = NULL;
2073	size_t eth_payload_len = 0;
2074
2075	int proto = be16_to_cpu((uint16_t )(saved_buffer + 12));
2076	if (proto != ETH_P_IP)
2077	{
2078	goto skip_offload;
2079	}
2080
2081	DPRINTF("+++ C+ mode has IP packet\n");
2082
2083	/* Note on memory alignment: eth_payload_data is 16-bit aligned
2084	* since saved_buffer is allocated with g_malloc() and ETH_HLEN is
2085	* even. 32-bit accesses must use ldl/stl wrappers to avoid
2086	* unaligned accesses.
2087	*/
2088	eth_payload_data = saved_buffer + ETH_HLEN;
2089	eth_payload_len = saved_size - ETH_HLEN;
2090
2091	ip = (struct ip_header*)eth_payload_data;
2092
2093	if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2094	DPRINTF("+++ C+ mode packet has bad IP version %d "
2095	"expected %d\n", IP_HEADER_VERSION(ip),
2096	IP_HEADER_VERSION_4);
2097	goto skip_offload;
2098	}
2099
2100	hlen = IP_HDR_GET_LEN(ip);
2101	if (hlen < sizeof(struct ip_header) \|\| hlen > eth_payload_len) {
2102	goto skip_offload;
2103	}
2104
2105	ip_protocol = ip->ip_p;
2106
2107	ip_data_len = be16_to_cpu(ip->ip_len);
2108	if (ip_data_len < hlen \|\| ip_data_len > eth_payload_len) {
2109	goto skip_offload;
2110	}
2111	ip_data_len -= hlen;
2112
2113	if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & CP_TX_IPCS))
2114	{
2115	DPRINTF("+++ C+ mode need IP checksum\n");
2116
2117	ip->ip_sum = 0;
2118	ip->ip_sum = ip_checksum(ip, hlen);
2119	DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2120	hlen, ip->ip_sum);
2121	}
2122
2123	/*
2124	* The code in this function triggers a GCC bug where an
2125	* interaction between -fsanitize=address and -Wstringop-overflow
2126	* results in a false-positive stringop-overflow warning that is
2127	* only emitted when the address sanitizer is enabled:
2128	* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114494
2129	* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99673
2130	* GCC incorrectly thinks that the eth_payload_data buffer has
2131	* the type and size of the first field in 'struct ip_header', i.e.
2132	* one byte, and then complains about all other attempts to access
2133	* data in the buffer.
2134	*
2135	* Work around this by disabling the warning when building with
2136	* GCC and the address sanitizer is enabled.
2137	*/
2138	#pragma GCC diagnostic push
2139	#if !defined(__clang__) && defined(QEMU_SANITIZE_ADDRESS)
2140	#pragma GCC diagnostic ignored "-Wstringop-overflow"
2141	#endif
2142
2143	if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2144	{
2145	/* Large enough for the TCP header? */
2146	if (ip_data_len < sizeof(tcp_header)) {
2147	goto skip_offload;
2148	}
2149
2150	int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) &
2151	CP_TC_LGSEN_MSS_MASK;
2152	if (large_send_mss == 0) {
2153	goto skip_offload;
2154	}
2155
2156	DPRINTF("+++ C+ mode offloaded task TSO IP data %d "
2157	"frame data %d specified MSS=%d\n",
2158	ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2159
2160	int tcp_send_offset = 0;
2161
2162	/* maximum IP header length is 60 bytes */
2163	uint8_t saved_ip_header[60];
2164
2165	/* save IP header template; data area is used in tcp checksum calculation */
2166	memcpy(saved_ip_header, eth_payload_data, hlen);
2167
2168	/* a placeholder for checksum calculation routine in tcp case */
2169	uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2170	// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2171
2172	/* pointer to TCP header */
2173	tcp_header p_tcp_hdr = (tcp_header)(eth_payload_data + hlen);
2174
2175	int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2176
2177	/* Invalid TCP data offset? */
2178	if (tcp_hlen < sizeof(tcp_header) \|\| tcp_hlen > ip_data_len) {
2179	goto skip_offload;
2180	}
2181
2182	int tcp_data_len = ip_data_len - tcp_hlen;
2183
2184	DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2185	"data len %d\n", ip_data_len, tcp_hlen, tcp_data_len);
2186
2187	/* note the cycle below overwrites IP header data,
2188	but restores it from saved_ip_header before sending packet */
2189
2190	int is_last_frame = 0;
2191
2192	for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += large_send_mss)
2193	{
2194	uint16_t chunk_size = large_send_mss;
2195
2196	/* check if this is the last frame */
2197	if (tcp_send_offset + large_send_mss >= tcp_data_len)
2198	{
2199	is_last_frame = 1;
2200	chunk_size = tcp_data_len - tcp_send_offset;
2201	}
2202
2203	DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2204	ldl_be_p(&p_tcp_hdr->th_seq));
2205
2206	/* add 4 TCP pseudoheader fields */
2207	/* copy IP source and destination fields */
2208	memcpy(data_to_checksum, saved_ip_header + 12, 8);
2209
2210	DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2211	"packet with %d bytes data\n", tcp_hlen +
2212	chunk_size);
2213
2214	if (tcp_send_offset)
2215	{
2216	memcpy((uint8_t)p_tcp_hdr + tcp_hlen, (uint8_t)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2217	}
2218
2219	/* keep PUSH and FIN flags only for the last frame */
2220	if (!is_last_frame)
2221	{
2222	TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH \| TH_FIN);
2223	}
2224
2225	/* recalculate TCP checksum */
2226	ip_pseudo_header p_tcpip_hdr = (ip_pseudo_header )data_to_checksum;
2227	p_tcpip_hdr->zeros = 0;
2228	p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2229	p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2230
2231	p_tcp_hdr->th_sum = 0;
2232
2233	int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2234	DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2235	tcp_checksum);
2236
2237	p_tcp_hdr->th_sum = tcp_checksum;
2238
2239	/* restore IP header */
2240	memcpy(eth_payload_data, saved_ip_header, hlen);
2241
2242	/* set IP data length and recalculate IP checksum */
2243	ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2244
2245	/* increment IP id for subsequent frames */
2246	ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id));
2247
2248	ip->ip_sum = 0;
2249	ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2250	DPRINTF("+++ C+ mode TSO IP header len=%d "
2251	"checksum=%04x\n", hlen, ip->ip_sum);
2252
2253	int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2254	DPRINTF("+++ C+ mode TSO transferring packet size "
2255	"%d\n", tso_send_size);
2256	rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2257	(uint8_t *)dot1q_buffer);
2258
2259	/* add transferred count to TCP sequence number */
2260	stl_be_p(&p_tcp_hdr->th_seq,
2261	chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
2262	}
2263
2264	/* Stop sending this frame */
2265	saved_size = 0;
2266	}
2267	else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS\|CP_TX_UDPCS)))
2268	{
2269	DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2270
2271	/* maximum IP header length is 60 bytes */
2272	uint8_t saved_ip_header[60];
2273	memcpy(saved_ip_header, eth_payload_data, hlen);
2274
2275	uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2276	// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2277
2278	/* add 4 TCP pseudoheader fields */
2279	/* copy IP source and destination fields */
2280	memcpy(data_to_checksum, saved_ip_header + 12, 8);
2281
2282	if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2283	{
2284	DPRINTF("+++ C+ mode calculating TCP checksum for "
2285	"packet with %d bytes data\n", ip_data_len);
2286
2287	ip_pseudo_header p_tcpip_hdr = (ip_pseudo_header )data_to_checksum;
2288	p_tcpip_hdr->zeros = 0;
2289	p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2290	p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2291
2292	tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2293
2294	p_tcp_hdr->th_sum = 0;
2295
2296	int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2297	DPRINTF("+++ C+ mode TCP checksum %04x\n",
2298	tcp_checksum);
2299
2300	p_tcp_hdr->th_sum = tcp_checksum;
2301	}
2302	else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2303	{
2304	DPRINTF("+++ C+ mode calculating UDP checksum for "
2305	"packet with %d bytes data\n", ip_data_len);
2306
2307	ip_pseudo_header p_udpip_hdr = (ip_pseudo_header )data_to_checksum;
2308	p_udpip_hdr->zeros = 0;
2309	p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2310	p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2311
2312	udp_header p_udp_hdr = (udp_header ) (data_to_checksum+12);
2313
2314	p_udp_hdr->uh_sum = 0;
2315
2316	int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2317	DPRINTF("+++ C+ mode UDP checksum %04x\n",
2318	udp_checksum);
2319
2320	p_udp_hdr->uh_sum = udp_checksum;
2321	}
2322
2323	/* restore IP header */
2324	memcpy(eth_payload_data, saved_ip_header, hlen);
2325	}
2326
2327	#pragma GCC diagnostic pop
2328
2329	}
2330
2331	skip_offload:
2332	/* update tally counter */
2333	++s->tally_counters.TxOk;
2334
2335	DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2336
2337	rtl8139_transfer_frame(s, saved_buffer, saved_size,
2338	(uint8_t *)dot1q_buffer);
2339
2340	/* restore card space if there was no recursion and reset offset */
2341	if (!s->cplus_txbuffer)
2342	{
2343	s->cplus_txbuffer = saved_buffer;
2344	s->cplus_txbuffer_len = saved_buffer_len;
2345	s->cplus_txbuffer_offset = 0;
2346	}
2347	else
2348	{
2349	g_free(saved_buffer);
2350	}
2351	}
2352	else
2353	{
2354	DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2355	}
2356
2357	return 1;
2358	}
2359
2360	static void rtl8139_cplus_transmit(RTL8139State *s)
2361	{
2362	int txcount = 0;
2363
2364	while (txcount < 64 && rtl8139_cplus_transmit_one(s))
2365	{
2366	++txcount;
2367	}
2368
2369	/* Mark transfer completed */
2370	if (!txcount)
2371	{
2372	DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2373	s->currCPlusTxDesc);
2374	}
2375	else
2376	{
2377	/* update interrupt status */
2378	s->IntrStatus \|= TxOK;
2379	rtl8139_update_irq(s);
2380	}
2381	}
2382
2383	static void rtl8139_transmit(RTL8139State *s)
2384	{
2385	int descriptor = s->currTxDesc, txcount = 0;
2386
2387	/while/
2388	if (rtl8139_transmit_one(s, descriptor))
2389	{
2390	++s->currTxDesc;
2391	s->currTxDesc %= 4;
2392	++txcount;
2393	}
2394
2395	/* Mark transfer completed */
2396	if (!txcount)
2397	{
2398	DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2399	s->currTxDesc);
2400	}
2401	}
2402
2403	static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2404	{
2405
2406	int descriptor = txRegOffset/4;
2407
2408	/* handle C+ transmit mode register configuration */
2409
2410	if (s->cplus_enabled)
2411	{
2412	DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2413	"descriptor=%d\n", txRegOffset, val, descriptor);
2414
2415	/* handle Dump Tally Counters command */
2416	s->TxStatus[descriptor] = val;
2417
2418	if (descriptor == 0 && (val & 0x8))
2419	{
2420	hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2421
2422	/* dump tally counters to specified memory location */
2423	RTL8139TallyCounters_dma_write(s, tc_addr);
2424
2425	/* mark dump completed */
2426	s->TxStatus[0] &= ~0x8;
2427	}
2428
2429	return;
2430	}
2431
2432	DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2433	txRegOffset, val, descriptor);
2434
2435	/* mask only reserved bits */
2436	val &= ~0xff00c000; /* these bits are reset on write */
2437	val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2438
2439	s->TxStatus[descriptor] = val;
2440
2441	/* attempt to start transmission */
2442	rtl8139_transmit(s);
2443	}
2444
2445	static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2446	uint32_t base, uint8_t addr,
2447	int size)
2448	{
2449	uint32_t reg = (addr - base) / 4;
2450	uint32_t offset = addr & 0x3;
2451	uint32_t ret = 0;
2452
2453	if (addr & (size - 1)) {
2454	DPRINTF("not implemented read for TxStatus/TxAddr "
2455	"addr=0x%x size=0x%x\n", addr, size);
2456	return ret;
2457	}
2458
2459	switch (size) {
2460	case 1: /* fall through */
2461	case 2: /* fall through */
2462	case 4:
2463	ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2464	DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2465	reg, addr, size, ret);
2466	break;
2467	default:
2468	DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2469	break;
2470	}
2471
2472	return ret;
2473	}
2474
2475	static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2476	{
2477	uint16_t ret = 0;
2478
2479	/* Simulate TSAD, it is read only anyway */
2480
2481	ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2482	\|((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2483	\|((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2484	\|((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2485
2486	\|((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2487	\|((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2488	\|((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2489	\|((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2490
2491	\|((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2492	\|((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2493	\|((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2494	\|((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2495
2496	\|((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2497	\|((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2498	\|((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2499	\|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2500
2501
2502	DPRINTF("TSAD read val=0x%04x\n", ret);
2503
2504	return ret;
2505	}
2506
2507	static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2508	{
2509	uint16_t ret = s->CSCR;
2510
2511	DPRINTF("CSCR read val=0x%04x\n", ret);
2512
2513	return ret;
2514	}
2515
2516	static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2517	{
2518	DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2519
2520	s->TxAddr[txAddrOffset/4] = val;
2521	}
2522
2523	static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2524	{
2525	uint32_t ret = s->TxAddr[txAddrOffset/4];
2526
2527	DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2528
2529	return ret;
2530	}
2531
2532	static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2533	{
2534	DPRINTF("RxBufPtr write val=0x%04x\n", val);
2535
2536	/* this value is off by 16 */
2537	s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2538
2539	/* more buffer space may be available so try to receive */
2540	qemu_flush_queued_packets(qemu_get_queue(s->nic));
2541
2542	DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2543	s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2544	}
2545
2546	static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2547	{
2548	/* this value is off by 16 */
2549	uint32_t ret = s->RxBufPtr - 0x10;
2550
2551	DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2552
2553	return ret;
2554	}
2555
2556	static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2557	{
2558	/* this value is NOT off by 16 */
2559	uint32_t ret = s->RxBufAddr;
2560
2561	DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2562
2563	return ret;
2564	}
2565
2566	static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2567	{
2568	DPRINTF("RxBuf write val=0x%08x\n", val);
2569
2570	s->RxBuf = val;
2571
2572	/* may need to reset rxring here */
2573	}
2574
2575	static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2576	{
2577	uint32_t ret = s->RxBuf;
2578
2579	DPRINTF("RxBuf read val=0x%08x\n", ret);
2580
2581	return ret;
2582	}
2583
2584	static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2585	{
2586	DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2587
2588	/* mask unwritable bits */
2589	val = SET_MASKED(val, 0x1e00, s->IntrMask);
2590
2591	s->IntrMask = val;
2592
2593	rtl8139_update_irq(s);
2594
2595	}
2596
2597	static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2598	{
2599	uint32_t ret = s->IntrMask;
2600
2601	DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2602
2603	return ret;
2604	}
2605
2606	static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2607	{
2608	DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2609
2610	#if 0
2611
2612	/* writing to ISR has no effect */
2613
2614	return;
2615
2616	#else
2617	uint16_t newStatus = s->IntrStatus & ~val;
2618
2619	/* mask unwritable bits */
2620	newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2621
2622	/* writing 1 to interrupt status register bit clears it */
2623	s->IntrStatus = 0;
2624	rtl8139_update_irq(s);
2625
2626	s->IntrStatus = newStatus;
2627	rtl8139_set_next_tctr_time(s);
2628	rtl8139_update_irq(s);
2629
2630	#endif
2631	}
2632
2633	static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2634	{
2635	uint32_t ret = s->IntrStatus;
2636
2637	DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2638
2639	#if 0
2640
2641	/* reading ISR clears all interrupts */
2642	s->IntrStatus = 0;
2643
2644	rtl8139_update_irq(s);
2645
2646	#endif
2647
2648	return ret;
2649	}
2650
2651	static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2652	{
2653	DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2654
2655	/* mask unwritable bits */
2656	val = SET_MASKED(val, 0xf000, s->MultiIntr);
2657
2658	s->MultiIntr = val;
2659	}
2660
2661	static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2662	{
2663	uint32_t ret = s->MultiIntr;
2664
2665	DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2666
2667	return ret;
2668	}
2669
2670	static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2671	{
2672	RTL8139State *s = opaque;
2673
2674	switch (addr)
2675	{
2676	case MAC0 ... MAC0+4:
2677	s->phys[addr - MAC0] = val;
2678	break;
2679	case MAC0+5:
2680	s->phys[addr - MAC0] = val;
2681	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2682	break;
2683	case MAC0+6 ... MAC0+7:
2684	/* reserved */
2685	break;
2686	case MAR0 ... MAR0+7:
2687	s->mult[addr - MAR0] = val;
2688	break;
2689	case ChipCmd:
2690	rtl8139_ChipCmd_write(s, val);
2691	break;
2692	case Cfg9346:
2693	rtl8139_Cfg9346_write(s, val);
2694	break;
2695	case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2696	rtl8139_TxConfig_writeb(s, val);
2697	break;
2698	case Config0:
2699	rtl8139_Config0_write(s, val);
2700	break;
2701	case Config1:
2702	rtl8139_Config1_write(s, val);
2703	break;
2704	case Config3:
2705	rtl8139_Config3_write(s, val);
2706	break;
2707	case Config4:
2708	rtl8139_Config4_write(s, val);
2709	break;
2710	case Config5:
2711	rtl8139_Config5_write(s, val);
2712	break;
2713	case MediaStatus:
2714	/* ignore */
2715	DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2716	val);
2717	break;
2718
2719	case HltClk:
2720	DPRINTF("HltClk write val=0x%08x\n", val);
2721	if (val == 'R')
2722	{
2723	s->clock_enabled = 1;
2724	}
2725	else if (val == 'H')
2726	{
2727	s->clock_enabled = 0;
2728	}
2729	break;
2730
2731	case TxThresh:
2732	DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2733	s->TxThresh = val;
2734	break;
2735
2736	case TxPoll:
2737	DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2738	if (val & (1 << 7))
2739	{
2740	DPRINTF("C+ TxPoll high priority transmission (not "
2741	"implemented)\n");
2742	//rtl8139_cplus_transmit(s);
2743	}
2744	if (val & (1 << 6))
2745	{
2746	DPRINTF("C+ TxPoll normal priority transmission\n");
2747	rtl8139_cplus_transmit(s);
2748	}
2749
2750	break;
2751	case RxConfig:
2752	DPRINTF("RxConfig write(b) val=0x%02x\n", val);
2753	rtl8139_RxConfig_write(s,
2754	(rtl8139_RxConfig_read(s) & 0xFFFFFF00) \| val);
2755	break;
2756	default:
2757	DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2758	val);
2759	break;
2760	}
2761	}
2762
2763	static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2764	{
2765	RTL8139State *s = opaque;
2766
2767	switch (addr)
2768	{
2769	case IntrMask:
2770	rtl8139_IntrMask_write(s, val);
2771	break;
2772
2773	case IntrStatus:
2774	rtl8139_IntrStatus_write(s, val);
2775	break;
2776
2777	case MultiIntr:
2778	rtl8139_MultiIntr_write(s, val);
2779	break;
2780
2781	case RxBufPtr:
2782	rtl8139_RxBufPtr_write(s, val);
2783	break;
2784
2785	case BasicModeCtrl:
2786	rtl8139_BasicModeCtrl_write(s, val);
2787	break;
2788	case BasicModeStatus:
2789	rtl8139_BasicModeStatus_write(s, val);
2790	break;
2791	case NWayAdvert:
2792	DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2793	s->NWayAdvert = val;
2794	break;
2795	case NWayLPAR:
2796	DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2797	break;
2798	case NWayExpansion:
2799	DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2800	s->NWayExpansion = val;
2801	break;
2802
2803	case CpCmd:
2804	rtl8139_CpCmd_write(s, val);
2805	break;
2806
2807	case IntrMitigate:
2808	rtl8139_IntrMitigate_write(s, val);
2809	break;
2810
2811	default:
2812	DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2813	addr, val);
2814
2815	rtl8139_io_writeb(opaque, addr, val & 0xff);
2816	rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2817	break;
2818	}
2819	}
2820
2821	static void rtl8139_set_next_tctr_time(RTL8139State *s)
2822	{
2823	const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32;
2824
2825	DPRINTF("entered rtl8139_set_next_tctr_time\n");
2826
2827	/* This function is called at least once per period, so it is a good
2828	* place to update the timer base.
2829	*
2830	* After one iteration of this loop the value in the Timer register does
2831	* not change, but the device model is counting up by 2^32 ticks (approx.
2832	* 130 seconds).
2833	*/
2834	while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2835	s->TCTR_base += ns_per_period;
2836	}
2837
2838	if (!s->TimerInt) {
2839	timer_del(s->timer);
2840	} else {
2841	uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD;
2842	if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2843	delta += ns_per_period;
2844	}
2845	timer_mod(s->timer, s->TCTR_base + delta);
2846	}
2847	}
2848
2849	static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2850	{
2851	RTL8139State *s = opaque;
2852
2853	switch (addr)
2854	{
2855	case RxMissed:
2856	DPRINTF("RxMissed clearing on write\n");
2857	s->RxMissed = 0;
2858	break;
2859
2860	case TxConfig:
2861	rtl8139_TxConfig_write(s, val);
2862	break;
2863
2864	case RxConfig:
2865	rtl8139_RxConfig_write(s, val);
2866	break;
2867
2868	case TxStatus0 ... TxStatus0+4*4-1:
2869	rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2870	break;
2871
2872	case TxAddr0 ... TxAddr0+4*4-1:
2873	rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2874	break;
2875
2876	case RxBuf:
2877	rtl8139_RxBuf_write(s, val);
2878	break;
2879
2880	case RxRingAddrLO:
2881	DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2882	s->RxRingAddrLO = val;
2883	break;
2884
2885	case RxRingAddrHI:
2886	DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2887	s->RxRingAddrHI = val;
2888	break;
2889
2890	case Timer:
2891	DPRINTF("TCTR Timer reset on write\n");
2892	s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2893	rtl8139_set_next_tctr_time(s);
2894	break;
2895
2896	case FlashReg:
2897	DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2898	if (s->TimerInt != val) {
2899	s->TimerInt = val;
2900	rtl8139_set_next_tctr_time(s);
2901	}
2902	break;
2903
2904	default:
2905	DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2906	addr, val);
2907	rtl8139_io_writeb(opaque, addr, val & 0xff);
2908	rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2909	rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2910	rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2911	break;
2912	}
2913	}
2914
2915	static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2916	{
2917	RTL8139State *s = opaque;
2918	int ret;
2919
2920	switch (addr)
2921	{
2922	case MAC0 ... MAC0+5:
2923	ret = s->phys[addr - MAC0];
2924	break;
2925	case MAC0+6 ... MAC0+7:
2926	ret = 0;
2927	break;
2928	case MAR0 ... MAR0+7:
2929	ret = s->mult[addr - MAR0];
2930	break;
2931	case TxStatus0 ... TxStatus0+4*4-1:
2932	ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2933	addr, 1);
2934	break;
2935	case ChipCmd:
2936	ret = rtl8139_ChipCmd_read(s);
2937	break;
2938	case Cfg9346:
2939	ret = rtl8139_Cfg9346_read(s);
2940	break;
2941	case Config0:
2942	ret = rtl8139_Config0_read(s);
2943	break;
2944	case Config1:
2945	ret = rtl8139_Config1_read(s);
2946	break;
2947	case Config3:
2948	ret = rtl8139_Config3_read(s);
2949	break;
2950	case Config4:
2951	ret = rtl8139_Config4_read(s);
2952	break;
2953	case Config5:
2954	ret = rtl8139_Config5_read(s);
2955	break;
2956
2957	case MediaStatus:
2958	/* The LinkDown bit of MediaStatus is inverse with link status */
2959	ret = 0xd0 \| (~s->BasicModeStatus & 0x04);
2960	DPRINTF("MediaStatus read 0x%x\n", ret);
2961	break;
2962
2963	case HltClk:
2964	ret = s->clock_enabled;
2965	DPRINTF("HltClk read 0x%x\n", ret);
2966	break;
2967
2968	case PCIRevisionID:
2969	ret = RTL8139_PCI_REVID;
2970	DPRINTF("PCI Revision ID read 0x%x\n", ret);
2971	break;
2972
2973	case TxThresh:
2974	ret = s->TxThresh;
2975	DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
2976	break;
2977
2978	case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2979	ret = s->TxConfig >> 24;
2980	DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
2981	break;
2982
2983	default:
2984	DPRINTF("not implemented read(b) addr=0x%x\n", addr);
2985	ret = 0;
2986	break;
2987	}
2988
2989	return ret;
2990	}
2991
2992	static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2993	{
2994	RTL8139State *s = opaque;
2995	uint32_t ret;
2996
2997	switch (addr)
2998	{
2999	case TxAddr0 ... TxAddr0+4*4-1:
3000	ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
3001	break;
3002	case IntrMask:
3003	ret = rtl8139_IntrMask_read(s);
3004	break;
3005
3006	case IntrStatus:
3007	ret = rtl8139_IntrStatus_read(s);
3008	break;
3009
3010	case MultiIntr:
3011	ret = rtl8139_MultiIntr_read(s);
3012	break;
3013
3014	case RxBufPtr:
3015	ret = rtl8139_RxBufPtr_read(s);
3016	break;
3017
3018	case RxBufAddr:
3019	ret = rtl8139_RxBufAddr_read(s);
3020	break;
3021
3022	case BasicModeCtrl:
3023	ret = rtl8139_BasicModeCtrl_read(s);
3024	break;
3025	case BasicModeStatus:
3026	ret = rtl8139_BasicModeStatus_read(s);
3027	break;
3028	case NWayAdvert:
3029	ret = s->NWayAdvert;
3030	DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3031	break;
3032	case NWayLPAR:
3033	ret = s->NWayLPAR;
3034	DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3035	break;
3036	case NWayExpansion:
3037	ret = s->NWayExpansion;
3038	DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3039	break;
3040
3041	case CpCmd:
3042	ret = rtl8139_CpCmd_read(s);
3043	break;
3044
3045	case IntrMitigate:
3046	ret = rtl8139_IntrMitigate_read(s);
3047	break;
3048
3049	case TxSummary:
3050	ret = rtl8139_TSAD_read(s);
3051	break;
3052
3053	case CSCR:
3054	ret = rtl8139_CSCR_read(s);
3055	break;
3056
3057	default:
3058	DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3059
3060	ret = rtl8139_io_readb(opaque, addr);
3061	ret \|= rtl8139_io_readb(opaque, addr + 1) << 8;
3062
3063	DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3064	break;
3065	}
3066
3067	return ret;
3068	}
3069
3070	static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3071	{
3072	RTL8139State *s = opaque;
3073	uint32_t ret;
3074
3075	switch (addr)
3076	{
3077	case RxMissed:
3078	ret = s->RxMissed;
3079
3080	DPRINTF("RxMissed read val=0x%08x\n", ret);
3081	break;
3082
3083	case TxConfig:
3084	ret = rtl8139_TxConfig_read(s);
3085	break;
3086
3087	case RxConfig:
3088	ret = rtl8139_RxConfig_read(s);
3089	break;
3090
3091	case TxStatus0 ... TxStatus0+4*4-1:
3092	ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3093	addr, 4);
3094	break;
3095
3096	case TxAddr0 ... TxAddr0+4*4-1:
3097	ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3098	break;
3099
3100	case RxBuf:
3101	ret = rtl8139_RxBuf_read(s);
3102	break;
3103
3104	case RxRingAddrLO:
3105	ret = s->RxRingAddrLO;
3106	DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3107	break;
3108
3109	case RxRingAddrHI:
3110	ret = s->RxRingAddrHI;
3111	DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3112	break;
3113
3114	case Timer:
3115	ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
3116	PCI_PERIOD;
3117	DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3118	break;
3119
3120	case FlashReg:
3121	ret = s->TimerInt;
3122	DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3123	break;
3124
3125	default:
3126	DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3127
3128	ret = rtl8139_io_readb(opaque, addr);
3129	ret \|= rtl8139_io_readb(opaque, addr + 1) << 8;
3130	ret \|= rtl8139_io_readb(opaque, addr + 2) << 16;
3131	ret \|= rtl8139_io_readb(opaque, addr + 3) << 24;
3132
3133	DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3134	break;
3135	}
3136
3137	return ret;
3138	}
3139
3140	/* */
3141
3142	static int rtl8139_post_load(void *opaque, int version_id)
3143	{
3144	RTL8139State* s = opaque;
3145	rtl8139_set_next_tctr_time(s);
3146	if (version_id < 4) {
3147	s->cplus_enabled = s->CpCmd != 0;
3148	}
3149
3150	/* nc.link_down can't be migrated, so infer link_down according
3151	* to link status bit in BasicModeStatus */
3152	qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
3153
3154	return 0;
3155	}
3156
3157	static bool rtl8139_hotplug_ready_needed(void *opaque)
3158	{
3159	return qdev_machine_modified();
3160	}
3161
3162	static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3163	.name = "rtl8139/hotplug_ready",
3164	.version_id = 1,
3165	.minimum_version_id = 1,
3166	.needed = rtl8139_hotplug_ready_needed,
3167	.fields = (const VMStateField[]) {
3168	VMSTATE_END_OF_LIST()
3169	}
3170	};
3171
3172	static int rtl8139_pre_save(void *opaque)
3173	{
3174	RTL8139State* s = opaque;
3175	int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3176
3177	/* for migration to older versions */
3178	s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD;
3179	s->rtl8139_mmio_io_addr_dummy = 0;
3180
3181	return 0;
3182	}
3183
3184	static const VMStateDescription vmstate_rtl8139 = {
3185	.name = "rtl8139",
3186	.version_id = 5,
3187	.minimum_version_id = 3,
3188	.post_load = rtl8139_post_load,
3189	.pre_save = rtl8139_pre_save,
3190	.fields = (const VMStateField[]) {
3191	VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3192	VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3193	VMSTATE_BUFFER(mult, RTL8139State),
3194	VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3195	VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3196
3197	VMSTATE_UINT32(RxBuf, RTL8139State),
3198	VMSTATE_UINT32(RxBufferSize, RTL8139State),
3199	VMSTATE_UINT32(RxBufPtr, RTL8139State),
3200	VMSTATE_UINT32(RxBufAddr, RTL8139State),
3201
3202	VMSTATE_UINT16(IntrStatus, RTL8139State),
3203	VMSTATE_UINT16(IntrMask, RTL8139State),
3204
3205	VMSTATE_UINT32(TxConfig, RTL8139State),
3206	VMSTATE_UINT32(RxConfig, RTL8139State),
3207	VMSTATE_UINT32(RxMissed, RTL8139State),
3208	VMSTATE_UINT16(CSCR, RTL8139State),
3209
3210	VMSTATE_UINT8(Cfg9346, RTL8139State),
3211	VMSTATE_UINT8(Config0, RTL8139State),
3212	VMSTATE_UINT8(Config1, RTL8139State),
3213	VMSTATE_UINT8(Config3, RTL8139State),
3214	VMSTATE_UINT8(Config4, RTL8139State),
3215	VMSTATE_UINT8(Config5, RTL8139State),
3216
3217	VMSTATE_UINT8(clock_enabled, RTL8139State),
3218	VMSTATE_UINT8(bChipCmdState, RTL8139State),
3219
3220	VMSTATE_UINT16(MultiIntr, RTL8139State),
3221
3222	VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3223	VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3224	VMSTATE_UINT16(NWayAdvert, RTL8139State),
3225	VMSTATE_UINT16(NWayLPAR, RTL8139State),
3226	VMSTATE_UINT16(NWayExpansion, RTL8139State),
3227
3228	VMSTATE_UINT16(CpCmd, RTL8139State),
3229	VMSTATE_UINT8(TxThresh, RTL8139State),
3230
3231	VMSTATE_UNUSED(4),
3232	VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3233	VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3234
3235	VMSTATE_UINT32(currTxDesc, RTL8139State),
3236	VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3237	VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3238	VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3239	VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3240
3241	VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3242	VMSTATE_INT32(eeprom.mode, RTL8139State),
3243	VMSTATE_UINT32(eeprom.tick, RTL8139State),
3244	VMSTATE_UINT8(eeprom.address, RTL8139State),
3245	VMSTATE_UINT16(eeprom.input, RTL8139State),
3246	VMSTATE_UINT16(eeprom.output, RTL8139State),
3247
3248	VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3249	VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3250	VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3251	VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3252
3253	VMSTATE_UINT32(TCTR, RTL8139State),
3254	VMSTATE_UINT32(TimerInt, RTL8139State),
3255	VMSTATE_INT64(TCTR_base, RTL8139State),
3256
3257	VMSTATE_UINT64(tally_counters.TxOk, RTL8139State),
3258	VMSTATE_UINT64(tally_counters.RxOk, RTL8139State),
3259	VMSTATE_UINT64(tally_counters.TxERR, RTL8139State),
3260	VMSTATE_UINT32(tally_counters.RxERR, RTL8139State),
3261	VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State),
3262	VMSTATE_UINT16(tally_counters.FAE, RTL8139State),
3263	VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State),
3264	VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State),
3265	VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State),
3266	VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State),
3267	VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5),
3268	VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State),
3269	VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State),
3270
3271	VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3272	VMSTATE_END_OF_LIST()
3273	},
3274	.subsections = (const VMStateDescription * const []) {
3275	&vmstate_rtl8139_hotplug_ready,
3276	NULL
3277	}
3278	};
3279
3280	/***********************************************************/
3281	/* PCI RTL8139 definitions */
3282
3283	static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3284	uint64_t val, unsigned size)
3285	{
3286	switch (size) {
3287	case 1:
3288	rtl8139_io_writeb(opaque, addr, val);
3289	break;
3290	case 2:
3291	rtl8139_io_writew(opaque, addr, val);
3292	break;
3293	case 4:
3294	rtl8139_io_writel(opaque, addr, val);
3295	break;
3296	}
3297	}
3298
3299	static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3300	unsigned size)
3301	{
3302	switch (size) {
3303	case 1:
3304	return rtl8139_io_readb(opaque, addr);
3305	case 2:
3306	return rtl8139_io_readw(opaque, addr);
3307	case 4:
3308	return rtl8139_io_readl(opaque, addr);
3309	}
3310
3311	return -1;
3312	}
3313
3314	static const MemoryRegionOps rtl8139_io_ops = {
3315	.read = rtl8139_ioport_read,
3316	.write = rtl8139_ioport_write,
3317	.impl = {
3318	.min_access_size = 1,
3319	.max_access_size = 4,
3320	},
3321	.endianness = DEVICE_LITTLE_ENDIAN,
3322	};
3323
3324	static void rtl8139_timer(void *opaque)
3325	{
3326	RTL8139State *s = opaque;
3327
3328	if (!s->clock_enabled)
3329	{
3330	DPRINTF(">>> timer: clock is not running\n");
3331	return;
3332	}
3333
3334	s->IntrStatus \|= PCSTimeout;
3335	rtl8139_update_irq(s);
3336	rtl8139_set_next_tctr_time(s);
3337	}
3338
3339	static void pci_rtl8139_uninit(PCIDevice *dev)
3340	{
3341	RTL8139State *s = RTL8139(dev);
3342
3343	g_free(s->cplus_txbuffer);
3344	s->cplus_txbuffer = NULL;
3345	timer_free(s->timer);
3346	qemu_del_nic(s->nic);
3347	}
3348
3349	static void rtl8139_set_link_status(NetClientState *nc)
3350	{
3351	RTL8139State *s = qemu_get_nic_opaque(nc);
3352
3353	if (nc->link_down) {
3354	s->BasicModeStatus &= ~0x04;
3355	} else {
3356	s->BasicModeStatus \|= 0x04;
3357	}
3358
3359	s->IntrStatus \|= RxUnderrun;
3360	rtl8139_update_irq(s);
3361	}
3362
3363	static NetClientInfo net_rtl8139_info = {
3364	.type = NET_CLIENT_DRIVER_NIC,
3365	.size = sizeof(NICState),
3366	.can_receive = rtl8139_can_receive,
3367	.receive = rtl8139_receive,
3368	.link_status_changed = rtl8139_set_link_status,
3369	};
3370
3371	static void pci_rtl8139_realize(PCIDevice dev, Error *errp)
3372	{
3373	RTL8139State *s = RTL8139(dev);
3374	DeviceState *d = DEVICE(dev);
3375	uint8_t *pci_conf;
3376
3377	pci_conf = dev->config;
3378	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3379	/* TODO: start of capability list, but no capability
3380	* list bit in status register, and offset 0xdc seems unused. */
3381	pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3382
3383	memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3384	"rtl8139", 0x100);
3385	memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io,
3386	0, 0x100);
3387
3388	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3389	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3390
3391	qemu_macaddr_default_if_unset(&s->conf.macaddr);
3392
3393	/* prepare eeprom */
3394	s->eeprom.contents[0] = 0x8129;
3395	#if 1
3396	/* PCI vendor and device ID should be mirrored here */
3397	s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3398	s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3399	#endif
3400	s->eeprom.contents[7] = s->conf.macaddr.a[0] \| s->conf.macaddr.a[1] << 8;
3401	s->eeprom.contents[8] = s->conf.macaddr.a[2] \| s->conf.macaddr.a[3] << 8;
3402	s->eeprom.contents[9] = s->conf.macaddr.a[4] \| s->conf.macaddr.a[5] << 8;
3403
3404	s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3405	object_get_typename(OBJECT(dev)), d->id,
3406	&d->mem_reentrancy_guard, s);
3407	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
3408
3409	s->cplus_txbuffer = NULL;
3410	s->cplus_txbuffer_len = 0;
3411	s->cplus_txbuffer_offset = 0;
3412
3413	s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
3414	}
3415
3416	static void rtl8139_instance_init(Object *obj)
3417	{
3418	RTL8139State *s = RTL8139(obj);
3419
3420	device_add_bootindex_property(obj, &s->conf.bootindex,
3421	"bootindex", "/ethernet-phy@0",
3422	DEVICE(obj));
3423	}
3424
3425	static const Property rtl8139_properties[] = {
3426	DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3427	};
3428
3429	static void rtl8139_class_init(ObjectClass klass, const void data)
3430	{
3431	DeviceClass *dc = DEVICE_CLASS(klass);
3432	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3433
3434	k->realize = pci_rtl8139_realize;
3435	k->exit = pci_rtl8139_uninit;
3436	k->romfile = "efi-rtl8139.rom";
3437	k->vendor_id = PCI_VENDOR_ID_REALTEK;
3438	k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3439	k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3440	k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3441	device_class_set_legacy_reset(dc, rtl8139_reset);
3442	dc->vmsd = &vmstate_rtl8139;
3443	device_class_set_props(dc, rtl8139_properties);
3444	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
3445	}
3446
3447	static const TypeInfo rtl8139_info = {
3448	.name = TYPE_RTL8139,
3449	.parent = TYPE_PCI_DEVICE,
3450	.instance_size = sizeof(RTL8139State),
3451	.class_init = rtl8139_class_init,
3452	.instance_init = rtl8139_instance_init,
3453	.interfaces = (const InterfaceInfo[]) {
3454	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
3455	{ },
3456	},
3457	};
3458
3459	static void rtl8139_register_types(void)
3460	{
3461	type_register_static(&rtl8139_info);
3462	}
3463
3464	type_init(rtl8139_register_types)