| 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 2 | |
| 3 | # allwinner-sun8i-emac.c |
| 4 | allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 |
| 5 | allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 |
| 6 | allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 |
| 7 | allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 |
| 8 | allwinner_sun8i_emac_reset(void) "HW reset" |
| 9 | allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" |
| 10 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 |
| 11 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 |
| 12 | |
| 13 | # lan9118_phy.c |
| 14 | lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 |
| 15 | lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 |
| 16 | lan9118_phy_update_link(const char *s) "%s" |
| 17 | lan9118_phy_reset(void) "" |
| 18 | |
| 19 | # lance.c |
| 20 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" |
| 21 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" |
| 22 | |
| 23 | # ne2000.c |
| 24 | ne2000_read(uint64_t addr, uint64_t val) "read addr=0x%" PRIx64 " val=0x%" PRIx64 |
| 25 | ne2000_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 |
| 26 | ne2000_ioport_read(uint64_t addr, uint64_t val) "io read addr=0x%02" PRIx64 " val=0x%02" PRIx64 |
| 27 | ne2000_ioport_write(uint64_t addr, uint64_t val) "io write addr=0x%02" PRIx64 " val=0x%02" PRIx64 |
| 28 | |
| 29 | # opencores_eth.c |
| 30 | open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x" |
| 31 | open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x" |
| 32 | open_eth_update_irq(uint32_t v) "IRQ <- 0x%x" |
| 33 | open_eth_receive(unsigned len) "RX: len: %u" |
| 34 | open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x" |
| 35 | open_eth_receive_reject(void) "RX: rejected" |
| 36 | open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x" |
| 37 | open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: 0x%08x, len: %u, tx_len: %u" |
| 38 | open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x" |
| 39 | open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x" |
| 40 | open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x" |
| 41 | open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x" |
| 42 | |
| 43 | # pcnet.c |
| 44 | pcnet_s_reset(void *s) "s=%p" |
| 45 | pcnet_user_int(void *s) "s=%p" |
| 46 | pcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old) "s=%p INTA=%d<=%d" |
| 47 | pcnet_init(void *s, uint64_t init_addr) "s=%p init_addr=0x%"PRIx64 |
| 48 | pcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen) "s=%p rlen=%d tlen=%d" |
| 49 | pcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl) "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]" |
| 50 | |
| 51 | # pcnet-pci.c |
| 52 | pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" |
| 53 | pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" |
| 54 | pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d" |
| 55 | pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d" |
| 56 | |
| 57 | # net_rx_pkt.c |
| 58 | net_rx_pkt_parsed(bool ip4, bool ip6, int l4proto, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, l4 protocol: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu" |
| 59 | net_rx_pkt_l4_csum_validate_entry(void) "Starting L4 checksum validation" |
| 60 | net_rx_pkt_l4_csum_validate_not_xxp(void) "Not a TCP/UDP packet" |
| 61 | net_rx_pkt_l4_csum_validate_udp_with_no_checksum(void) "UDP packet without checksum" |
| 62 | net_rx_pkt_l4_csum_validate_ip4_fragment(void) "IP4 fragment" |
| 63 | net_rx_pkt_l4_csum_validate_csum(bool csum_valid) "Checksum valid: %d" |
| 64 | |
| 65 | net_rx_pkt_l4_csum_calc_entry(void) "Starting L4 checksum calculation" |
| 66 | net_rx_pkt_l4_csum_calc_ip4_udp(void) "IP4/UDP packet" |
| 67 | net_rx_pkt_l4_csum_calc_ip4_tcp(void) "IP4/TCP packet" |
| 68 | net_rx_pkt_l4_csum_calc_ip6_udp(void) "IP6/UDP packet" |
| 69 | net_rx_pkt_l4_csum_calc_ip6_tcp(void) "IP6/TCP packet" |
| 70 | net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, length %u" |
| 71 | net_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum) "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X" |
| 72 | |
| 73 | net_rx_pkt_l4_csum_fix_entry(void) "Starting L4 checksum correction" |
| 74 | net_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso) "TCP packet, L4 cso: %u" |
| 75 | net_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso) "UDP packet, L4 cso: %u" |
| 76 | net_rx_pkt_l4_csum_fix_not_xxp(void) "Not an IP4 packet" |
| 77 | net_rx_pkt_l4_csum_fix_ip4_fragment(void) "IP4 fragment" |
| 78 | net_rx_pkt_l4_csum_fix_udp_with_no_checksum(void) "UDP packet without checksum" |
| 79 | net_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum) "L4 Checksum: Offset: %u, value 0x%X" |
| 80 | |
| 81 | net_rx_pkt_l3_csum_validate_entry(void) "Starting L3 checksum validation" |
| 82 | net_rx_pkt_l3_csum_validate_not_ip4(void) "Not an IP4 packet" |
| 83 | net_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid) "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d" |
| 84 | |
| 85 | net_rx_pkt_rss_ip4(void) "Calculating IPv4 RSS hash" |
| 86 | net_rx_pkt_rss_ip4_tcp(void) "Calculating IPv4/TCP RSS hash" |
| 87 | net_rx_pkt_rss_ip4_udp(void) "Calculating IPv4/UDP RSS hash" |
| 88 | net_rx_pkt_rss_ip6_tcp(void) "Calculating IPv6/TCP RSS hash" |
| 89 | net_rx_pkt_rss_ip6_udp(void) "Calculating IPv6/UDP RSS hash" |
| 90 | net_rx_pkt_rss_ip6(void) "Calculating IPv6 RSS hash" |
| 91 | net_rx_pkt_rss_ip6_ex(void) "Calculating IPv6/EX RSS hash" |
| 92 | net_rx_pkt_rss_ip6_ex_tcp(void) "Calculating IPv6/EX/TCP RSS hash" |
| 93 | net_rx_pkt_rss_ip6_ex_udp(void) "Calculating IPv6/EX/UDP RSS hash" |
| 94 | net_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash) "RSS hash for %zu bytes: 0x%X" |
| 95 | net_rx_pkt_rss_add_chunk(void* ptr, size_t size, size_t input_offset) "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes" |
| 96 | |
| 97 | # e1000.c |
| 98 | e1000_receiver_overrun(size_t s, uint32_t rdh, uint32_t rdt) "Receiver overrun: dropped packet of %zu bytes, RDH=%u, RDT=%u" |
| 99 | |
| 100 | # e1000x_common.c |
| 101 | e1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master) "link_up: %d, rx_enabled %d, pci_master %d" |
| 102 | e1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet) "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X" |
| 103 | e1000x_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X" |
| 104 | e1000x_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X" |
| 105 | e1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x" |
| 106 | e1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x" |
| 107 | e1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val) "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x" |
| 108 | e1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS = %u" |
| 109 | e1000x_rx_disabled(uint32_t rctl_reg) "Received packet dropped because receive is disabled RCTL = %u" |
| 110 | e1000x_rx_oversized(size_t size) "Received packet dropped because it was oversized (%zu bytes)" |
| 111 | e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x" |
| 112 | e1000x_link_negotiation_start(void) "Start link auto negotiation" |
| 113 | e1000x_link_negotiation_done(void) "Auto negotiation is completed" |
| 114 | |
| 115 | # e1000e_core.c |
| 116 | e1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 |
| 117 | e1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 |
| 118 | e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x" |
| 119 | e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED" |
| 120 | e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x" |
| 121 | e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED" |
| 122 | e1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X" |
| 123 | e1000e_core_ctrl_sw_reset(void) "Doing SW reset" |
| 124 | e1000e_core_ctrl_phy_reset(void) "Doing PHY reset" |
| 125 | |
| 126 | e1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d" |
| 127 | e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" |
| 128 | e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" |
| 129 | e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d" |
| 130 | e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d" |
| 131 | e1000e_link_status_changed(bool status) "New link status: %d" |
| 132 | |
| 133 | e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 |
| 134 | e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 |
| 135 | e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)" |
| 136 | e1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented." |
| 137 | e1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented." |
| 138 | e1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported" |
| 139 | e1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported" |
| 140 | e1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported" |
| 141 | e1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported" |
| 142 | e1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported" |
| 143 | |
| 144 | e1000e_tx_disabled(void) "TX Disabled" |
| 145 | e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x" |
| 146 | |
| 147 | e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u" |
| 148 | |
| 149 | e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full" |
| 150 | e1000e_rx_can_recv(void) "Can receive" |
| 151 | e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u" |
| 152 | e1000e_rx_null_descriptor(void) "Null RX descriptor!!" |
| 153 | e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]" |
| 154 | e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]" |
| 155 | e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]" |
| 156 | e1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u" |
| 157 | e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" |
| 158 | e1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u" |
| 159 | e1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x" |
| 160 | e1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments" |
| 161 | e1000e_rx_flt_dropped(void) "Received packet dropped by RX filter" |
| 162 | e1000e_rx_written_to_guest(int queue_idx) "Received packet written to guest (queue %d)" |
| 163 | e1000e_rx_not_written_to_guest(int queue_idx) "Received packet NOT written to guest (queue %d)" |
| 164 | e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)" |
| 165 | e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)" |
| 166 | e1000e_rx_set_cso(int cso_state) "RX CSO state set to %d" |
| 167 | e1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u" |
| 168 | e1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X" |
| 169 | e1000e_rx_start_recv(void) |
| 170 | |
| 171 | e1000e_rx_rss_started(void) "Starting RSS processing" |
| 172 | e1000e_rx_rss_disabled(void) "RSS is disabled" |
| 173 | e1000e_rx_rss_type(uint32_t type) "RSS type is %u" |
| 174 | e1000e_rx_rss_ip4(int l4hdr_proto, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: L4 header protocol %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d" |
| 175 | e1000e_rx_rss_ip6_rfctl(uint32_t rfctl) "RSS IPv6: rfctl 0x%X" |
| 176 | e1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, int l4hdr_proto, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6ex_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: ex_dis: %d, new_ex_dis: %d, L4 header protocol %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6ex enabled %d, ipv6ex enabled %d, ipv6 enabled %d" |
| 177 | |
| 178 | e1000e_rx_metadata_protocols(bool hasip4, bool hasip6, int l4hdr_protocol) "protocols: ip4: %d, ip6: %d, l4hdr: %d" |
| 179 | e1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X" |
| 180 | e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X" |
| 181 | e1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X" |
| 182 | e1000e_rx_metadata_ack(void) "the packet is TCP ACK" |
| 183 | e1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u" |
| 184 | e1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info" |
| 185 | e1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled" |
| 186 | e1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled" |
| 187 | e1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum" |
| 188 | e1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum" |
| 189 | e1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X" |
| 190 | e1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL" |
| 191 | e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL" |
| 192 | |
| 193 | e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X" |
| 194 | |
| 195 | e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x" |
| 196 | e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR" |
| 197 | e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR" |
| 198 | e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]" |
| 199 | e1000e_irq_legacy_notify(bool level) "IRQ line state: %d" |
| 200 | e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x" |
| 201 | e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x" |
| 202 | e1000e_irq_clear(uint32_t offset, uint32_t old, uint32_t new) "Clearing interrupt register 0x%x: 0x%x --> 0x%x" |
| 203 | e1000e_irq_set(uint32_t offset, uint32_t old, uint32_t new) "Setting interrupt register 0x%x: 0x%x --> 0x%x" |
| 204 | e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x" |
| 205 | e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x" |
| 206 | e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" |
| 207 | e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" |
| 208 | e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" |
| 209 | e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" |
| 210 | e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" |
| 211 | e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int" |
| 212 | e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" |
| 213 | e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" |
| 214 | e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing ICR on read due corresponding IMS bit: 0x%x & 0x%x" |
| 215 | e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" |
| 216 | e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" |
| 217 | e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" |
| 218 | e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts" |
| 219 | e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns" |
| 220 | e1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X" |
| 221 | e1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running" |
| 222 | e1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running" |
| 223 | e1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running" |
| 224 | e1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running" |
| 225 | e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u" |
| 226 | e1000e_irq_itr_set(uint32_t val) "ITR = %u" |
| 227 | e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)" |
| 228 | e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u" |
| 229 | |
| 230 | e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x" |
| 231 | e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x" |
| 232 | |
| 233 | e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x" |
| 234 | |
| 235 | e1000e_vm_state_running(void) "VM state is running" |
| 236 | e1000e_vm_state_stopped(void) "VM state is stopped" |
| 237 | |
| 238 | # e1000e.c |
| 239 | e1000e_cb_pci_realize(void) "E1000E PCI realize entry" |
| 240 | e1000e_cb_pci_uninit(void) "E1000E PCI unit entry" |
| 241 | e1000e_cb_qdev_reset_hold(void) "E1000E qdev reset hold" |
| 242 | e1000e_cb_pre_save(void) "E1000E pre save entry" |
| 243 | e1000e_cb_post_load(void) "E1000E post load entry" |
| 244 | |
| 245 | e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64 |
| 246 | e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64 |
| 247 | e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64 |
| 248 | e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64 |
| 249 | e1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64 |
| 250 | e1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64 |
| 251 | e1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64 |
| 252 | e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented" |
| 253 | e1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 |
| 254 | |
| 255 | e1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d" |
| 256 | e1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d" |
| 257 | e1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d" |
| 258 | |
| 259 | e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x" |
| 260 | e1000e_cfg_support_virtio(bool support) "Virtio header supported: %d" |
| 261 | |
| 262 | # igb.c |
| 263 | igb_write_config(uint32_t address, uint32_t val, int len) "CONFIG write 0x%"PRIx32", value: 0x%"PRIx32", len: %"PRId32 |
| 264 | igbvf_write_config(uint32_t address, uint32_t val, int len) "CONFIG write 0x%"PRIx32", value: 0x%"PRIx32", len: %"PRId32 |
| 265 | |
| 266 | # igb_core.c |
| 267 | igb_core_mdic_read(uint32_t addr, uint32_t data) "MDIC READ: PHY[%u] = 0x%x" |
| 268 | igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED" |
| 269 | igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x" |
| 270 | igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED" |
| 271 | igb_core_vf_reset(uint16_t vfn) "VF%d" |
| 272 | |
| 273 | igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d" |
| 274 | |
| 275 | igb_rx_desc_buff_size(uint32_t b) "buffer size: %u" |
| 276 | igb_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer %u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" |
| 277 | |
| 278 | igb_rx_metadata_rss(uint32_t rss, uint16_t rss_pkt_type) "RSS data: rss: 0x%X, rss_pkt_type: 0x%X" |
| 279 | |
| 280 | igb_irq_icr_clear_gpie_nsicr(void) "Clearing ICR on read due to GPIE.NSICR enabled" |
| 281 | igb_irq_set_iam(uint32_t icr) "Update IAM: 0x%x" |
| 282 | igb_irq_read_iam(uint32_t icr) "Current IAM: 0x%x" |
| 283 | igb_irq_write_eics(uint32_t val, bool msix) "Update EICS: 0x%x MSI-X: %d" |
| 284 | igb_irq_write_eims(uint32_t val, bool msix) "Update EIMS: 0x%x MSI-X: %d" |
| 285 | igb_irq_write_eimc(uint32_t val, bool msix) "Update EIMC: 0x%x MSI-X: %d" |
| 286 | igb_irq_write_eiac(uint32_t val) "Update EIAC: 0x%x" |
| 287 | igb_irq_write_eiam(uint32_t val, bool msix) "Update EIAM: 0x%x MSI-X: %d" |
| 288 | igb_irq_write_eicr(uint32_t val, bool msix) "Update EICR: 0x%x MSI-X: %d" |
| 289 | igb_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = 0x%x" |
| 290 | igb_set_pfmailbox(uint32_t vf_num, uint32_t val) "PFMailbox[%d]: 0x%x" |
| 291 | igb_set_vfmailbox(uint32_t vf_num, uint32_t val) "VFMailbox[%d]: 0x%x" |
| 292 | |
| 293 | igb_wrn_rx_desc_modes_not_supp(int desc_type) "Not supported descriptor type: %d" |
| 294 | |
| 295 | # igbvf.c |
| 296 | igbvf_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 |
| 297 | |
| 298 | # spapr_llan.c |
| 299 | spapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs) "pool=%d count=%"PRId32" rxbufs=%"PRIu32 |
| 300 | spapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd) "use_buf_ptr=%d bd=0x%016"PRIx64 |
| 301 | spapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs) "ptr=%"PRIu32" rxbufs=%"PRIu32 |
| 302 | spapr_vlan_receive(const char *id, uint32_t rx_bufs) "[%s] rx_bufs=%"PRIu32 |
| 303 | spapr_vlan_receive_dma_completed(void) "DMA write completed" |
| 304 | spapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo) "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64 |
| 305 | spapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len) "created RX pool %d for size %"PRIu64 |
| 306 | spapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count) "add buf using pool %d (size %"PRIu64", count=%"PRId32")" |
| 307 | spapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd) "added buf ptr=%"PRIu32" rx_bufs=%"PRIu32" bd=0x%016"PRIx64 |
| 308 | spapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf) "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")" |
| 309 | spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")" |
| 310 | spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) "rxbufs = %"PRIu32 |
| 311 | spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) " buf desc: 0x%"PRIx64 |
| 312 | spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) "%d buffers, total length 0x%x" |
| 313 | |
| 314 | # sungem.c |
| 315 | sungem_tx_checksum(uint16_t start, uint16_t off) "TX checksumming from byte %d, inserting at %d" |
| 316 | sungem_tx_checksum_oob(void) "TX checksum out of packet bounds" |
| 317 | sungem_tx_unfinished(void) "TX packet started without finishing the previous one" |
| 318 | sungem_tx_overflow(void) "TX packet queue overflow" |
| 319 | sungem_tx_finished(uint32_t size) "TX completing %"PRIu32 " bytes packet" |
| 320 | sungem_tx_kick(void) "TX Kick..." |
| 321 | sungem_tx_disabled(void) "TX not enabled" |
| 322 | sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 |
| 323 | sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64 |
| 324 | sungem_tx_reset(void) "TX reset" |
| 325 | sungem_rx_mac_disabled(void) "Check RX MAC disabled" |
| 326 | sungem_rx_txdma_disabled(void) "Check RX TXDMA disabled" |
| 327 | sungem_rx_check(bool full, uint32_t kick, uint32_t done) "Check RX %d (kick=%"PRIu32", done=%"PRIu32")" |
| 328 | sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32 |
| 329 | sungem_rx_mac_multicast(void) "Multicast" |
| 330 | sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".." |
| 331 | sungem_rx_packet(size_t size) "RX got %zu bytes packet" |
| 332 | sungem_rx_disabled(void) "RX not enabled" |
| 333 | sungem_rx_bad_frame_size(size_t size) "RX bad frame size %zu, dropped" |
| 334 | sungem_rx_unmatched(void) "No match, dropped" |
| 335 | sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 |
| 336 | sungem_rx_ringfull(void) "RX ring full" |
| 337 | sungem_rx_desc(uint64_t control, uint64_t buffer) "RX desc: 0x%"PRIx64" 0x%"PRIx64 |
| 338 | sungem_rx_reset(void) "RX reset" |
| 339 | sungem_rx_kick(uint64_t val) "RXDMA_KICK written to %"PRIu64 |
| 340 | sungem_reset(bool pci_reset) "Full reset (PCI:%d)" |
| 341 | sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x" |
| 342 | sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x" |
| 343 | sungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32 |
| 344 | sungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x" |
| 345 | sungem_mmio_greg_write(uint64_t addr, uint64_t val) "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64 |
| 346 | sungem_mmio_greg_read(uint64_t addr, uint64_t val) "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64 |
| 347 | sungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64 |
| 348 | sungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64 |
| 349 | sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64 |
| 350 | sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64 |
| 351 | sungem_mmio_wol_write(uint64_t addr, uint64_t val) "MMIO wol write to 0x%"PRIx64" val=0x%"PRIx64 |
| 352 | sungem_mmio_wol_read(uint64_t addr, uint64_t val) "MMIO wol read from 0x%"PRIx64" val=0x%"PRIx64 |
| 353 | sungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64 |
| 354 | sungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64 |
| 355 | sungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64 |
| 356 | sungem_mmio_mif_read(uint64_t addr, uint64_t val) "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64 |
| 357 | sungem_mmio_pcs_write(uint64_t addr, uint64_t val) "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64 |
| 358 | sungem_mmio_pcs_read(uint64_t addr, uint64_t val) "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64 |
| 359 | |
| 360 | # sunhme.c |
| 361 | sunhme_seb_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 362 | sunhme_seb_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 363 | sunhme_etx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 364 | sunhme_etx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 365 | sunhme_erx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 366 | sunhme_erx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 367 | sunhme_mac_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 368 | sunhme_mac_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 369 | sunhme_mii_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 370 | sunhme_mii_read(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" |
| 371 | sunhme_mif_write(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" |
| 372 | sunhme_mif_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 |
| 373 | sunhme_tx_desc(uint64_t buffer, uint32_t status, int cr, int nr) "addr 0x%"PRIx64" status 0x%"PRIx32 " (ring %d/%d)" |
| 374 | sunhme_tx_xsum_add(int offset, int len) "adding xsum at offset %d, len %d" |
| 375 | sunhme_tx_xsum_stuff(uint16_t xsum, int offset) "stuffing xsum 0x%x at offset %d" |
| 376 | sunhme_tx_done(int len) "successfully transmitted frame with len %d" |
| 377 | sunhme_rx_incoming(size_t len) "received incoming frame with len %zu" |
| 378 | sunhme_rx_filter_destmac(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "received frame for MAC: %02x:%02x:%02x:%02x:%02x:%02x" |
| 379 | sunhme_rx_filter_local_match(void) "incoming frame matches local MAC address" |
| 380 | sunhme_rx_filter_bcast_match(void) "incoming frame matches broadcast MAC address" |
| 381 | sunhme_rx_filter_hash_nomatch(void) "incoming MAC address not in hash table" |
| 382 | sunhme_rx_filter_hash_match(void) "incoming MAC address found in hash table" |
| 383 | sunhme_rx_filter_promisc_match(void) "incoming frame accepted due to promiscuous mode" |
| 384 | sunhme_rx_filter_reject(void) "rejecting incoming frame" |
| 385 | sunhme_rx_filter_accept(void) "accepting incoming frame" |
| 386 | sunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr) "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)" |
| 387 | sunhme_rx_xsum_calc(uint16_t xsum) "calculated incoming xsum as 0x%x" |
| 388 | sunhme_rx_norxd(void) "no free rx descriptors available" |
| 389 | sunhme_update_irq(uint32_t mifmask, uint32_t mif, uint32_t sebmask, uint32_t seb, int level) "mifmask: 0x%x mif: 0x%x sebmask: 0x%x seb: 0x%x level: %d" |
| 390 | |
| 391 | # virtio-net.c |
| 392 | virtio_net_announce_notify(void) "" |
| 393 | virtio_net_announce_timer(int round) "%d" |
| 394 | virtio_net_handle_announce(int round) "%d" |
| 395 | virtio_net_post_load_device(void) |
| 396 | virtio_net_rss_load(void *nic, size_t nfds, void *fds) "nic=%p nfds=%zu fds=%p" |
| 397 | virtio_net_rss_attach_ebpf(void *nic, int prog_fd) "nic=%p prog-fd=%d" |
| 398 | virtio_net_rss_disable(void *nic) "nic=%p" |
| 399 | virtio_net_rss_error(void *nic, const char *msg, uint32_t value) "nic=%p msg=%s, value 0x%08x" |
| 400 | virtio_net_rss_enable(void *nic, uint32_t p1, uint16_t p2, uint8_t p3) "nic=%p hashes 0x%x, table of %d, key of %d" |
| 401 | |
| 402 | # tulip.c |
| 403 | tulip_reg_write(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 |
| 404 | tulip_reg_read(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 |
| 405 | tulip_receive(const uint8_t *buf, size_t len) "buf %p size %zu" |
| 406 | tulip_descriptor(const char *prefix, uint32_t addr, uint32_t status, uint32_t control, uint32_t len1, uint32_t len2, uint32_t buf1, uint32_t buf2) "%s 0x%08x: status 0x%08x control 0x%03x len1 %4d len2 %4d buf1 0x%08x buf2 0x%08x" |
| 407 | tulip_rx_state(const char *state) "RX %s" |
| 408 | tulip_tx_state(const char *state) "TX %s" |
| 409 | tulip_irq(uint32_t mask, uint32_t en, const char *state) "mask 0x%08x ie 0x%08x %s" |
| 410 | tulip_mii_write(int phy, int reg, uint16_t data) "phy 0x%x reg 0x%x data 0x%04x" |
| 411 | tulip_mii_read(int phy, int reg, uint16_t data) "phy 0x%x, reg 0x%x data 0x%04x" |
| 412 | tulip_reset(void) "" |
| 413 | tulip_setup_frame(void) "" |
| 414 | tulip_setup_filter(int n, uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f) "%d: %02x:%02x:%02x:%02x:%02x:%02x" |
| 415 | |
| 416 | # lasi_i82596.c |
| 417 | lasi_82596_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64" val=0x%04x" |
| 418 | lasi_82596_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64" val=0x%04x" |
| 419 | |
| 420 | # i82596.c |
| 421 | i82596_s_reset(void *s) "%p Reset chip" |
| 422 | i82596_transmit(uint32_t size, uint32_t addr) "size %u from addr 0x%04x" |
| 423 | i82596_receive_analysis(const char *s) "%s" |
| 424 | i82596_receive_queue_full(void) "Packet queue full, dropping packet" |
| 425 | i82596_receive_suspended(void) "RX unit suspended, queueing packet" |
| 426 | i82596_rx_state_change(uint8_t old_state, uint8_t new_state) "RX state changed from %d to %d" |
| 427 | i82596_new_mac(const char *id_with_mac) "New MAC for: %s" |
| 428 | i82596_set_multicast(uint16_t count) "Added %d multicast entries" |
| 429 | i82596_scb_command(uint8_t cuc, uint8_t ruc) "SCB command CUC=0x%02x RUC=0x%02x" |
| 430 | i82596_dump(uint32_t addr) "Dump command to addr 0x%08x" |
| 431 | i82596_flush_queue(int count) "Flushing %d packets from queue" |
| 432 | i82596_tx_tfd(uint64_t addr, uint16_t status, uint16_t cmd, uint32_t link, uint32_t tbd) "TFD @0x%"PRIx64": status=0x%04x cmd=0x%04x link=0x%08x tbd=0x%08x" |
| 433 | i82596_tx_tbd(uint64_t addr, uint16_t size, uint32_t buf) "TBD @0x%"PRIx64": size=%d buf=0x%08x" |
| 434 | i82596_rx_rfd(uint64_t addr, uint16_t status, uint16_t cmd, uint32_t link, uint32_t rbd) "RFD @0x%"PRIx64": status=0x%04x cmd=0x%04x link=0x%08x rbd=0x%08x" |
| 435 | i82596_rx_rbd(uint64_t addr, uint16_t count, uint32_t buf, uint16_t size) "RBD @0x%"PRIx64": count=%d buf=0x%08x size=%d" |
| 436 | i82596_receive_packet(const uint8_t *buf, size_t size) "RX packet %p size %zu" |
| 437 | i82596_rx_short_frame(size_t size) "RX: Frame too short (%zu bytes)" |
| 438 | i82596_rx_rfd_update(uint32_t addr, uint32_t next_rfd) "RX: Updating RFD 0x%08x to point to 0x%08x" |
| 439 | i82596_rx_out_of_rbds(void) "RX: Out of RBDs mid-frame" |
| 440 | i82596_rx_incomplete(size_t copied, size_t total) "RX: Incomplete copy (%zu/%zu bytes)" |
| 441 | i82596_rx_complete(uint32_t crc, uint32_t align, uint32_t resource) "RX: Complete (errors: CRC=%d align=%d res=%d)" |
| 442 | i82596_receive_iov(size_t size, int iovcnt) "RX IOV: %zu bytes in %d vectors" |
| 443 | i82596_ca_init(uint32_t scb, uint8_t mode, uint32_t base) "CA: Init - SCB=0x%08x mode=%d base=0x%08x" |
| 444 | i82596_ioport_write(uint32_t addr, uint32_t val) "IO write addr=0x%08x val=0x%08x" |
| 445 | |
| 446 | # imx_fec.c |
| 447 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" |
| 448 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" |
| 449 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" |
| 450 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" |
| 451 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" |
| 452 | imx_eth_rx_bd_full(void) "RX buffer is full" |
| 453 | imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 |
| 454 | imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 |
| 455 | imx_fec_receive(size_t size) "len %zu" |
| 456 | imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" |
| 457 | imx_fec_receive_last(int last) "rx frame flags 0x%04x" |
| 458 | imx_enet_receive(size_t size) "len %zu" |
| 459 | imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" |
| 460 | imx_enet_receive_last(int last) "rx frame flags 0x%04x" |
| 461 | |
| 462 | # npcm7xx_emc.c |
| 463 | npcm7xx_emc_reset(int emc_num) "Resetting emc%d" |
| 464 | npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" |
| 465 | npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" |
| 466 | npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" |
| 467 | npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x" |
| 468 | npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" |
| 469 | npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x" |
| 470 | npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" |
| 471 | npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s" |
| 472 | npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" |
| 473 | npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" |
| 474 | npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" |
| 475 | npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x" |
| 476 | npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]" |
| 477 | npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x" |
| 478 | |
| 479 | # npcm_gmac.c |
| 480 | npcm_gmac_reg_read(const char *name, uint64_t offset, uint32_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 |
| 481 | npcm_gmac_reg_write(const char *name, uint64_t offset, uint32_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 |
| 482 | npcm_gmac_mdio_access(const char *name, uint8_t is_write, uint8_t pa, uint8_t gr, uint16_t val) "%s: is_write: %" PRIu8 " pa: %" PRIu8 " gr: %" PRIu8 " val: 0x%04" PRIx16 |
| 483 | npcm_gmac_reset(const char *name, uint16_t value) "%s: phy_regs[0][1]: 0x%04" PRIx16 |
| 484 | npcm_gmac_set_link(bool active) "Set link: active=%u" |
| 485 | npcm_gmac_update_irq(const char *name, uint32_t status, uint32_t intr_en, int level) "%s: Status Reg: 0x%04" PRIX32 " Interrupt Enable Reg: 0x%04" PRIX32 " IRQ Set: %d" |
| 486 | npcm_gmac_packet_desc_read(const char* name, uint32_t desc_addr) "%s: attempting to read descriptor @0x%04" PRIX32 |
| 487 | npcm_gmac_packet_receive(const char* name, uint32_t len) "%s: RX packet length: 0x%04" PRIX32 |
| 488 | npcm_gmac_packet_receiving_buffer(const char* name, uint32_t buf_len, uint32_t rx_buf_addr) "%s: Receiving into Buffer size: 0x%04" PRIX32 " at address 0x%04" PRIX32 |
| 489 | npcm_gmac_packet_received(const char* name, uint32_t len) "%s: Reception finished, packet left: 0x%04" PRIX32 |
| 490 | npcm_gmac_packet_sent(const char* name, uint16_t len) "%s: TX packet sent!, length: 0x%04" PRIX16 |
| 491 | npcm_gmac_debug_desc_data(const char* name, void* addr, uint32_t des0, uint32_t des1, uint32_t des2, uint32_t des3)"%s: Address: %p Descriptor 0: 0x%04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 " Descriptor 3: 0x%04" PRIX32 |
| 492 | npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t tdes1) "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32 |
| 493 | npcm_gmac_tx_desc_owner(const char* name, uint32_t desc_addr) "%s: TX Descriptor @0x%04" PRIX32 " is owned by software" |
| 494 | |
| 495 | # npcm_pcs.c |
| 496 | npcm_pcs_reg_read(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| 497 | npcm_pcs_reg_write(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| 498 | |
| 499 | # dp8398x.c |
| 500 | dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" |
| 501 | dp8393x_lower_irq(void) "lower irq" |
| 502 | dp8393x_load_cam(int idx, int cam0, int cam1, int cam2, int cam3, int cam4, int cam5) "load cam[%d] with 0x%02x0x%02x0x%02x0x%02x0x%02x0x%02x" |
| 503 | dp8393x_load_cam_done(int cen) "load cam done. cam enable mask 0x%04x" |
| 504 | dp8393x_read_rra_regs(int crba0, int crba1, int rbwc0, int rbwc1) "CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x" |
| 505 | dp8393x_transmit_packet(int ttda) "Transmit packet at 0x%"PRIx32 |
| 506 | dp8393x_transmit_txlen_error(int len) "tx_len is %d" |
| 507 | dp8393x_read(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" |
| 508 | dp8393x_write(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" |
| 509 | dp8393x_write_invalid(int reg) "writing to reg %d invalid" |
| 510 | dp8393x_write_invalid_dcr(const char *name) "writing to %s invalid" |
| 511 | dp8393x_receive_oversize(int size) "oversize packet, pkt_size is %d" |
| 512 | dp8393x_receive_not_netcard(void) "packet not for netcard" |
| 513 | dp8393x_receive_packet(int crba) "Receive packet at 0x%"PRIx32 |
| 514 | dp8393x_receive_write_status(int crba) "Write status at 0x%"PRIx32 |
| 515 | |
| 516 | # xen_nic.c |
| 517 | xen_netdev_realize(int dev, const char *info, const char *peer) "vif%u info '%s' peer '%s'" |
| 518 | xen_netdev_unrealize(int dev) "vif%u" |
| 519 | xen_netdev_create(int dev) "vif%u" |
| 520 | xen_netdev_destroy(int dev) "vif%u" |
| 521 | xen_netdev_disconnect(int dev) "vif%u" |
| 522 | xen_netdev_connect(int dev, unsigned int tx, unsigned int rx, int port) "vif%u tx %u rx %u port %u" |
| 523 | xen_netdev_frontend_changed(const char *dev, int state) "vif%s state %d" |
| 524 | xen_netdev_tx(int dev, int ref, int off, int len, unsigned int flags, const char *c, const char *d, const char *m, const char *e) "vif%u ref %u off %u len %u flags 0x%x%s%s%s%s" |
| 525 | xen_netdev_rx(int dev, int idx, int status, int flags) "vif%u idx %d status %d flags 0x%x" |
| 526 | |
| 527 | # xilinx_ethlite.c |
| 528 | ethlite_pkt_lost(uint32_t rx_ctrl) "rx_ctrl:0x%" PRIx32 |
| 529 | ethlite_pkt_size_too_big(uint64_t size) "size:0x%" PRIx64 |
| 530 | ethlite_pkt_tx_size_too_big(uint64_t size) "size:0x%" PRIx64 |