| 1 | #ifndef HW_TULIP_H |
| 2 | #define HW_TULIP_H |
| 3 | |
| 4 | #include "qemu/units.h" |
| 5 | #include "net/net.h" |
| 6 | #include "qom/object.h" |
| 7 | |
| 8 | #define TYPE_TULIP "tulip" |
| 9 | OBJECT_DECLARE_SIMPLE_TYPE(TULIPState, TULIP) |
| 10 | |
| 11 | #define CSR(_x) ((_x) << 3) |
| 12 | |
| 13 | #define CSR0_SWR BIT(0) |
| 14 | #define CSR0_BAR BIT(1) |
| 15 | #define CSR0_DSL_SHIFT 2 |
| 16 | #define CSR0_DSL_MASK 0x1f |
| 17 | #define CSR0_BLE BIT(7) |
| 18 | #define CSR0_PBL_SHIFT 8 |
| 19 | #define CSR0_PBL_MASK 0x3f |
| 20 | #define CSR0_CAC_SHIFT 14 |
| 21 | #define CSR0_CAC_MASK 0x3 |
| 22 | #define CSR0_DAS 0x10000 |
| 23 | #define CSR0_TAP_SHIFT 17 |
| 24 | #define CSR0_TAP_MASK 0x7 |
| 25 | #define CSR0_DBO 0x100000 |
| 26 | #define CSR1_TPD 0x01 |
| 27 | #define CSR0_RLE BIT(23) |
| 28 | #define CSR0_WIE BIT(24) |
| 29 | |
| 30 | #define CSR2_RPD 0x01 |
| 31 | |
| 32 | #define CSR5_TI BIT(0) |
| 33 | #define CSR5_TPS BIT(1) |
| 34 | #define CSR5_TU BIT(2) |
| 35 | #define CSR5_TJT BIT(3) |
| 36 | #define CSR5_LNP_ANC BIT(4) |
| 37 | #define CSR5_UNF BIT(5) |
| 38 | #define CSR5_RI BIT(6) |
| 39 | #define CSR5_RU BIT(7) |
| 40 | #define CSR5_RPS BIT(8) |
| 41 | #define CSR5_RWT BIT(9) |
| 42 | #define CSR5_ETI BIT(10) |
| 43 | #define CSR5_GTE BIT(11) |
| 44 | #define CSR5_LNF BIT(12) |
| 45 | #define CSR5_FBE BIT(13) |
| 46 | #define CSR5_ERI BIT(14) |
| 47 | #define CSR5_AIS BIT(15) |
| 48 | #define CSR5_NIS BIT(16) |
| 49 | #define CSR5_RS_SHIFT 17 |
| 50 | #define CSR5_RS_MASK 7 |
| 51 | #define CSR5_TS_SHIFT 20 |
| 52 | #define CSR5_TS_MASK 7 |
| 53 | |
| 54 | #define CSR5_TS_STOPPED 0 |
| 55 | #define CSR5_TS_RUNNING_FETCH 1 |
| 56 | #define CSR5_TS_RUNNING_WAIT_EOT 2 |
| 57 | #define CSR5_TS_RUNNING_READ_BUF 3 |
| 58 | #define CSR5_TS_RUNNING_SETUP 5 |
| 59 | #define CSR5_TS_SUSPENDED 6 |
| 60 | #define CSR5_TS_RUNNING_CLOSE 7 |
| 61 | |
| 62 | #define CSR5_RS_STOPPED 0 |
| 63 | #define CSR5_RS_RUNNING_FETCH 1 |
| 64 | #define CSR5_RS_RUNNING_CHECK_EOR 2 |
| 65 | #define CSR5_RS_RUNNING_WAIT_RECEIVE 3 |
| 66 | #define CSR5_RS_SUSPENDED 4 |
| 67 | #define CSR5_RS_RUNNING_CLOSE 5 |
| 68 | #define CSR5_RS_RUNNING_FLUSH 6 |
| 69 | #define CSR5_RS_RUNNING_QUEUE 7 |
| 70 | |
| 71 | #define CSR5_EB_SHIFT 23 |
| 72 | #define CSR5_EB_MASK 7 |
| 73 | |
| 74 | #define CSR5_GPI BIT(26) |
| 75 | #define CSR5_LC BIT(27) |
| 76 | |
| 77 | #define CSR6_HP BIT(0) |
| 78 | #define CSR6_SR BIT(1) |
| 79 | #define CSR6_HO BIT(2) |
| 80 | #define CSR6_PB BIT(3) |
| 81 | #define CSR6_IF BIT(4) |
| 82 | #define CSR6_SB BIT(5) |
| 83 | #define CSR6_PR BIT(6) |
| 84 | #define CSR6_PM BIT(7) |
| 85 | #define CSR6_FKD BIT(8) |
| 86 | #define CSR6_FD BIT(9) |
| 87 | |
| 88 | #define CSR6_OM_SHIFT 10 |
| 89 | #define CSR6_OM_MASK 3 |
| 90 | #define CSR6_OM_NORMAL 0 |
| 91 | #define CSR6_OM_INT_LOOPBACK 1 |
| 92 | #define CSR6_OM_EXT_LOOPBACK 2 |
| 93 | |
| 94 | #define CSR6_FC BIT(12) |
| 95 | #define CSR6_ST BIT(13) |
| 96 | |
| 97 | |
| 98 | #define CSR6_TR_SHIFT 14 |
| 99 | #define CSR6_TR_MASK 3 |
| 100 | #define CSR6_TR_72 0 |
| 101 | #define CSR6_TR_96 1 |
| 102 | #define CSR6_TR_128 2 |
| 103 | #define CSR6_TR_160 3 |
| 104 | |
| 105 | #define CSR6_CA BIT(17) |
| 106 | #define CSR6_RA BIT(30) |
| 107 | #define CSR6_SC BIT(31) |
| 108 | |
| 109 | #define CSR7_TIM BIT(0) |
| 110 | #define CSR7_TSM BIT(1) |
| 111 | #define CSR7_TUM BIT(2) |
| 112 | #define CSR7_TJM BIT(3) |
| 113 | #define CSR7_LPM BIT(4) |
| 114 | #define CSR7_UNM BIT(5) |
| 115 | #define CSR7_RIM BIT(6) |
| 116 | #define CSR7_RUM BIT(7) |
| 117 | #define CSR7_RSM BIT(8) |
| 118 | #define CSR7_RWM BIT(9) |
| 119 | #define CSR7_TMM BIT(11) |
| 120 | #define CSR7_LFM BIT(12) |
| 121 | #define CSR7_SEM BIT(13) |
| 122 | #define CSR7_ERM BIT(14) |
| 123 | #define CSR7_AIM BIT(15) |
| 124 | #define CSR7_NIM BIT(16) |
| 125 | |
| 126 | #define CSR8_MISSED_FRAME_OVL BIT(16) |
| 127 | #define CSR8_MISSED_FRAME_CNT_MASK 0xffff |
| 128 | |
| 129 | #define CSR9_DATA_MASK 0xff |
| 130 | #define CSR9_SR_CS BIT(0) |
| 131 | #define CSR9_SR_SK BIT(1) |
| 132 | #define CSR9_SR_DI BIT(2) |
| 133 | #define CSR9_SR_DO BIT(3) |
| 134 | #define CSR9_REG BIT(10) |
| 135 | #define CSR9_SR BIT(11) |
| 136 | #define CSR9_BR BIT(12) |
| 137 | #define CSR9_WR BIT(13) |
| 138 | #define CSR9_RD BIT(14) |
| 139 | #define CSR9_MOD BIT(15) |
| 140 | #define CSR9_MDC BIT(16) |
| 141 | #define CSR9_MDO BIT(17) |
| 142 | #define CSR9_MII BIT(18) |
| 143 | #define CSR9_MDI BIT(19) |
| 144 | |
| 145 | #define CSR11_CON BIT(16) |
| 146 | #define CSR11_TIMER_MASK 0xffff |
| 147 | |
| 148 | #define CSR12_MRA BIT(0) |
| 149 | #define CSR12_LS100 BIT(1) |
| 150 | #define CSR12_LS10 BIT(2) |
| 151 | #define CSR12_APS BIT(3) |
| 152 | #define CSR12_ARA BIT(8) |
| 153 | #define CSR12_TRA BIT(9) |
| 154 | #define CSR12_NSN BIT(10) |
| 155 | #define CSR12_TRF BIT(11) |
| 156 | #define CSR12_ANS_SHIFT 12 |
| 157 | #define CSR12_ANS_MASK 7 |
| 158 | #define CSR12_LPN BIT(15) |
| 159 | #define CSR12_LPC_SHIFT 16 |
| 160 | #define CSR12_LPC_MASK 0xffff |
| 161 | |
| 162 | #define CSR13_SRL BIT(0) |
| 163 | #define CSR13_CAC BIT(2) |
| 164 | #define CSR13_AUI BIT(3) |
| 165 | #define CSR13_SDM_SHIFT 4 |
| 166 | #define CSR13_SDM_MASK 0xfff |
| 167 | |
| 168 | #define CSR14_ECEN BIT(0) |
| 169 | #define CSR14_LBK BIT(1) |
| 170 | #define CSR14_DREN BIT(2) |
| 171 | #define CSR14_LSE BIT(3) |
| 172 | #define CSR14_CPEN_SHIFT 4 |
| 173 | #define CSR14_CPEN_MASK 3 |
| 174 | #define CSR14_MBO BIT(6) |
| 175 | #define CSR14_ANE BIT(7) |
| 176 | #define CSR14_RSQ BIT(8) |
| 177 | #define CSR14_CSQ BIT(9) |
| 178 | #define CSR14_CLD BIT(10) |
| 179 | #define CSR14_SQE BIT(11) |
| 180 | #define CSR14_LTE BIT(12) |
| 181 | #define CSR14_APE BIT(13) |
| 182 | #define CSR14_SPP BIT(14) |
| 183 | #define CSR14_TAS BIT(15) |
| 184 | |
| 185 | #define CSR15_JBD BIT(0) |
| 186 | #define CSR15_HUJ BIT(1) |
| 187 | #define CSR15_JCK BIT(2) |
| 188 | #define CSR15_ABM BIT(3) |
| 189 | #define CSR15_RWD BIT(4) |
| 190 | #define CSR15_RWR BIT(5) |
| 191 | #define CSR15_LE1 BIT(6) |
| 192 | #define CSR15_LV1 BIT(7) |
| 193 | #define CSR15_TSCK BIT(8) |
| 194 | #define CSR15_FUSQ BIT(9) |
| 195 | #define CSR15_FLF BIT(10) |
| 196 | #define CSR15_LSD BIT(11) |
| 197 | #define CSR15_DPST BIT(12) |
| 198 | #define CSR15_FRL BIT(13) |
| 199 | #define CSR15_LE2 BIT(14) |
| 200 | #define CSR15_LV2 BIT(15) |
| 201 | |
| 202 | #define RDES0_OF BIT(0) |
| 203 | #define RDES0_CE BIT(1) |
| 204 | #define RDES0_DB BIT(2) |
| 205 | #define RDES0_RJ BIT(4) |
| 206 | #define RDES0_FT BIT(5) |
| 207 | #define RDES0_CS BIT(6) |
| 208 | #define RDES0_TL BIT(7) |
| 209 | #define RDES0_LS BIT(8) |
| 210 | #define RDES0_FS BIT(9) |
| 211 | #define RDES0_MF BIT(10) |
| 212 | #define RDES0_RF BIT(11) |
| 213 | #define RDES0_DT_SHIFT 12 |
| 214 | #define RDES0_DT_MASK 3 |
| 215 | #define RDES0_DE BIT(14) |
| 216 | #define RDES0_ES BIT(15) |
| 217 | #define RDES0_FL_SHIFT 16 |
| 218 | #define RDES0_FL_MASK 0x3fff |
| 219 | #define RDES0_FF BIT(30) |
| 220 | #define RDES0_OWN BIT(31) |
| 221 | |
| 222 | #define RDES1_BUF1_SIZE_SHIFT 0 |
| 223 | #define RDES1_BUF1_SIZE_MASK 0x7ff |
| 224 | |
| 225 | #define RDES1_BUF2_SIZE_SHIFT 11 |
| 226 | #define RDES1_BUF2_SIZE_MASK 0x7ff |
| 227 | #define RDES1_RCH BIT(24) |
| 228 | #define RDES1_RER BIT(25) |
| 229 | |
| 230 | #define TDES0_DE BIT(0) |
| 231 | #define TDES0_UF BIT(1) |
| 232 | #define TDES0_LF BIT(2) |
| 233 | #define TDES0_CC_SHIFT 3 |
| 234 | #define TDES0_CC_MASK 0xf |
| 235 | #define TDES0_HF BIT(7) |
| 236 | #define TDES0_EC BIT(8) |
| 237 | #define TDES0_LC BIT(9) |
| 238 | #define TDES0_NC BIT(10) |
| 239 | #define TDES0_LO BIT(11) |
| 240 | #define TDES0_TO BIT(14) |
| 241 | #define TDES0_ES BIT(15) |
| 242 | #define TDES0_OWN BIT(31) |
| 243 | |
| 244 | #define TDES1_BUF1_SIZE_SHIFT 0 |
| 245 | #define TDES1_BUF1_SIZE_MASK 0x7ff |
| 246 | |
| 247 | #define TDES1_BUF2_SIZE_SHIFT 11 |
| 248 | #define TDES1_BUF2_SIZE_MASK 0x7ff |
| 249 | |
| 250 | #define TDES1_FT0 BIT(22) |
| 251 | #define TDES1_DPD BIT(23) |
| 252 | #define TDES1_TCH BIT(24) |
| 253 | #define TDES1_TER BIT(25) |
| 254 | #define TDES1_AC BIT(26) |
| 255 | #define TDES1_SET BIT(27) |
| 256 | #define TDES1_FT1 BIT(28) |
| 257 | #define TDES1_FS BIT(29) |
| 258 | #define TDES1_LS BIT(30) |
| 259 | #define TDES1_IC BIT(31) |
| 260 | |
| 261 | struct tulip_descriptor { |
| 262 | uint32_t status; |
| 263 | uint32_t control; |
| 264 | uint32_t buf_addr1; |
| 265 | uint32_t buf_addr2; |
| 266 | }; |
| 267 | |
| 268 | #endif |