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1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "qemu/osdep.h"
19 #include "hw/core/hw-error.h"
20 #include "hw/pci/pci.h"
21 #include "hw/core/qdev-properties.h"
22 #include "net/tap.h"
23 #include "net/checksum.h"
24 #include "system/system.h"
25 #include "qemu/log.h"
26 #include "qemu/module.h"
27 #include "hw/pci/msix.h"
28 #include "hw/pci/msi.h"
29 #include "migration/register.h"
30 #include "migration/vmstate.h"
31
32 #include "vmxnet3.h"
33 #include "vmxnet3_defs.h"
34 #include "vmxnet_debug.h"
35 #include "vmware_utils.h"
36 #include "net_tx_pkt.h"
37 #include "net_rx_pkt.h"
38 #include "qom/object.h"
39
40 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
41 #define VMXNET3_MSIX_BAR_SIZE 0x2000
42
43 #define VMXNET3_EXP_EP_OFFSET (0x48)
44 #define VMXNET3_MSI_OFFSET (0x84)
45 #define VMXNET3_MSIX_OFFSET (0x9c)
46 #define VMXNET3_DSN_OFFSET (0x100)
47
48 #define VMXNET3_BAR0_IDX (0)
49 #define VMXNET3_BAR1_IDX (1)
50 #define VMXNET3_MSIX_BAR_IDX (2)
51
52 #define VMXNET3_OFF_MSIX_TABLE (0x000)
53 #define VMXNET3_OFF_MSIX_PBA (0x1000)
54
55 /* Link speed in Mbps should be shifted by 16 */
56 #define VMXNET3_LINK_SPEED (1000 << 16)
57
58 /* Link status: 1 - up, 0 - down. */
59 #define VMXNET3_LINK_STATUS_UP 0x1
60
61 /* Least significant bit should be set for revision and version */
62 #define VMXNET3_UPT_REVISION 0x1
63 #define VMXNET3_DEVICE_REVISION 0x1
64
65 /* Number of interrupt vectors for non-MSIx modes */
66 #define VMXNET3_MAX_NMSIX_INTRS (1)
67
68 /* Macros for rings descriptors access */
69 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
70 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
71
72 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
73 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
74
75 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
76 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
77
78 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
79 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
80
81 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
82 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
83
84 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
85 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
86
87 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
88 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
89
90 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
91 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
92
93 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
94 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
95
96 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
97 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
98
99 /* Macros for guest driver shared area access */
100 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
101 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
102
103 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
104 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
105
106 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
107 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
108
109 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
110 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
111
112 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
113 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
114
115 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
116 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
117
118 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
119
120 struct VMXNET3Class {
121 PCIDeviceClass parent_class;
122 DeviceRealize parent_dc_realize;
123 };
124 typedef struct VMXNET3Class VMXNET3Class;
125
126 DECLARE_CLASS_CHECKERS(VMXNET3Class, VMXNET3_DEVICE,
127 TYPE_VMXNET3)
128
129 static inline void vmxnet3_ring_init(PCIDevice *d,
130 Vmxnet3Ring *ring,
131 hwaddr pa,
132 uint32_t size,
133 uint32_t cell_size,
134 bool zero_region)
135 {
136 ring->pa = pa;
137 ring->size = size;
138 ring->cell_size = cell_size;
139 ring->gen = VMXNET3_INIT_GEN;
140 ring->next = 0;
141
142 if (zero_region) {
143 vmw_shmem_set(d, pa, 0, size * cell_size);
144 }
145 }
146
147 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
148 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
149 (ring_name), (ridx), \
150 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
151
152 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
153 {
154 if (++ring->next >= ring->size) {
155 ring->next = 0;
156 ring->gen ^= 1;
157 }
158 }
159
160 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
161 {
162 if (ring->next-- == 0) {
163 ring->next = ring->size - 1;
164 ring->gen ^= 1;
165 }
166 }
167
168 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
169 {
170 return ring->pa + ring->next * ring->cell_size;
171 }
172
173 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
174 void *buff)
175 {
176 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
177 }
178
179 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
180 void *buff)
181 {
182 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
183 }
184
185 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
186 {
187 return ring->next;
188 }
189
190 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
191 {
192 return ring->gen;
193 }
194
195 /* Debug trace-related functions */
196 static inline void
197 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
198 {
199 VMW_PKPRN("TX DESCR: "
200 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
201 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
202 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
203 descr->addr, descr->len, descr->gen, descr->rsvd,
204 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
205 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
206 }
207
208 static inline void
209 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
210 {
211 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
212 "csum_start: %d, csum_offset: %d",
213 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
214 vhdr->csum_start, vhdr->csum_offset);
215 }
216
217 static inline void
218 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
219 {
220 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
221 "dtype: %d, ext1: %d, btype: %d",
222 descr->addr, descr->len, descr->gen,
223 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
224 }
225
226 /* Interrupt management */
227
228 /*
229 * This function returns sign whether interrupt line is in asserted state
230 * This depends on the type of interrupt used. For INTX interrupt line will
231 * be asserted until explicit deassertion, for MSI(X) interrupt line will
232 * be deasserted automatically due to notification semantics of the MSI(X)
233 * interrupts
234 */
235 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
236 {
237 PCIDevice *d = PCI_DEVICE(s);
238
239 if (s->msix_used && msix_enabled(d)) {
240 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
241 msix_notify(d, int_idx);
242 return false;
243 }
244 if (msi_enabled(d)) {
245 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
246 msi_notify(d, int_idx);
247 return false;
248 }
249
250 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
251 pci_irq_assert(d);
252 return true;
253 }
254
255 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
256 {
257 PCIDevice *d = PCI_DEVICE(s);
258
259 /*
260 * This function should never be called for MSI(X) interrupts
261 * because deassertion never required for message interrupts
262 */
263 assert(!s->msix_used || !msix_enabled(d));
264 /*
265 * This function should never be called for MSI(X) interrupts
266 * because deassertion never required for message interrupts
267 */
268 assert(!msi_enabled(d));
269
270 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
271 pci_irq_deassert(d);
272 }
273
274 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
275 {
276 if (!s->interrupt_states[lidx].is_pending &&
277 s->interrupt_states[lidx].is_asserted) {
278 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
279 _vmxnet3_deassert_interrupt_line(s, lidx);
280 s->interrupt_states[lidx].is_asserted = false;
281 return;
282 }
283
284 if (s->interrupt_states[lidx].is_pending &&
285 !s->interrupt_states[lidx].is_masked &&
286 !s->interrupt_states[lidx].is_asserted) {
287 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
288 s->interrupt_states[lidx].is_asserted =
289 _vmxnet3_assert_interrupt_line(s, lidx);
290 s->interrupt_states[lidx].is_pending = false;
291 return;
292 }
293 }
294
295 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
296 {
297 PCIDevice *d = PCI_DEVICE(s);
298 s->interrupt_states[lidx].is_pending = true;
299 vmxnet3_update_interrupt_line_state(s, lidx);
300
301 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
302 goto do_automask;
303 }
304
305 if (msi_enabled(d) && s->auto_int_masking) {
306 goto do_automask;
307 }
308
309 return;
310
311 do_automask:
312 s->interrupt_states[lidx].is_masked = true;
313 vmxnet3_update_interrupt_line_state(s, lidx);
314 }
315
316 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
317 {
318 return s->interrupt_states[lidx].is_asserted;
319 }
320
321 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
322 {
323 s->interrupt_states[int_idx].is_pending = false;
324 if (s->auto_int_masking) {
325 s->interrupt_states[int_idx].is_masked = true;
326 }
327 vmxnet3_update_interrupt_line_state(s, int_idx);
328 }
329
330 static void
331 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
332 {
333 s->interrupt_states[lidx].is_masked = is_masked;
334 vmxnet3_update_interrupt_line_state(s, lidx);
335 }
336
337 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem)
338 {
339 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC);
340 }
341
342 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
343 #define VMXNET3_MAKE_BYTE(byte_num, val) \
344 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
345
346 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
347 {
348 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
349 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
350 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
351 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
352 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
353 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
354
355 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
356
357 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
358 }
359
360 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
361 {
362 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
363 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
364 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
365 VMXNET3_MAKE_BYTE(3, addr->a[3]);
366 }
367
368 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
369 {
370 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
371 VMXNET3_MAKE_BYTE(1, addr->a[5]);
372 }
373
374 static void
375 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
376 {
377 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
378 }
379
380 static inline void
381 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
382 {
383 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
384 }
385
386 static inline void
387 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
388 {
389 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
390 }
391
392 static void
393 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
394 {
395 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
396 }
397
398 static void
399 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
400 {
401 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
402 }
403
404 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
405 {
406 struct Vmxnet3_TxCompDesc txcq_descr;
407 PCIDevice *d = PCI_DEVICE(s);
408
409 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
410
411 memset(&txcq_descr, 0, sizeof(txcq_descr));
412 txcq_descr.txdIdx = tx_ridx;
413 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
414 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1);
415 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2);
416 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);
417
418 /* Flush changes in TX descriptor before changing the counter value */
419 smp_wmb();
420
421 vmxnet3_inc_tx_completion_counter(s, qidx);
422 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
423 }
424
425 static bool
426 vmxnet3_setup_tx_offloads(VMXNET3State *s)
427 {
428 switch (s->offload_mode) {
429 case VMXNET3_OM_NONE:
430 return net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
431
432 case VMXNET3_OM_CSUM:
433 VMW_PKPRN("L4 CSO requested\n");
434 return net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
435
436 case VMXNET3_OM_TSO:
437 VMW_PKPRN("GSO offload requested.");
438 if (!net_tx_pkt_build_vheader(s->tx_pkt, true, true,
439 s->cso_or_gso_size)) {
440 return false;
441 }
442 net_tx_pkt_update_ip_checksums(s->tx_pkt);
443 break;
444
445 default:
446 g_assert_not_reached();
447 }
448
449 return true;
450 }
451
452 static void
453 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
454 const struct Vmxnet3_TxDesc *txd)
455 {
456 s->offload_mode = txd->om;
457 s->cso_or_gso_size = txd->msscof;
458 s->tci = txd->tci;
459 s->needs_vlan = txd->ti;
460 }
461
462 typedef enum {
463 VMXNET3_PKT_STATUS_OK,
464 VMXNET3_PKT_STATUS_ERROR,
465 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
466 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
467 } Vmxnet3PktStatus;
468
469 static void
470 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
471 Vmxnet3PktStatus status)
472 {
473 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt);
474 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
475
476 switch (status) {
477 case VMXNET3_PKT_STATUS_OK:
478 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) {
479 case ETH_PKT_BCAST:
480 stats->bcastPktsTxOK++;
481 stats->bcastBytesTxOK += tot_len;
482 break;
483 case ETH_PKT_MCAST:
484 stats->mcastPktsTxOK++;
485 stats->mcastBytesTxOK += tot_len;
486 break;
487 case ETH_PKT_UCAST:
488 stats->ucastPktsTxOK++;
489 stats->ucastBytesTxOK += tot_len;
490 break;
491 default:
492 g_assert_not_reached();
493 }
494
495 if (s->offload_mode == VMXNET3_OM_TSO) {
496 /*
497 * According to VMWARE headers this statistic is a number
498 * of packets after segmentation but since we don't have
499 * this information in QEMU model, the best we can do is to
500 * provide number of non-segmented packets
501 */
502 stats->TSOPktsTxOK++;
503 stats->TSOBytesTxOK += tot_len;
504 }
505 break;
506
507 case VMXNET3_PKT_STATUS_DISCARD:
508 stats->pktsTxDiscard++;
509 break;
510
511 case VMXNET3_PKT_STATUS_ERROR:
512 stats->pktsTxError++;
513 break;
514
515 default:
516 g_assert_not_reached();
517 }
518 }
519
520 static void
521 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
522 int qidx,
523 Vmxnet3PktStatus status)
524 {
525 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
526 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt);
527
528 switch (status) {
529 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
530 stats->pktsRxOutOfBuf++;
531 break;
532
533 case VMXNET3_PKT_STATUS_ERROR:
534 stats->pktsRxError++;
535 break;
536 case VMXNET3_PKT_STATUS_OK:
537 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
538 case ETH_PKT_BCAST:
539 stats->bcastPktsRxOK++;
540 stats->bcastBytesRxOK += tot_len;
541 break;
542 case ETH_PKT_MCAST:
543 stats->mcastPktsRxOK++;
544 stats->mcastBytesRxOK += tot_len;
545 break;
546 case ETH_PKT_UCAST:
547 stats->ucastPktsRxOK++;
548 stats->ucastBytesRxOK += tot_len;
549 break;
550 default:
551 g_assert_not_reached();
552 }
553
554 if (tot_len > s->mtu) {
555 stats->LROPktsRxOK++;
556 stats->LROBytesRxOK += tot_len;
557 }
558 break;
559 default:
560 g_assert_not_reached();
561 }
562 }
563
564 static inline void
565 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring,
566 struct Vmxnet3_TxDesc *txd)
567 {
568 vmxnet3_ring_read_curr_cell(pcidev, ring, txd);
569 txd->addr = le64_to_cpu(txd->addr);
570 txd->val1 = le32_to_cpu(txd->val1);
571 txd->val2 = le32_to_cpu(txd->val2);
572 }
573
574 static inline bool
575 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
576 int qidx,
577 struct Vmxnet3_TxDesc *txd,
578 uint32_t *descr_idx)
579 {
580 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
581 PCIDevice *d = PCI_DEVICE(s);
582
583 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
584 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
585 /* Only read after generation field verification */
586 smp_rmb();
587 /* Re-read to be sure we got the latest version */
588 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
589 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
590 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
591 vmxnet3_inc_tx_consumption_counter(s, qidx);
592 return true;
593 }
594
595 return false;
596 }
597
598 static bool
599 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
600 {
601 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
602
603 if (!vmxnet3_setup_tx_offloads(s)) {
604 status = VMXNET3_PKT_STATUS_ERROR;
605 goto func_exit;
606 }
607
608 /* debug prints */
609 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt));
610 net_tx_pkt_dump(s->tx_pkt);
611
612 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
613 status = VMXNET3_PKT_STATUS_DISCARD;
614 goto func_exit;
615 }
616
617 func_exit:
618 vmxnet3_on_tx_done_update_stats(s, qidx, status);
619 return (status == VMXNET3_PKT_STATUS_OK);
620 }
621
622 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
623 {
624 struct Vmxnet3_TxDesc txd;
625 uint32_t txd_idx;
626 uint32_t data_len;
627 hwaddr data_pa;
628
629 for (;;) {
630 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
631 break;
632 }
633
634 vmxnet3_dump_tx_descr(&txd);
635
636 if (!s->skip_current_tx_pkt) {
637 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
638 data_pa = txd.addr;
639
640 if (!net_tx_pkt_add_raw_fragment_pci(s->tx_pkt, PCI_DEVICE(s),
641 data_pa, data_len)) {
642 s->skip_current_tx_pkt = true;
643 }
644 }
645
646 if (s->tx_sop) {
647 vmxnet3_tx_retrieve_metadata(s, &txd);
648 s->tx_sop = false;
649 }
650
651 if (txd.eop) {
652 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) {
653 if (s->needs_vlan) {
654 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
655 }
656
657 vmxnet3_send_packet(s, qidx);
658 } else {
659 vmxnet3_on_tx_done_update_stats(s, qidx,
660 VMXNET3_PKT_STATUS_ERROR);
661 }
662
663 vmxnet3_complete_packet(s, qidx, txd_idx);
664 s->tx_sop = true;
665 s->skip_current_tx_pkt = false;
666 net_tx_pkt_reset(s->tx_pkt,
667 net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
668 }
669 }
670
671 net_tx_pkt_reset(s->tx_pkt, net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
672 }
673
674 static inline void
675 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
676 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
677 {
678 PCIDevice *d = PCI_DEVICE(s);
679
680 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
681 *didx = vmxnet3_ring_curr_cell_idx(ring);
682 vmxnet3_ring_read_curr_cell(d, ring, dbuf);
683 dbuf->addr = le64_to_cpu(dbuf->addr);
684 dbuf->val1 = le32_to_cpu(dbuf->val1);
685 dbuf->ext1 = le32_to_cpu(dbuf->ext1);
686 }
687
688 static inline uint8_t
689 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
690 {
691 return s->rxq_descr[qidx].rx_ring[ridx].gen;
692 }
693
694 static inline hwaddr
695 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
696 {
697 uint8_t ring_gen;
698 struct Vmxnet3_RxCompDesc rxcd;
699
700 hwaddr daddr =
701 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
702
703 pci_dma_read(PCI_DEVICE(s),
704 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
705 rxcd.val1 = le32_to_cpu(rxcd.val1);
706 rxcd.val2 = le32_to_cpu(rxcd.val2);
707 rxcd.val3 = le32_to_cpu(rxcd.val3);
708 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
709
710 if (rxcd.gen != ring_gen) {
711 *descr_gen = ring_gen;
712 vmxnet3_inc_rx_completion_counter(s, qidx);
713 return daddr;
714 }
715
716 return 0;
717 }
718
719 static inline void
720 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
721 {
722 vmxnet3_dec_rx_completion_counter(s, qidx);
723 }
724
725 #define RXQ_IDX (0)
726 #define RX_HEAD_BODY_RING (0)
727 #define RX_BODY_ONLY_RING (1)
728
729 static bool
730 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
731 struct Vmxnet3_RxDesc *descr_buf,
732 uint32_t *descr_idx,
733 uint32_t *ridx)
734 {
735 for (;;) {
736 uint32_t ring_gen;
737 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
738 descr_buf, descr_idx);
739
740 /* If no more free descriptors - return */
741 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
742 if (descr_buf->gen != ring_gen) {
743 return false;
744 }
745
746 /* Only read after generation field verification */
747 smp_rmb();
748 /* Re-read to be sure we got the latest version */
749 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
750 descr_buf, descr_idx);
751
752 /* Mark current descriptor as used/skipped */
753 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
754
755 /* If this is what we are looking for - return */
756 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
757 *ridx = RX_HEAD_BODY_RING;
758 return true;
759 }
760 }
761 }
762
763 static bool
764 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
765 struct Vmxnet3_RxDesc *d,
766 uint32_t *didx,
767 uint32_t *ridx)
768 {
769 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
770
771 /* Try to find corresponding descriptor in head/body ring */
772 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
773 /* Only read after generation field verification */
774 smp_rmb();
775 /* Re-read to be sure we got the latest version */
776 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
777 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
778 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
779 *ridx = RX_HEAD_BODY_RING;
780 return true;
781 }
782 }
783
784 /*
785 * If there is no free descriptors on head/body ring or next free
786 * descriptor is a head descriptor switch to body only ring
787 */
788 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
789
790 /* If no more free descriptors - return */
791 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
792 /* Only read after generation field verification */
793 smp_rmb();
794 /* Re-read to be sure we got the latest version */
795 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
796 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
797 *ridx = RX_BODY_ONLY_RING;
798 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
799 return true;
800 }
801
802 return false;
803 }
804
805 static inline bool
806 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
807 struct Vmxnet3_RxDesc *descr_buf,
808 uint32_t *descr_idx,
809 uint32_t *ridx)
810 {
811 if (is_head || !s->rx_packets_compound) {
812 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
813 } else {
814 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
815 }
816 }
817
818 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
819 * the implementation always passes an RxCompDesc with a "Checksum
820 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
821 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
822 *
823 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
824 * and place a fully computed checksum into the tcp/udp header.
825 * Otherwise, the OS driver will receive a checksum-correct indication
826 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
827 * having just the pseudo header csum value.
828 *
829 * While this is not a problem if packet is destined for local delivery,
830 * in the case the host OS performs forwarding, it will forward an
831 * incorrectly checksummed packet.
832 */
833 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt,
834 const void *pkt_data,
835 size_t pkt_len)
836 {
837 struct virtio_net_hdr *vhdr;
838 bool hasip4, hasip6;
839 EthL4HdrProto l4hdr_proto;
840 uint8_t *data;
841 int len;
842
843 vhdr = net_rx_pkt_get_vhdr(pkt);
844 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
845 return;
846 }
847
848 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
849 if (!(hasip4 || hasip6) ||
850 (l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
851 l4hdr_proto != ETH_L4_HDR_PROTO_UDP)) {
852 return;
853 }
854
855 vmxnet3_dump_virt_hdr(vhdr);
856
857 /* Validate packet len: csum_start + scum_offset + length of csum field */
858 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
859 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
860 "cannot calculate checksum",
861 pkt_len, vhdr->csum_start, vhdr->csum_offset);
862 return;
863 }
864
865 data = (uint8_t *)pkt_data + vhdr->csum_start;
866 len = pkt_len - vhdr->csum_start;
867 /* Put the checksum obtained into the packet */
868 stw_be_p(data + vhdr->csum_offset,
869 net_checksum_finish_nozero(net_checksum_add(len, data)));
870
871 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
872 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
873 }
874
875 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt,
876 struct Vmxnet3_RxCompDesc *rxcd)
877 {
878 int csum_ok, is_gso;
879 bool hasip4, hasip6;
880 EthL4HdrProto l4hdr_proto;
881 struct virtio_net_hdr *vhdr;
882 uint8_t offload_type;
883
884 if (net_rx_pkt_is_vlan_stripped(pkt)) {
885 rxcd->ts = 1;
886 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt);
887 }
888
889 vhdr = net_rx_pkt_get_vhdr(pkt);
890 /*
891 * Checksum is valid when lower level tell so or when lower level
892 * requires checksum offload telling that packet produced/bridged
893 * locally and did travel over network after last checksum calculation
894 * or production
895 */
896 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
897 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
898
899 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
900 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
901
902 if (!csum_ok && !is_gso) {
903 goto nocsum;
904 }
905
906 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
907 if ((l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
908 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) ||
909 (!hasip4 && !hasip6)) {
910 goto nocsum;
911 }
912
913 rxcd->cnc = 0;
914 rxcd->v4 = hasip4 ? 1 : 0;
915 rxcd->v6 = hasip6 ? 1 : 0;
916 rxcd->tcp = l4hdr_proto == ETH_L4_HDR_PROTO_TCP;
917 rxcd->udp = l4hdr_proto == ETH_L4_HDR_PROTO_UDP;
918 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
919 return;
920
921 nocsum:
922 rxcd->cnc = 1;
923 }
924
925 static void
926 vmxnet3_pci_dma_writev(PCIDevice *pci_dev,
927 const struct iovec *iov,
928 size_t start_iov_off,
929 hwaddr target_addr,
930 size_t bytes_to_copy)
931 {
932 size_t curr_off = 0;
933 size_t copied = 0;
934
935 while (bytes_to_copy) {
936 if (start_iov_off < (curr_off + iov->iov_len)) {
937 size_t chunk_len =
938 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
939
940 pci_dma_write(pci_dev, target_addr + copied,
941 iov->iov_base + start_iov_off - curr_off,
942 chunk_len);
943
944 copied += chunk_len;
945 start_iov_off += chunk_len;
946 curr_off = start_iov_off;
947 bytes_to_copy -= chunk_len;
948 } else {
949 curr_off += iov->iov_len;
950 }
951 iov++;
952 }
953 }
954
955 static void
956 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa,
957 struct Vmxnet3_RxCompDesc *rxcd)
958 {
959 rxcd->val1 = cpu_to_le32(rxcd->val1);
960 rxcd->val2 = cpu_to_le32(rxcd->val2);
961 rxcd->val3 = cpu_to_le32(rxcd->val3);
962 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd));
963 }
964
965 static bool
966 vmxnet3_indicate_packet(VMXNET3State *s)
967 {
968 struct Vmxnet3_RxDesc rxd;
969 PCIDevice *d = PCI_DEVICE(s);
970 bool is_head = true;
971 uint32_t rxd_idx;
972 uint32_t rx_ridx = 0;
973
974 struct Vmxnet3_RxCompDesc rxcd;
975 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
976 hwaddr new_rxcd_pa = 0;
977 hwaddr ready_rxcd_pa = 0;
978 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt);
979 size_t bytes_copied = 0;
980 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt);
981 uint16_t num_frags = 0;
982 size_t chunk_size;
983
984 net_rx_pkt_dump(s->rx_pkt);
985
986 while (bytes_left > 0) {
987
988 /* cannot add more frags to packet */
989 if (num_frags == s->max_rx_frags) {
990 break;
991 }
992
993 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
994 if (!new_rxcd_pa) {
995 break;
996 }
997
998 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
999 break;
1000 }
1001
1002 chunk_size = MIN(bytes_left, rxd.len);
1003 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size);
1004 bytes_copied += chunk_size;
1005 bytes_left -= chunk_size;
1006
1007 vmxnet3_dump_rx_descr(&rxd);
1008
1009 if (ready_rxcd_pa != 0) {
1010 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1011 }
1012
1013 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1014 rxcd.rxdIdx = rxd_idx;
1015 rxcd.len = chunk_size;
1016 rxcd.sop = is_head;
1017 rxcd.gen = new_rxcd_gen;
1018 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1019
1020 if (bytes_left == 0) {
1021 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1022 }
1023
1024 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1025 "sop %d csum_correct %lu",
1026 (unsigned long) rx_ridx,
1027 (unsigned long) rxcd.rxdIdx,
1028 (unsigned long) rxcd.len,
1029 (int) rxcd.sop,
1030 (unsigned long) rxcd.tuc);
1031
1032 is_head = false;
1033 ready_rxcd_pa = new_rxcd_pa;
1034 new_rxcd_pa = 0;
1035 num_frags++;
1036 }
1037
1038 if (ready_rxcd_pa != 0) {
1039 rxcd.eop = 1;
1040 rxcd.err = (bytes_left != 0);
1041
1042 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1043
1044 /* Flush RX descriptor changes */
1045 smp_wmb();
1046 }
1047
1048 if (new_rxcd_pa != 0) {
1049 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1050 }
1051
1052 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1053
1054 if (bytes_left == 0) {
1055 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1056 return true;
1057 } else if (num_frags == s->max_rx_frags) {
1058 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1059 return false;
1060 } else {
1061 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1062 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1063 return false;
1064 }
1065 }
1066
1067 static void
1068 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1069 uint64_t val, unsigned size)
1070 {
1071 VMXNET3State *s = opaque;
1072
1073 if (!s->device_active) {
1074 return;
1075 }
1076
1077 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1078 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1079 int tx_queue_idx =
1080 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1081 VMXNET3_REG_ALIGN);
1082 if (tx_queue_idx < s->txq_num) {
1083 vmxnet3_process_tx_queue(s, tx_queue_idx);
1084 } else {
1085 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Illegal TX queue %d/%d\n",
1086 tx_queue_idx, s->txq_num);
1087 }
1088 return;
1089 }
1090
1091 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1092 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1093 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1094 VMXNET3_REG_ALIGN);
1095
1096 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1097
1098 vmxnet3_on_interrupt_mask_changed(s, l, val);
1099 return;
1100 }
1101
1102 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1103 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1104 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1105 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1106 return;
1107 }
1108
1109 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1110 (uint64_t) addr, val, size);
1111 }
1112
1113 static uint64_t
1114 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1115 {
1116 VMXNET3State *s = opaque;
1117
1118 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1119 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1120 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1121 VMXNET3_REG_ALIGN);
1122 return s->interrupt_states[l].is_masked;
1123 }
1124
1125 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1126 return 0;
1127 }
1128
1129 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1130 {
1131 int i;
1132 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1133 s->interrupt_states[i].is_asserted = false;
1134 s->interrupt_states[i].is_pending = false;
1135 s->interrupt_states[i].is_masked = true;
1136 }
1137 }
1138
1139 static void vmxnet3_reset_mac(VMXNET3State *s)
1140 {
1141 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1142 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
1143 }
1144
1145 static void vmxnet3_deactivate_device(VMXNET3State *s)
1146 {
1147 if (s->device_active) {
1148 VMW_CBPRN("Deactivating vmxnet3...");
1149 net_tx_pkt_uninit(s->tx_pkt);
1150 net_rx_pkt_uninit(s->rx_pkt);
1151 s->device_active = false;
1152 }
1153 }
1154
1155 static void vmxnet3_reset(VMXNET3State *s)
1156 {
1157 VMW_CBPRN("Resetting vmxnet3...");
1158
1159 vmxnet3_deactivate_device(s);
1160 vmxnet3_reset_interrupt_states(s);
1161 s->drv_shmem = 0;
1162 s->tx_sop = true;
1163 s->skip_current_tx_pkt = false;
1164 }
1165
1166 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1167 {
1168 PCIDevice *d = PCI_DEVICE(s);
1169
1170 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1171 devRead.rxFilterConf.rxMode);
1172 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1173 }
1174
1175 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1176 {
1177 int i;
1178 PCIDevice *d = PCI_DEVICE(s);
1179
1180 /* Copy configuration from shared memory */
1181 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem,
1182 devRead.rxFilterConf.vfTable,
1183 s->vlan_table,
1184 sizeof(s->vlan_table));
1185
1186 /* Invert byte order when needed */
1187 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1188 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1189 }
1190
1191 /* Dump configuration for debugging purposes */
1192 VMW_CFPRN("Configured VLANs:");
1193 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1194 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1195 VMW_CFPRN("\tVLAN %d is present", i);
1196 }
1197 }
1198 }
1199
1200 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1201 {
1202 PCIDevice *d = PCI_DEVICE(s);
1203
1204 uint16_t list_bytes =
1205 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem,
1206 devRead.rxFilterConf.mfTableLen);
1207
1208 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1209
1210 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1211 if (!s->mcast_list) {
1212 if (s->mcast_list_len == 0) {
1213 VMW_CFPRN("Current multicast list is empty");
1214 } else {
1215 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1216 s->mcast_list_len);
1217 }
1218 s->mcast_list_len = 0;
1219 } else {
1220 int i;
1221 hwaddr mcast_list_pa =
1222 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem,
1223 devRead.rxFilterConf.mfTablePA);
1224
1225 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes);
1226
1227 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1228 for (i = 0; i < s->mcast_list_len; i++) {
1229 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a));
1230 }
1231 }
1232 }
1233
1234 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1235 {
1236 vmxnet3_update_rx_mode(s);
1237 vmxnet3_update_vlan_filters(s);
1238 vmxnet3_update_mcast_filters(s);
1239 }
1240
1241 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1242 {
1243 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1244 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1245 return interrupt_mode;
1246 }
1247
1248 static void vmxnet3_fill_stats(VMXNET3State *s)
1249 {
1250 int i;
1251 PCIDevice *d = PCI_DEVICE(s);
1252
1253 if (!s->device_active)
1254 return;
1255
1256 for (i = 0; i < s->txq_num; i++) {
1257 pci_dma_write(d,
1258 s->txq_descr[i].tx_stats_pa,
1259 &s->txq_descr[i].txq_stats,
1260 sizeof(s->txq_descr[i].txq_stats));
1261 }
1262
1263 for (i = 0; i < s->rxq_num; i++) {
1264 pci_dma_write(d,
1265 s->rxq_descr[i].rx_stats_pa,
1266 &s->rxq_descr[i].rxq_stats,
1267 sizeof(s->rxq_descr[i].rxq_stats));
1268 }
1269 }
1270
1271 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1272 {
1273 struct Vmxnet3_GOSInfo gos;
1274 PCIDevice *d = PCI_DEVICE(s);
1275
1276 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos,
1277 &gos, sizeof(gos));
1278 s->rx_packets_compound =
1279 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1280
1281 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1282 }
1283
1284 static void
1285 vmxnet3_dump_conf_descr(const char *name,
1286 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1287 {
1288 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1289 name, pm_descr->confVer, pm_descr->confLen);
1290
1291 };
1292
1293 static void vmxnet3_update_pm_state(VMXNET3State *s)
1294 {
1295 struct Vmxnet3_VariableLenConfDesc pm_descr;
1296 PCIDevice *d = PCI_DEVICE(s);
1297
1298 pm_descr.confLen =
1299 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen);
1300 pm_descr.confVer =
1301 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer);
1302 pm_descr.confPA =
1303 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA);
1304
1305 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1306 }
1307
1308 static void vmxnet3_update_features(VMXNET3State *s)
1309 {
1310 uint32_t guest_features;
1311 int rxcso_supported;
1312 PCIDevice *d = PCI_DEVICE(s);
1313
1314 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1315 devRead.misc.uptFeatures);
1316
1317 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1318 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1319 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1320
1321 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1322 s->lro_supported, rxcso_supported,
1323 s->rx_vlan_stripping);
1324 if (s->peer_has_vhdr) {
1325 NetOffloads ol = { .csum = rxcso_supported,
1326 .tso4 = s->lro_supported,
1327 .tso6 = s->lro_supported };
1328
1329 qemu_set_offload(qemu_get_queue(s->nic)->peer, &ol);
1330 }
1331 }
1332
1333 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1334 {
1335 return s->msix_used || msi_enabled(PCI_DEVICE(s))
1336 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1;
1337 }
1338
1339 static bool vmxnet3_validate_irq_idx(const char *type, bool is_msix, int idx)
1340 {
1341 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1342
1343 if (idx >= max_ints) {
1344 qemu_log_mask(LOG_GUEST_ERROR,
1345 "vmxnet3: Bad %s queue interrupt index: %d\n",
1346 type, idx);
1347 return false;
1348 }
1349
1350 return true;
1351 }
1352
1353 static bool vmxnet3_validate_interrupts(VMXNET3State *s)
1354 {
1355 int i;
1356
1357 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1358 if (!vmxnet3_validate_irq_idx("event", s->msix_used, s->event_int_idx)) {
1359 return false;
1360 }
1361
1362 for (i = 0; i < s->txq_num; i++) {
1363 int idx = s->txq_descr[i].intr_idx;
1364 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1365 if (!vmxnet3_validate_irq_idx("TX", s->msix_used, idx)) {
1366 return false;
1367 }
1368 }
1369
1370 for (i = 0; i < s->rxq_num; i++) {
1371 int idx = s->rxq_descr[i].intr_idx;
1372 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1373 if (!vmxnet3_validate_irq_idx("RX", s->msix_used, idx)) {
1374 return false;
1375 }
1376 }
1377
1378 return true;
1379 }
1380
1381 static bool vmxnet3_validate_queues(VMXNET3State *s)
1382 {
1383 /*
1384 * txq_num and rxq_num are total number of queues
1385 * configured by guest. These numbers must not
1386 * exceed corresponding maximal values.
1387 */
1388
1389 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1390 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad TX queues number: %d\n",
1391 s->txq_num);
1392 return false;
1393 }
1394
1395 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1396 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad RX queues number: %d\n",
1397 s->rxq_num);
1398 return false;
1399 }
1400
1401 return true;
1402 }
1403
1404 static void vmxnet3_activate_device(VMXNET3State *s)
1405 {
1406 int i;
1407 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1408 PCIDevice *d = PCI_DEVICE(s);
1409 hwaddr qdescr_table_pa;
1410 uint64_t pa;
1411 uint32_t size;
1412
1413 /* Verify configuration consistency */
1414 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) {
1415 VMW_ERPRN("Device configuration received from driver is invalid");
1416 return;
1417 }
1418
1419 /* Verify if device is active */
1420 if (s->device_active) {
1421 VMW_CFPRN("Vmxnet3 device is active");
1422 return;
1423 }
1424
1425 s->txq_num =
1426 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues);
1427 s->rxq_num =
1428 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues);
1429
1430 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1431 if (!vmxnet3_validate_queues(s)) {
1432 return;
1433 }
1434
1435 vmxnet3_adjust_by_guest_type(s);
1436 vmxnet3_update_features(s);
1437 vmxnet3_update_pm_state(s);
1438 vmxnet3_setup_rx_filtering(s);
1439 /* Cache fields from shared memory */
1440 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu);
1441 if (s->mtu < VMXNET3_MIN_MTU || s->mtu > VMXNET3_MAX_MTU) {
1442 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad MTU size: %u\n", s->mtu);
1443 return;
1444 }
1445 VMW_CFPRN("MTU is %u", s->mtu);
1446
1447 s->max_rx_frags =
1448 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG);
1449
1450 if (s->max_rx_frags == 0) {
1451 s->max_rx_frags = 1;
1452 }
1453
1454 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1455
1456 s->event_int_idx =
1457 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx);
1458 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1459 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1460
1461 s->auto_int_masking =
1462 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask);
1463 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1464
1465 qdescr_table_pa =
1466 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA);
1467 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1468
1469 /*
1470 * Worst-case scenario is a packet that holds all TX rings space so
1471 * we calculate total size of all TX rings for max TX fragments number
1472 */
1473 s->max_tx_frags = 0;
1474
1475 /* TX queues */
1476 for (i = 0; i < s->txq_num; i++) {
1477 hwaddr qdescr_pa =
1478 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1479
1480 /* Read interrupt number for this TX queue */
1481 s->txq_descr[i].intr_idx =
1482 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx);
1483 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1484
1485 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1486
1487 /* Read rings memory locations for TX queues */
1488 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);
1489 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize);
1490 if (size > VMXNET3_TX_RING_MAX_SIZE) {
1491 size = VMXNET3_TX_RING_MAX_SIZE;
1492 }
1493
1494 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,
1495 sizeof(struct Vmxnet3_TxDesc), false);
1496 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1497
1498 s->max_tx_frags += size;
1499
1500 /* TXC ring */
1501 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);
1502 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize);
1503 if (size > VMXNET3_TC_RING_MAX_SIZE) {
1504 size = VMXNET3_TC_RING_MAX_SIZE;
1505 }
1506 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,
1507 sizeof(struct Vmxnet3_TxCompDesc), true);
1508 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1509
1510 s->txq_descr[i].tx_stats_pa =
1511 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1512
1513 memset(&s->txq_descr[i].txq_stats, 0,
1514 sizeof(s->txq_descr[i].txq_stats));
1515
1516 /* Fill device-managed parameters for queues */
1517 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
1518 ctrl.txThreshold,
1519 VMXNET3_DEF_TX_THRESHOLD);
1520 }
1521
1522 /* Preallocate TX packet wrapper */
1523 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1524 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
1525 net_rx_pkt_init(&s->rx_pkt);
1526
1527 /* Read rings memory locations for RX queues */
1528 for (i = 0; i < s->rxq_num; i++) {
1529 int j;
1530 hwaddr qd_pa =
1531 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1532 i * sizeof(struct Vmxnet3_RxQueueDesc);
1533
1534 /* Read interrupt number for this RX queue */
1535 s->rxq_descr[i].intr_idx =
1536 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx);
1537 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1538
1539 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1540
1541 /* Read rings memory locations */
1542 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1543 /* RX rings */
1544 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);
1545 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]);
1546 if (size > VMXNET3_RX_RING_MAX_SIZE) {
1547 size = VMXNET3_RX_RING_MAX_SIZE;
1548 }
1549 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,
1550 sizeof(struct Vmxnet3_RxDesc), false);
1551 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1552 i, j, pa, size);
1553 }
1554
1555 /* RXC ring */
1556 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);
1557 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize);
1558 if (size > VMXNET3_RC_RING_MAX_SIZE) {
1559 size = VMXNET3_RC_RING_MAX_SIZE;
1560 }
1561 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,
1562 sizeof(struct Vmxnet3_RxCompDesc), true);
1563 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1564
1565 s->rxq_descr[i].rx_stats_pa =
1566 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1567 memset(&s->rxq_descr[i].rxq_stats, 0,
1568 sizeof(s->rxq_descr[i].rxq_stats));
1569 }
1570
1571 if (!vmxnet3_validate_interrupts(s)) {
1572 return;
1573 }
1574
1575 /* Make sure everything is in place before device activation */
1576 smp_wmb();
1577
1578 vmxnet3_reset_mac(s);
1579
1580 s->device_active = true;
1581 }
1582
1583 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1584 {
1585 s->last_command = cmd;
1586
1587 switch (cmd) {
1588 case VMXNET3_CMD_GET_PERM_MAC_HI:
1589 VMW_CBPRN("Set: Get upper part of permanent MAC");
1590 break;
1591
1592 case VMXNET3_CMD_GET_PERM_MAC_LO:
1593 VMW_CBPRN("Set: Get lower part of permanent MAC");
1594 break;
1595
1596 case VMXNET3_CMD_GET_STATS:
1597 VMW_CBPRN("Set: Get device statistics");
1598 vmxnet3_fill_stats(s);
1599 break;
1600
1601 case VMXNET3_CMD_ACTIVATE_DEV:
1602 VMW_CBPRN("Set: Activating vmxnet3 device");
1603 vmxnet3_activate_device(s);
1604 break;
1605
1606 case VMXNET3_CMD_UPDATE_RX_MODE:
1607 VMW_CBPRN("Set: Update rx mode");
1608 vmxnet3_update_rx_mode(s);
1609 break;
1610
1611 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1612 VMW_CBPRN("Set: Update VLAN filters");
1613 vmxnet3_update_vlan_filters(s);
1614 break;
1615
1616 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1617 VMW_CBPRN("Set: Update MAC filters");
1618 vmxnet3_update_mcast_filters(s);
1619 break;
1620
1621 case VMXNET3_CMD_UPDATE_FEATURE:
1622 VMW_CBPRN("Set: Update features");
1623 vmxnet3_update_features(s);
1624 break;
1625
1626 case VMXNET3_CMD_UPDATE_PMCFG:
1627 VMW_CBPRN("Set: Update power management config");
1628 vmxnet3_update_pm_state(s);
1629 break;
1630
1631 case VMXNET3_CMD_GET_LINK:
1632 VMW_CBPRN("Set: Get link");
1633 break;
1634
1635 case VMXNET3_CMD_RESET_DEV:
1636 VMW_CBPRN("Set: Reset device");
1637 vmxnet3_reset(s);
1638 break;
1639
1640 case VMXNET3_CMD_QUIESCE_DEV:
1641 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1642 vmxnet3_deactivate_device(s);
1643 break;
1644
1645 case VMXNET3_CMD_GET_CONF_INTR:
1646 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1647 break;
1648
1649 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1650 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1651 "adaptive ring info flags");
1652 break;
1653
1654 case VMXNET3_CMD_GET_DID_LO:
1655 VMW_CBPRN("Set: Get lower part of device ID");
1656 break;
1657
1658 case VMXNET3_CMD_GET_DID_HI:
1659 VMW_CBPRN("Set: Get upper part of device ID");
1660 break;
1661
1662 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1663 VMW_CBPRN("Set: Get device extra info");
1664 break;
1665
1666 default:
1667 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1668 break;
1669 }
1670 }
1671
1672 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1673 {
1674 uint64_t ret;
1675
1676 switch (s->last_command) {
1677 case VMXNET3_CMD_ACTIVATE_DEV:
1678 ret = (s->device_active) ? 0 : 1;
1679 VMW_CFPRN("Device active: %" PRIx64, ret);
1680 break;
1681
1682 case VMXNET3_CMD_RESET_DEV:
1683 case VMXNET3_CMD_QUIESCE_DEV:
1684 case VMXNET3_CMD_GET_QUEUE_STATUS:
1685 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1686 ret = 0;
1687 break;
1688
1689 case VMXNET3_CMD_GET_LINK:
1690 ret = s->link_status_and_speed;
1691 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1692 break;
1693
1694 case VMXNET3_CMD_GET_PERM_MAC_LO:
1695 ret = vmxnet3_get_mac_low(&s->perm_mac);
1696 break;
1697
1698 case VMXNET3_CMD_GET_PERM_MAC_HI:
1699 ret = vmxnet3_get_mac_high(&s->perm_mac);
1700 break;
1701
1702 case VMXNET3_CMD_GET_CONF_INTR:
1703 ret = vmxnet3_get_interrupt_config(s);
1704 break;
1705
1706 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1707 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1708 break;
1709
1710 case VMXNET3_CMD_GET_DID_LO:
1711 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1712 break;
1713
1714 case VMXNET3_CMD_GET_DID_HI:
1715 ret = VMXNET3_DEVICE_REVISION;
1716 break;
1717
1718 default:
1719 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1720 ret = 0;
1721 break;
1722 }
1723
1724 return ret;
1725 }
1726
1727 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1728 {
1729 uint32_t events;
1730 PCIDevice *d = PCI_DEVICE(s);
1731
1732 VMW_CBPRN("Setting events: 0x%x", val);
1733 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val;
1734 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1735 }
1736
1737 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1738 {
1739 PCIDevice *d = PCI_DEVICE(s);
1740 uint32_t events;
1741
1742 VMW_CBPRN("Clearing events: 0x%x", val);
1743 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val;
1744 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1745 }
1746
1747 static void
1748 vmxnet3_io_bar1_write(void *opaque,
1749 hwaddr addr,
1750 uint64_t val,
1751 unsigned size)
1752 {
1753 VMXNET3State *s = opaque;
1754
1755 switch (addr) {
1756 /* Vmxnet3 Revision Report Selection */
1757 case VMXNET3_REG_VRRS:
1758 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1759 val, size);
1760 break;
1761
1762 /* UPT Version Report Selection */
1763 case VMXNET3_REG_UVRS:
1764 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1765 val, size);
1766 break;
1767
1768 /* Driver Shared Address Low */
1769 case VMXNET3_REG_DSAL:
1770 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1771 val, size);
1772 /*
1773 * Guest driver will first write the low part of the shared
1774 * memory address. We save it to temp variable and set the
1775 * shared address only after we get the high part
1776 */
1777 if (val == 0) {
1778 vmxnet3_deactivate_device(s);
1779 }
1780 s->temp_shared_guest_driver_memory = val;
1781 s->drv_shmem = 0;
1782 break;
1783
1784 /* Driver Shared Address High */
1785 case VMXNET3_REG_DSAH:
1786 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1787 val, size);
1788 /*
1789 * Set the shared memory between guest driver and device.
1790 * We already should have low address part.
1791 */
1792 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1793 break;
1794
1795 /* Command */
1796 case VMXNET3_REG_CMD:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1798 val, size);
1799 vmxnet3_handle_command(s, val);
1800 break;
1801
1802 /* MAC Address Low */
1803 case VMXNET3_REG_MACL:
1804 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1805 val, size);
1806 s->temp_mac = val;
1807 break;
1808
1809 /* MAC Address High */
1810 case VMXNET3_REG_MACH:
1811 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1812 val, size);
1813 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1814 break;
1815
1816 /* Interrupt Cause Register */
1817 case VMXNET3_REG_ICR:
1818 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1819 val, size);
1820 qemu_log_mask(LOG_GUEST_ERROR,
1821 "%s: write to read-only register VMXNET3_REG_ICR\n",
1822 TYPE_VMXNET3);
1823 break;
1824
1825 /* Event Cause Register */
1826 case VMXNET3_REG_ECR:
1827 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1828 val, size);
1829 vmxnet3_ack_events(s, val);
1830 break;
1831
1832 default:
1833 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1834 addr, val, size);
1835 break;
1836 }
1837 }
1838
1839 static uint64_t
1840 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1841 {
1842 VMXNET3State *s = opaque;
1843 uint64_t ret = 0;
1844
1845 switch (addr) {
1846 /* Vmxnet3 Revision Report Selection */
1847 case VMXNET3_REG_VRRS:
1848 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1849 ret = VMXNET3_DEVICE_REVISION;
1850 break;
1851
1852 /* UPT Version Report Selection */
1853 case VMXNET3_REG_UVRS:
1854 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1855 ret = VMXNET3_UPT_REVISION;
1856 break;
1857
1858 /* Command */
1859 case VMXNET3_REG_CMD:
1860 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1861 ret = vmxnet3_get_command_status(s);
1862 break;
1863
1864 /* MAC Address Low */
1865 case VMXNET3_REG_MACL:
1866 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1867 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1868 break;
1869
1870 /* MAC Address High */
1871 case VMXNET3_REG_MACH:
1872 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1873 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1874 break;
1875
1876 /*
1877 * Interrupt Cause Register
1878 * Used for legacy interrupts only so interrupt index always 0
1879 */
1880 case VMXNET3_REG_ICR:
1881 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1882 if (vmxnet3_interrupt_asserted(s, 0)) {
1883 vmxnet3_clear_interrupt(s, 0);
1884 ret = true;
1885 } else {
1886 ret = false;
1887 }
1888 break;
1889
1890 default:
1891 VMW_CBPRN("Unknown read BAR1[%" PRIx64 "], %d bytes", addr, size);
1892 break;
1893 }
1894
1895 return ret;
1896 }
1897
1898 static int
1899 vmxnet3_can_receive(NetClientState *nc)
1900 {
1901 VMXNET3State *s = qemu_get_nic_opaque(nc);
1902 return s->device_active &&
1903 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1904 }
1905
1906 static inline bool
1907 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1908 {
1909 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1910 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1911 return true;
1912 }
1913
1914 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1915 }
1916
1917 static bool
1918 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1919 {
1920 int i;
1921 for (i = 0; i < s->mcast_list_len; i++) {
1922 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1923 return true;
1924 }
1925 }
1926 return false;
1927 }
1928
1929 static bool
1930 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1931 size_t size)
1932 {
1933 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1934
1935 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1936 return true;
1937 }
1938
1939 if (!vmxnet3_is_registered_vlan(s, data)) {
1940 return false;
1941 }
1942
1943 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
1944 case ETH_PKT_UCAST:
1945 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1946 return false;
1947 }
1948 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1949 return false;
1950 }
1951 break;
1952
1953 case ETH_PKT_BCAST:
1954 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1955 return false;
1956 }
1957 break;
1958
1959 case ETH_PKT_MCAST:
1960 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1961 return true;
1962 }
1963 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1964 return false;
1965 }
1966 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1967 return false;
1968 }
1969 break;
1970
1971 default:
1972 g_assert_not_reached();
1973 }
1974
1975 return true;
1976 }
1977
1978 static ssize_t
1979 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1980 {
1981 VMXNET3State *s = qemu_get_nic_opaque(nc);
1982 size_t bytes_indicated;
1983
1984 if (!vmxnet3_can_receive(nc)) {
1985 VMW_PKPRN("Cannot receive now");
1986 return -1;
1987 }
1988
1989 if (s->peer_has_vhdr) {
1990 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1991 buf += sizeof(struct virtio_net_hdr);
1992 size -= sizeof(struct virtio_net_hdr);
1993 }
1994
1995 net_rx_pkt_set_packet_type(s->rx_pkt,
1996 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1997
1998 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
1999 struct iovec iov = {
2000 .iov_base = (void *)buf,
2001 .iov_len = size
2002 };
2003
2004 net_rx_pkt_set_protocols(s->rx_pkt, &iov, 1, 0);
2005 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
2006 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
2007 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2008 if (bytes_indicated < size) {
2009 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
2010 }
2011 } else {
2012 VMW_PKPRN("Packet dropped by RX filter");
2013 bytes_indicated = size;
2014 }
2015
2016 assert(size > 0);
2017 assert(bytes_indicated != 0);
2018 return bytes_indicated;
2019 }
2020
2021 static void vmxnet3_set_link_status(NetClientState *nc)
2022 {
2023 VMXNET3State *s = qemu_get_nic_opaque(nc);
2024
2025 if (nc->link_down) {
2026 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2027 } else {
2028 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2029 }
2030
2031 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2032 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2033 }
2034
2035 static NetClientInfo net_vmxnet3_info = {
2036 .type = NET_CLIENT_DRIVER_NIC,
2037 .size = sizeof(NICState),
2038 .receive = vmxnet3_receive,
2039 .link_status_changed = vmxnet3_set_link_status,
2040 };
2041
2042 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2043 {
2044 NetClientState *nc = qemu_get_queue(s->nic);
2045
2046 if (qemu_has_vnet_hdr(nc->peer)) {
2047 return true;
2048 }
2049
2050 return false;
2051 }
2052
2053 static void vmxnet3_net_uninit(VMXNET3State *s)
2054 {
2055 g_free(s->mcast_list);
2056 vmxnet3_deactivate_device(s);
2057 qemu_del_nic(s->nic);
2058 }
2059
2060 static void vmxnet3_net_init(VMXNET3State *s)
2061 {
2062 DeviceState *d = DEVICE(s);
2063
2064 VMW_CBPRN("vmxnet3_net_init called...");
2065
2066 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2067
2068 /* Windows guest will query the address that was set on init */
2069 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2070
2071 s->mcast_list = NULL;
2072 s->mcast_list_len = 0;
2073
2074 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2075
2076 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
2077
2078 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2079 object_get_typename(OBJECT(s)),
2080 d->id, &d->mem_reentrancy_guard, s);
2081
2082 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2083 s->tx_sop = true;
2084 s->skip_current_tx_pkt = false;
2085 s->tx_pkt = NULL;
2086 s->rx_pkt = NULL;
2087 s->rx_vlan_stripping = false;
2088 s->lro_supported = false;
2089
2090 if (s->peer_has_vhdr) {
2091 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2092 sizeof(struct virtio_net_hdr));
2093 }
2094
2095 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2096 }
2097
2098 static void
2099 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2100 {
2101 PCIDevice *d = PCI_DEVICE(s);
2102 int i;
2103 for (i = 0; i < num_vectors; i++) {
2104 msix_vector_unuse(d, i);
2105 }
2106 }
2107
2108 static void
2109 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2110 {
2111 PCIDevice *d = PCI_DEVICE(s);
2112 int i;
2113 for (i = 0; i < num_vectors; i++) {
2114 msix_vector_use(d, i);
2115 }
2116 }
2117
2118 static bool
2119 vmxnet3_init_msix(VMXNET3State *s)
2120 {
2121 PCIDevice *d = PCI_DEVICE(s);
2122 int res = msix_init(d, VMXNET3_MAX_INTRS,
2123 &s->msix_bar,
2124 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2125 &s->msix_bar,
2126 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
2127 VMXNET3_MSIX_OFFSET, NULL);
2128
2129 if (0 > res) {
2130 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2131 s->msix_used = false;
2132 } else {
2133 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2134 s->msix_used = true;
2135 }
2136 return s->msix_used;
2137 }
2138
2139 static void
2140 vmxnet3_cleanup_msix(VMXNET3State *s)
2141 {
2142 PCIDevice *d = PCI_DEVICE(s);
2143
2144 if (s->msix_used) {
2145 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2146 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2147 }
2148 }
2149
2150 static void
2151 vmxnet3_cleanup_msi(VMXNET3State *s)
2152 {
2153 PCIDevice *d = PCI_DEVICE(s);
2154
2155 msi_uninit(d);
2156 }
2157
2158 static const MemoryRegionOps b0_ops = {
2159 .read = vmxnet3_io_bar0_read,
2160 .write = vmxnet3_io_bar0_write,
2161 .endianness = DEVICE_LITTLE_ENDIAN,
2162 .impl = {
2163 .min_access_size = 4,
2164 .max_access_size = 4,
2165 },
2166 };
2167
2168 static const MemoryRegionOps b1_ops = {
2169 .read = vmxnet3_io_bar1_read,
2170 .write = vmxnet3_io_bar1_write,
2171 .endianness = DEVICE_LITTLE_ENDIAN,
2172 .impl = {
2173 .min_access_size = 4,
2174 .max_access_size = 4,
2175 },
2176 };
2177
2178 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s)
2179 {
2180 uint64_t dsn_payload;
2181 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2182
2183 dsnp[0] = 0xfe;
2184 dsnp[1] = s->conf.macaddr.a[3];
2185 dsnp[2] = s->conf.macaddr.a[4];
2186 dsnp[3] = s->conf.macaddr.a[5];
2187 dsnp[4] = s->conf.macaddr.a[0];
2188 dsnp[5] = s->conf.macaddr.a[1];
2189 dsnp[6] = s->conf.macaddr.a[2];
2190 dsnp[7] = 0xff;
2191 return dsn_payload;
2192 }
2193
2194
2195 #define VMXNET3_USE_64BIT (true)
2196 #define VMXNET3_PER_VECTOR_MASK (false)
2197
2198 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2199 {
2200 VMXNET3State *s = VMXNET3(pci_dev);
2201 int ret;
2202
2203 VMW_CBPRN("Starting init...");
2204
2205 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2206 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2207 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2208 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2209
2210 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2211 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2212 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2213 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2214
2215 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2216 VMXNET3_MSIX_BAR_SIZE);
2217 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2218 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2219
2220 vmxnet3_reset_interrupt_states(s);
2221
2222 /* Interrupt pin A */
2223 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2224
2225 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
2226 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
2227 /* Any error other than -ENOTSUP(board's MSI support is broken)
2228 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2229 assert(!ret || ret == -ENOTSUP);
2230
2231 if (!vmxnet3_init_msix(s)) {
2232 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2233 }
2234
2235 vmxnet3_net_init(s);
2236
2237 if (pci_is_express(pci_dev)) {
2238 if (pci_bus_is_express(pci_get_bus(pci_dev))) {
2239 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2240 }
2241
2242 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
2243 vmxnet3_device_serial_num(s));
2244 }
2245 }
2246
2247 static void vmxnet3_instance_init(Object *obj)
2248 {
2249 VMXNET3State *s = VMXNET3(obj);
2250 device_add_bootindex_property(obj, &s->conf.bootindex,
2251 "bootindex", "/ethernet-phy@0",
2252 DEVICE(obj));
2253 PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
2254 }
2255
2256 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2257 {
2258 VMXNET3State *s = VMXNET3(pci_dev);
2259
2260 VMW_CBPRN("Starting uninit...");
2261
2262 vmxnet3_net_uninit(s);
2263
2264 vmxnet3_cleanup_msix(s);
2265
2266 vmxnet3_cleanup_msi(s);
2267 }
2268
2269 static void vmxnet3_qdev_reset(DeviceState *dev)
2270 {
2271 PCIDevice *d = PCI_DEVICE(dev);
2272 VMXNET3State *s = VMXNET3(d);
2273
2274 VMW_CBPRN("Starting QDEV reset...");
2275 vmxnet3_reset(s);
2276 }
2277
2278 static bool vmxnet3_mc_list_needed(void *opaque)
2279 {
2280 return true;
2281 }
2282
2283 static int vmxnet3_mcast_list_pre_load(void *opaque)
2284 {
2285 VMXNET3State *s = opaque;
2286
2287 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2288
2289 return 0;
2290 }
2291
2292
2293 static int vmxnet3_pre_save(void *opaque)
2294 {
2295 VMXNET3State *s = opaque;
2296
2297 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2298
2299 return 0;
2300 }
2301
2302 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2303 .name = "vmxnet3/mcast_list",
2304 .version_id = 1,
2305 .minimum_version_id = 1,
2306 .pre_load = vmxnet3_mcast_list_pre_load,
2307 .needed = vmxnet3_mc_list_needed,
2308 .fields = (const VMStateField[]) {
2309 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL,
2310 mcast_list_buff_size),
2311 VMSTATE_END_OF_LIST()
2312 }
2313 };
2314
2315 static const VMStateDescription vmstate_vmxnet3_ring = {
2316 .name = "vmxnet3-ring",
2317 .version_id = 0,
2318 .fields = (const VMStateField[]) {
2319 VMSTATE_UINT64(pa, Vmxnet3Ring),
2320 VMSTATE_UINT32(size, Vmxnet3Ring),
2321 VMSTATE_UINT32(cell_size, Vmxnet3Ring),
2322 VMSTATE_UINT32(next, Vmxnet3Ring),
2323 VMSTATE_UINT8(gen, Vmxnet3Ring),
2324 VMSTATE_END_OF_LIST()
2325 }
2326 };
2327
2328 static const VMStateDescription vmstate_vmxnet3_tx_stats = {
2329 .name = "vmxnet3-tx-stats",
2330 .version_id = 0,
2331 .fields = (const VMStateField[]) {
2332 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats),
2333 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats),
2334 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats),
2335 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats),
2336 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats),
2337 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats),
2338 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats),
2339 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats),
2340 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats),
2341 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats),
2342 VMSTATE_END_OF_LIST()
2343 }
2344 };
2345
2346 static const VMStateDescription vmstate_vmxnet3_txq_descr = {
2347 .name = "vmxnet3-txq-descr",
2348 .version_id = 0,
2349 .fields = (const VMStateField[]) {
2350 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2351 Vmxnet3Ring),
2352 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2353 Vmxnet3Ring),
2354 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr),
2355 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr),
2356 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats,
2357 struct UPT1_TxStats),
2358 VMSTATE_END_OF_LIST()
2359 }
2360 };
2361
2362 static const VMStateDescription vmstate_vmxnet3_rx_stats = {
2363 .name = "vmxnet3-rx-stats",
2364 .version_id = 0,
2365 .fields = (const VMStateField[]) {
2366 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats),
2367 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats),
2368 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats),
2369 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats),
2370 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats),
2371 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats),
2372 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats),
2373 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats),
2374 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats),
2375 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats),
2376 VMSTATE_END_OF_LIST()
2377 }
2378 };
2379
2380 static const VMStateDescription vmstate_vmxnet3_rxq_descr = {
2381 .name = "vmxnet3-rxq-descr",
2382 .version_id = 0,
2383 .fields = (const VMStateField[]) {
2384 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr,
2385 VMXNET3_RX_RINGS_PER_QUEUE, 0,
2386 vmstate_vmxnet3_ring, Vmxnet3Ring),
2387 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring,
2388 Vmxnet3Ring),
2389 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr),
2390 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr),
2391 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats,
2392 struct UPT1_RxStats),
2393 VMSTATE_END_OF_LIST()
2394 }
2395 };
2396
2397 static int vmxnet3_post_load(void *opaque, int version_id)
2398 {
2399 VMXNET3State *s = opaque;
2400
2401 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
2402 net_rx_pkt_init(&s->rx_pkt);
2403
2404 if (s->msix_used) {
2405 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2406 }
2407
2408 if (!vmxnet3_validate_queues(s)) {
2409 return -1;
2410 }
2411 if (!vmxnet3_validate_interrupts(s)) {
2412 return -1;
2413 }
2414
2415 return 0;
2416 }
2417
2418 static const VMStateDescription vmstate_vmxnet3_int_state = {
2419 .name = "vmxnet3-int-state",
2420 .version_id = 0,
2421 .fields = (const VMStateField[]) {
2422 VMSTATE_BOOL(is_masked, Vmxnet3IntState),
2423 VMSTATE_BOOL(is_pending, Vmxnet3IntState),
2424 VMSTATE_BOOL(is_asserted, Vmxnet3IntState),
2425 VMSTATE_END_OF_LIST()
2426 }
2427 };
2428
2429 static const VMStateDescription vmstate_vmxnet3 = {
2430 .name = "vmxnet3",
2431 .version_id = 1,
2432 .minimum_version_id = 1,
2433 .pre_save = vmxnet3_pre_save,
2434 .post_load = vmxnet3_post_load,
2435 .fields = (const VMStateField[]) {
2436 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2437 VMSTATE_MSIX(parent_obj, VMXNET3State),
2438 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2439 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2440 VMSTATE_BOOL(lro_supported, VMXNET3State),
2441 VMSTATE_UINT32(rx_mode, VMXNET3State),
2442 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2443 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2444 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2445 VMSTATE_UINT32(mtu, VMXNET3State),
2446 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2447 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2448 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2449 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2450 VMSTATE_UINT8(txq_num, VMXNET3State),
2451 VMSTATE_UINT8(rxq_num, VMXNET3State),
2452 VMSTATE_UINT32(device_active, VMXNET3State),
2453 VMSTATE_UINT32(last_command, VMXNET3State),
2454 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2455 VMSTATE_UINT32(temp_mac, VMXNET3State),
2456 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2457 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2458
2459 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State,
2460 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr,
2461 Vmxnet3TxqDescr),
2462 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State,
2463 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr,
2464 Vmxnet3RxqDescr),
2465 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State,
2466 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state,
2467 Vmxnet3IntState),
2468
2469 VMSTATE_END_OF_LIST()
2470 },
2471 .subsections = (const VMStateDescription * const []) {
2472 &vmxstate_vmxnet3_mcast_list,
2473 NULL
2474 }
2475 };
2476
2477 static const Property vmxnet3_properties[] = {
2478 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2479 };
2480
2481 static void vmxnet3_class_init(ObjectClass *class, const void *data)
2482 {
2483 DeviceClass *dc = DEVICE_CLASS(class);
2484 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2485
2486 c->realize = vmxnet3_pci_realize;
2487 c->exit = vmxnet3_pci_uninit;
2488 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2489 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2490 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2491 c->romfile = "efi-vmxnet3.rom";
2492 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2493 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2494 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2495 dc->desc = "VMWare Paravirtualized Ethernet v3";
2496 device_class_set_legacy_reset(dc, vmxnet3_qdev_reset);
2497 dc->vmsd = &vmstate_vmxnet3;
2498 device_class_set_props(dc, vmxnet3_properties);
2499 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2500 }
2501
2502 static const TypeInfo vmxnet3_info = {
2503 .name = TYPE_VMXNET3,
2504 .parent = TYPE_PCI_DEVICE,
2505 .class_size = sizeof(VMXNET3Class),
2506 .instance_size = sizeof(VMXNET3State),
2507 .class_init = vmxnet3_class_init,
2508 .instance_init = vmxnet3_instance_init,
2509 .interfaces = (const InterfaceInfo[]) {
2510 { INTERFACE_PCIE_DEVICE },
2511 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2512 { }
2513 },
2514 };
2515
2516 static void vmxnet3_register_types(void)
2517 {
2518 VMW_CBPRN("vmxnet3_register_types called...");
2519 type_register_static(&vmxnet3_info);
2520 }
2521
2522 type_init(vmxnet3_register_types)