| 1 | /* |
| 2 | * QEMU model of Xilinx AXI-Ethernet. |
| 3 | * |
| 4 | * Copyright (c) 2011 Edgar E. Iglesias. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/core/hw-error.h" |
| 27 | #include "hw/core/sysbus.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "qemu/log.h" |
| 30 | #include "qemu/module.h" |
| 31 | #include "net/net.h" |
| 32 | #include "net/checksum.h" |
| 33 | |
| 34 | #include "hw/core/irq.h" |
| 35 | #include "hw/core/qdev-properties.h" |
| 36 | #include "hw/core/stream.h" |
| 37 | #include "qom/object.h" |
| 38 | |
| 39 | #define DPHY(x) |
| 40 | |
| 41 | #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" |
| 42 | #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" |
| 43 | #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" |
| 44 | |
| 45 | OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET) |
| 46 | |
| 47 | typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink; |
| 48 | DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM, |
| 49 | TYPE_XILINX_AXI_ENET_DATA_STREAM) |
| 50 | |
| 51 | DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_CONTROL_STREAM, |
| 52 | TYPE_XILINX_AXI_ENET_CONTROL_STREAM) |
| 53 | |
| 54 | /* Advertisement control register. */ |
| 55 | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
| 56 | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
| 57 | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
| 58 | |
| 59 | #define CONTROL_PAYLOAD_WORDS 5 |
| 60 | #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) |
| 61 | |
| 62 | struct PHY { |
| 63 | uint32_t regs[32]; |
| 64 | |
| 65 | int link; |
| 66 | |
| 67 | unsigned int (*read)(struct PHY *phy, unsigned int req); |
| 68 | void (*write)(struct PHY *phy, unsigned int req, |
| 69 | unsigned int data); |
| 70 | }; |
| 71 | |
| 72 | static unsigned int tdk_read(struct PHY *phy, unsigned int req) |
| 73 | { |
| 74 | int regnum; |
| 75 | unsigned r = 0; |
| 76 | |
| 77 | regnum = req & 0x1f; |
| 78 | |
| 79 | switch (regnum) { |
| 80 | case 1: |
| 81 | if (!phy->link) { |
| 82 | break; |
| 83 | } |
| 84 | /* MR1. */ |
| 85 | /* Speeds and modes. */ |
| 86 | r |= (1 << 13) | (1 << 14); |
| 87 | r |= (1 << 11) | (1 << 12); |
| 88 | r |= (1 << 5); /* Autoneg complete. */ |
| 89 | r |= (1 << 3); /* Autoneg able. */ |
| 90 | r |= (1 << 2); /* link. */ |
| 91 | r |= (1 << 1); /* link. */ |
| 92 | break; |
| 93 | case 5: |
| 94 | /* Link partner ability. |
| 95 | We are kind; always agree with whatever best mode |
| 96 | the guest advertises. */ |
| 97 | r = 1 << 14; /* Success. */ |
| 98 | /* Copy advertised modes. */ |
| 99 | r |= phy->regs[4] & (15 << 5); |
| 100 | /* Autoneg support. */ |
| 101 | r |= 1; |
| 102 | break; |
| 103 | case 17: |
| 104 | /* Marvell PHY on many xilinx boards. */ |
| 105 | r = 0x8000; /* 1000Mb */ |
| 106 | if (phy->link) { |
| 107 | r |= 0x0400; /* Link is up */ |
| 108 | } |
| 109 | break; |
| 110 | case 18: |
| 111 | { |
| 112 | /* Diagnostics reg. */ |
| 113 | int duplex = 0; |
| 114 | int speed_100 = 0; |
| 115 | |
| 116 | if (!phy->link) { |
| 117 | break; |
| 118 | } |
| 119 | |
| 120 | /* Are we advertising 100 half or 100 duplex ? */ |
| 121 | speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); |
| 122 | speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); |
| 123 | |
| 124 | /* Are we advertising 10 duplex or 100 duplex ? */ |
| 125 | duplex = !!(phy->regs[4] & ADVERTISE_100FULL); |
| 126 | duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); |
| 127 | r = (speed_100 << 10) | (duplex << 11); |
| 128 | } |
| 129 | break; |
| 130 | |
| 131 | default: |
| 132 | r = phy->regs[regnum]; |
| 133 | break; |
| 134 | } |
| 135 | DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); |
| 136 | return r; |
| 137 | } |
| 138 | |
| 139 | static void |
| 140 | tdk_write(struct PHY *phy, unsigned int req, unsigned int data) |
| 141 | { |
| 142 | int regnum; |
| 143 | |
| 144 | regnum = req & 0x1f; |
| 145 | DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); |
| 146 | switch (regnum) { |
| 147 | case 2: |
| 148 | case 3: |
| 149 | /* Writes to PHY Identification registers are disallowed */ |
| 150 | break; |
| 151 | default: |
| 152 | phy->regs[regnum] = data; |
| 153 | break; |
| 154 | } |
| 155 | |
| 156 | /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ |
| 157 | phy->regs[0] &= ~0x8200; |
| 158 | } |
| 159 | |
| 160 | static void |
| 161 | tdk_init(struct PHY *phy) |
| 162 | { |
| 163 | phy->regs[0] = 0x3100; |
| 164 | /* PHY Id. */ |
| 165 | phy->regs[2] = 0x0300; |
| 166 | phy->regs[3] = 0xe400; |
| 167 | /* Autonegotiation advertisement reg. */ |
| 168 | phy->regs[4] = 0x01E1; |
| 169 | phy->link = 1; |
| 170 | |
| 171 | phy->read = tdk_read; |
| 172 | phy->write = tdk_write; |
| 173 | } |
| 174 | |
| 175 | struct MDIOBus { |
| 176 | struct PHY *devs[32]; |
| 177 | }; |
| 178 | |
| 179 | static void |
| 180 | mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
| 181 | { |
| 182 | bus->devs[addr & 0x1f] = phy; |
| 183 | } |
| 184 | |
| 185 | #ifdef USE_THIS_DEAD_CODE |
| 186 | static void |
| 187 | mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
| 188 | { |
| 189 | bus->devs[addr & 0x1f] = NULL; |
| 190 | } |
| 191 | #endif |
| 192 | |
| 193 | static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, |
| 194 | unsigned int reg) |
| 195 | { |
| 196 | struct PHY *phy; |
| 197 | uint16_t data; |
| 198 | |
| 199 | phy = bus->devs[addr]; |
| 200 | if (phy && phy->read) { |
| 201 | data = phy->read(phy, reg); |
| 202 | } else { |
| 203 | data = 0xffff; |
| 204 | } |
| 205 | DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); |
| 206 | return data; |
| 207 | } |
| 208 | |
| 209 | static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, |
| 210 | unsigned int reg, uint16_t data) |
| 211 | { |
| 212 | struct PHY *phy; |
| 213 | |
| 214 | DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); |
| 215 | phy = bus->devs[addr]; |
| 216 | if (phy && phy->write) { |
| 217 | phy->write(phy, reg, data); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | #define DENET(x) |
| 222 | |
| 223 | #define R_RAF (0x000 / 4) |
| 224 | enum { |
| 225 | RAF_MCAST_REJ = (1 << 1), |
| 226 | RAF_BCAST_REJ = (1 << 2), |
| 227 | RAF_EMCF_EN = (1 << 12), |
| 228 | RAF_NEWFUNC_EN = (1 << 11) |
| 229 | }; |
| 230 | |
| 231 | #define R_IS (0x00C / 4) |
| 232 | enum { |
| 233 | IS_HARD_ACCESS_COMPLETE = 1, |
| 234 | IS_AUTONEG = (1 << 1), |
| 235 | IS_RX_COMPLETE = (1 << 2), |
| 236 | IS_RX_REJECT = (1 << 3), |
| 237 | IS_TX_COMPLETE = (1 << 5), |
| 238 | IS_RX_DCM_LOCK = (1 << 6), |
| 239 | IS_MGM_RDY = (1 << 7), |
| 240 | IS_PHY_RST_DONE = (1 << 8), |
| 241 | }; |
| 242 | |
| 243 | #define R_IP (0x010 / 4) |
| 244 | #define R_IE (0x014 / 4) |
| 245 | #define R_UAWL (0x020 / 4) |
| 246 | #define R_UAWU (0x024 / 4) |
| 247 | #define R_PPST (0x030 / 4) |
| 248 | enum { |
| 249 | PPST_LINKSTATUS = (1 << 0), |
| 250 | PPST_PHY_LINKSTATUS = (1 << 7), |
| 251 | }; |
| 252 | |
| 253 | #define R_STATS_RX_BYTESL (0x200 / 4) |
| 254 | #define R_STATS_RX_BYTESH (0x204 / 4) |
| 255 | #define R_STATS_TX_BYTESL (0x208 / 4) |
| 256 | #define R_STATS_TX_BYTESH (0x20C / 4) |
| 257 | #define R_STATS_RXL (0x290 / 4) |
| 258 | #define R_STATS_RXH (0x294 / 4) |
| 259 | #define R_STATS_RX_BCASTL (0x2a0 / 4) |
| 260 | #define R_STATS_RX_BCASTH (0x2a4 / 4) |
| 261 | #define R_STATS_RX_MCASTL (0x2a8 / 4) |
| 262 | #define R_STATS_RX_MCASTH (0x2ac / 4) |
| 263 | |
| 264 | #define R_RCW0 (0x400 / 4) |
| 265 | #define R_RCW1 (0x404 / 4) |
| 266 | enum { |
| 267 | RCW1_VLAN = (1 << 27), |
| 268 | RCW1_RX = (1 << 28), |
| 269 | RCW1_FCS = (1 << 29), |
| 270 | RCW1_JUM = (1 << 30), |
| 271 | RCW1_RST = (1 << 31), |
| 272 | }; |
| 273 | |
| 274 | #define R_TC (0x408 / 4) |
| 275 | enum { |
| 276 | TC_VLAN = (1 << 27), |
| 277 | TC_TX = (1 << 28), |
| 278 | TC_FCS = (1 << 29), |
| 279 | TC_JUM = (1 << 30), |
| 280 | TC_RST = (1 << 31), |
| 281 | }; |
| 282 | |
| 283 | #define R_EMMC (0x410 / 4) |
| 284 | enum { |
| 285 | EMMC_LINKSPEED_10MB = (0 << 30), |
| 286 | EMMC_LINKSPEED_100MB = (1 << 30), |
| 287 | EMMC_LINKSPEED_1000MB = (2 << 30), |
| 288 | }; |
| 289 | |
| 290 | #define R_PHYC (0x414 / 4) |
| 291 | |
| 292 | #define R_MC (0x500 / 4) |
| 293 | #define MC_EN (1 << 6) |
| 294 | |
| 295 | #define R_MCR (0x504 / 4) |
| 296 | #define R_MWD (0x508 / 4) |
| 297 | #define R_MRD (0x50c / 4) |
| 298 | #define R_MIS (0x600 / 4) |
| 299 | #define R_MIP (0x620 / 4) |
| 300 | #define R_MIE (0x640 / 4) |
| 301 | #define R_MIC (0x640 / 4) |
| 302 | |
| 303 | #define R_UAW0 (0x700 / 4) |
| 304 | #define R_UAW1 (0x704 / 4) |
| 305 | #define R_FMI (0x708 / 4) |
| 306 | #define R_AF0 (0x710 / 4) |
| 307 | #define R_AF1 (0x714 / 4) |
| 308 | #define R_MAX (0x34 / 4) |
| 309 | |
| 310 | /* Indirect registers. */ |
| 311 | struct TEMAC { |
| 312 | struct MDIOBus mdio_bus; |
| 313 | struct PHY phy; |
| 314 | |
| 315 | void *parent; |
| 316 | }; |
| 317 | |
| 318 | |
| 319 | struct XilinxAXIEnetStreamSink { |
| 320 | Object parent; |
| 321 | |
| 322 | struct XilinxAXIEnet *enet; |
| 323 | } ; |
| 324 | |
| 325 | struct XilinxAXIEnet { |
| 326 | SysBusDevice busdev; |
| 327 | MemoryRegion iomem; |
| 328 | qemu_irq irq; |
| 329 | StreamSink *tx_data_dev; |
| 330 | StreamSink *tx_control_dev; |
| 331 | XilinxAXIEnetStreamSink rx_data_dev; |
| 332 | XilinxAXIEnetStreamSink rx_control_dev; |
| 333 | NICState *nic; |
| 334 | NICConf conf; |
| 335 | |
| 336 | |
| 337 | uint32_t c_rxmem; |
| 338 | uint32_t c_txmem; |
| 339 | uint32_t c_phyaddr; |
| 340 | |
| 341 | struct TEMAC TEMAC; |
| 342 | |
| 343 | /* MII regs. */ |
| 344 | union { |
| 345 | uint32_t regs[4]; |
| 346 | struct { |
| 347 | uint32_t mc; |
| 348 | uint32_t mcr; |
| 349 | uint32_t mwd; |
| 350 | uint32_t mrd; |
| 351 | }; |
| 352 | } mii; |
| 353 | |
| 354 | struct { |
| 355 | uint64_t rx_bytes; |
| 356 | uint64_t tx_bytes; |
| 357 | |
| 358 | uint64_t rx; |
| 359 | uint64_t rx_bcast; |
| 360 | uint64_t rx_mcast; |
| 361 | } stats; |
| 362 | |
| 363 | /* Receive configuration words. */ |
| 364 | uint32_t rcw[2]; |
| 365 | /* Transmit config. */ |
| 366 | uint32_t tc; |
| 367 | uint32_t emmc; |
| 368 | uint32_t phyc; |
| 369 | |
| 370 | /* Unicast Address Word. */ |
| 371 | uint32_t uaw[2]; |
| 372 | /* Unicast address filter used with extended mcast. */ |
| 373 | uint32_t ext_uaw[2]; |
| 374 | uint32_t fmi; |
| 375 | |
| 376 | uint32_t regs[R_MAX]; |
| 377 | |
| 378 | /* Multicast filter addrs. */ |
| 379 | uint32_t maddr[4][2]; |
| 380 | /* 32K x 1 lookup filter. */ |
| 381 | uint32_t ext_mtable[1024]; |
| 382 | |
| 383 | uint32_t hdr[CONTROL_PAYLOAD_WORDS]; |
| 384 | |
| 385 | uint8_t *txmem; |
| 386 | uint32_t txpos; |
| 387 | |
| 388 | uint8_t *rxmem; |
| 389 | uint32_t rxsize; |
| 390 | uint32_t rxpos; |
| 391 | |
| 392 | uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; |
| 393 | uint32_t rxappsize; |
| 394 | |
| 395 | /* Whether axienet_eth_rx_notify should flush incoming queue. */ |
| 396 | bool need_flush; |
| 397 | }; |
| 398 | |
| 399 | static void axienet_rx_reset(XilinxAXIEnet *s) |
| 400 | { |
| 401 | s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; |
| 402 | } |
| 403 | |
| 404 | static void axienet_tx_reset(XilinxAXIEnet *s) |
| 405 | { |
| 406 | s->tc = TC_JUM | TC_TX | TC_VLAN; |
| 407 | s->txpos = 0; |
| 408 | } |
| 409 | |
| 410 | static inline int axienet_rx_resetting(XilinxAXIEnet *s) |
| 411 | { |
| 412 | return s->rcw[1] & RCW1_RST; |
| 413 | } |
| 414 | |
| 415 | static inline int axienet_rx_enabled(XilinxAXIEnet *s) |
| 416 | { |
| 417 | return s->rcw[1] & RCW1_RX; |
| 418 | } |
| 419 | |
| 420 | static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) |
| 421 | { |
| 422 | return !!(s->regs[R_RAF] & RAF_EMCF_EN); |
| 423 | } |
| 424 | |
| 425 | static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) |
| 426 | { |
| 427 | return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); |
| 428 | } |
| 429 | |
| 430 | static void xilinx_axienet_reset(DeviceState *d) |
| 431 | { |
| 432 | XilinxAXIEnet *s = XILINX_AXI_ENET(d); |
| 433 | |
| 434 | axienet_rx_reset(s); |
| 435 | axienet_tx_reset(s); |
| 436 | |
| 437 | s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; |
| 438 | s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; |
| 439 | |
| 440 | s->emmc = EMMC_LINKSPEED_100MB; |
| 441 | } |
| 442 | |
| 443 | static void enet_update_irq(XilinxAXIEnet *s) |
| 444 | { |
| 445 | s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; |
| 446 | qemu_set_irq(s->irq, !!s->regs[R_IP]); |
| 447 | } |
| 448 | |
| 449 | static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) |
| 450 | { |
| 451 | XilinxAXIEnet *s = opaque; |
| 452 | uint32_t r = 0; |
| 453 | addr >>= 2; |
| 454 | |
| 455 | switch (addr) { |
| 456 | case R_RCW0: |
| 457 | case R_RCW1: |
| 458 | r = s->rcw[addr & 1]; |
| 459 | break; |
| 460 | |
| 461 | case R_TC: |
| 462 | r = s->tc; |
| 463 | break; |
| 464 | |
| 465 | case R_EMMC: |
| 466 | r = s->emmc; |
| 467 | break; |
| 468 | |
| 469 | case R_PHYC: |
| 470 | r = s->phyc; |
| 471 | break; |
| 472 | |
| 473 | case R_MCR: |
| 474 | r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ |
| 475 | break; |
| 476 | |
| 477 | case R_STATS_RX_BYTESL: |
| 478 | case R_STATS_RX_BYTESH: |
| 479 | r = s->stats.rx_bytes >> (32 * (addr & 1)); |
| 480 | break; |
| 481 | |
| 482 | case R_STATS_TX_BYTESL: |
| 483 | case R_STATS_TX_BYTESH: |
| 484 | r = s->stats.tx_bytes >> (32 * (addr & 1)); |
| 485 | break; |
| 486 | |
| 487 | case R_STATS_RXL: |
| 488 | case R_STATS_RXH: |
| 489 | r = s->stats.rx >> (32 * (addr & 1)); |
| 490 | break; |
| 491 | case R_STATS_RX_BCASTL: |
| 492 | case R_STATS_RX_BCASTH: |
| 493 | r = s->stats.rx_bcast >> (32 * (addr & 1)); |
| 494 | break; |
| 495 | case R_STATS_RX_MCASTL: |
| 496 | case R_STATS_RX_MCASTH: |
| 497 | r = s->stats.rx_mcast >> (32 * (addr & 1)); |
| 498 | break; |
| 499 | |
| 500 | case R_MC: |
| 501 | case R_MWD: |
| 502 | case R_MRD: |
| 503 | r = s->mii.regs[addr & 3]; |
| 504 | break; |
| 505 | |
| 506 | case R_UAW0: |
| 507 | case R_UAW1: |
| 508 | r = s->uaw[addr & 1]; |
| 509 | break; |
| 510 | |
| 511 | case R_UAWU: |
| 512 | case R_UAWL: |
| 513 | r = s->ext_uaw[addr & 1]; |
| 514 | break; |
| 515 | |
| 516 | case R_FMI: |
| 517 | r = s->fmi; |
| 518 | break; |
| 519 | |
| 520 | case R_AF0: |
| 521 | case R_AF1: |
| 522 | r = s->maddr[s->fmi & 3][addr & 1]; |
| 523 | break; |
| 524 | |
| 525 | case 0x8000 ... 0x83ff: |
| 526 | r = s->ext_mtable[addr - 0x8000]; |
| 527 | break; |
| 528 | |
| 529 | default: |
| 530 | if (addr < ARRAY_SIZE(s->regs)) { |
| 531 | r = s->regs[addr]; |
| 532 | } |
| 533 | DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n", |
| 534 | __func__, addr * 4, r)); |
| 535 | break; |
| 536 | } |
| 537 | return r; |
| 538 | } |
| 539 | |
| 540 | static void enet_write(void *opaque, hwaddr addr, |
| 541 | uint64_t value, unsigned size) |
| 542 | { |
| 543 | XilinxAXIEnet *s = opaque; |
| 544 | struct TEMAC *t = &s->TEMAC; |
| 545 | |
| 546 | addr >>= 2; |
| 547 | switch (addr) { |
| 548 | case R_RCW0: |
| 549 | case R_RCW1: |
| 550 | s->rcw[addr & 1] = value; |
| 551 | if ((addr & 1) && value & RCW1_RST) { |
| 552 | axienet_rx_reset(s); |
| 553 | } else { |
| 554 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 555 | } |
| 556 | break; |
| 557 | |
| 558 | case R_TC: |
| 559 | s->tc = value; |
| 560 | if (value & TC_RST) { |
| 561 | axienet_tx_reset(s); |
| 562 | } |
| 563 | break; |
| 564 | |
| 565 | case R_EMMC: |
| 566 | s->emmc = value; |
| 567 | break; |
| 568 | |
| 569 | case R_PHYC: |
| 570 | s->phyc = value; |
| 571 | break; |
| 572 | |
| 573 | case R_MC: |
| 574 | value &= ((1 << 7) - 1); |
| 575 | |
| 576 | /* Enable the MII. */ |
| 577 | if (value & MC_EN) { |
| 578 | unsigned int miiclkdiv = value & ((1 << 6) - 1); |
| 579 | if (!miiclkdiv) { |
| 580 | qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); |
| 581 | } |
| 582 | } |
| 583 | s->mii.mc = value; |
| 584 | break; |
| 585 | |
| 586 | case R_MCR: { |
| 587 | unsigned int phyaddr = (value >> 24) & 0x1f; |
| 588 | unsigned int regaddr = (value >> 16) & 0x1f; |
| 589 | unsigned int op = (value >> 14) & 3; |
| 590 | unsigned int initiate = (value >> 11) & 1; |
| 591 | |
| 592 | if (initiate) { |
| 593 | if (op == 1) { |
| 594 | mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); |
| 595 | } else if (op == 2) { |
| 596 | s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); |
| 597 | } else { |
| 598 | qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); |
| 599 | } |
| 600 | } |
| 601 | s->mii.mcr = value; |
| 602 | break; |
| 603 | } |
| 604 | |
| 605 | case R_MWD: |
| 606 | case R_MRD: |
| 607 | s->mii.regs[addr & 3] = value; |
| 608 | break; |
| 609 | |
| 610 | |
| 611 | case R_UAW0: |
| 612 | case R_UAW1: |
| 613 | s->uaw[addr & 1] = value; |
| 614 | break; |
| 615 | |
| 616 | case R_UAWL: |
| 617 | case R_UAWU: |
| 618 | s->ext_uaw[addr & 1] = value; |
| 619 | break; |
| 620 | |
| 621 | case R_FMI: |
| 622 | s->fmi = value; |
| 623 | break; |
| 624 | |
| 625 | case R_AF0: |
| 626 | case R_AF1: |
| 627 | s->maddr[s->fmi & 3][addr & 1] = value; |
| 628 | break; |
| 629 | |
| 630 | case R_IS: |
| 631 | s->regs[addr] &= ~value; |
| 632 | break; |
| 633 | |
| 634 | case 0x8000 ... 0x83ff: |
| 635 | s->ext_mtable[addr - 0x8000] = value; |
| 636 | break; |
| 637 | |
| 638 | default: |
| 639 | DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n", |
| 640 | __func__, addr * 4, (unsigned)value)); |
| 641 | if (addr < ARRAY_SIZE(s->regs)) { |
| 642 | s->regs[addr] = value; |
| 643 | } |
| 644 | break; |
| 645 | } |
| 646 | enet_update_irq(s); |
| 647 | } |
| 648 | |
| 649 | static const MemoryRegionOps enet_ops = { |
| 650 | .read = enet_read, |
| 651 | .write = enet_write, |
| 652 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 653 | }; |
| 654 | |
| 655 | static int eth_can_rx(XilinxAXIEnet *s) |
| 656 | { |
| 657 | /* RX enabled? */ |
| 658 | return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); |
| 659 | } |
| 660 | |
| 661 | static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) |
| 662 | { |
| 663 | int match = 1; |
| 664 | |
| 665 | if (memcmp(buf, &f0, 4)) { |
| 666 | match = 0; |
| 667 | } |
| 668 | |
| 669 | if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { |
| 670 | match = 0; |
| 671 | } |
| 672 | |
| 673 | return match; |
| 674 | } |
| 675 | |
| 676 | static void axienet_eth_rx_notify(void *opaque) |
| 677 | { |
| 678 | XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); |
| 679 | |
| 680 | while (s->rxappsize && stream_can_push(s->tx_control_dev, |
| 681 | axienet_eth_rx_notify, s)) { |
| 682 | size_t ret = stream_push(s->tx_control_dev, |
| 683 | (void *)s->rxapp + CONTROL_PAYLOAD_SIZE |
| 684 | - s->rxappsize, s->rxappsize, true); |
| 685 | s->rxappsize -= ret; |
| 686 | } |
| 687 | |
| 688 | while (s->rxsize && stream_can_push(s->tx_data_dev, |
| 689 | axienet_eth_rx_notify, s)) { |
| 690 | size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, |
| 691 | s->rxsize, true); |
| 692 | s->rxsize -= ret; |
| 693 | s->rxpos += ret; |
| 694 | if (!s->rxsize) { |
| 695 | s->regs[R_IS] |= IS_RX_COMPLETE; |
| 696 | if (s->need_flush) { |
| 697 | s->need_flush = false; |
| 698 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 699 | } |
| 700 | } |
| 701 | } |
| 702 | enet_update_irq(s); |
| 703 | } |
| 704 | |
| 705 | static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
| 706 | { |
| 707 | XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
| 708 | static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, |
| 709 | 0xff, 0xff, 0xff}; |
| 710 | static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; |
| 711 | uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; |
| 712 | int promisc = s->fmi & (1 << 31); |
| 713 | int unicast, broadcast, multicast, ip_multicast = 0; |
| 714 | uint32_t csum32; |
| 715 | uint16_t csum16; |
| 716 | int i; |
| 717 | |
| 718 | DENET(qemu_log("%s: %zd bytes\n", __func__, size)); |
| 719 | |
| 720 | if (!eth_can_rx(s)) { |
| 721 | s->need_flush = true; |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | unicast = ~buf[0] & 0x1; |
| 726 | broadcast = memcmp(buf, sa_bcast, 6) == 0; |
| 727 | multicast = !unicast && !broadcast; |
| 728 | if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { |
| 729 | ip_multicast = 1; |
| 730 | } |
| 731 | |
| 732 | /* Jumbo or vlan sizes ? */ |
| 733 | if (!(s->rcw[1] & RCW1_JUM)) { |
| 734 | if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { |
| 735 | return size; |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | /* Basic Address filters. If you want to use the extended filters |
| 740 | you'll generally have to place the ethernet mac into promiscuous mode |
| 741 | to avoid the basic filtering from dropping most frames. */ |
| 742 | if (!promisc) { |
| 743 | if (unicast) { |
| 744 | if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { |
| 745 | return size; |
| 746 | } |
| 747 | } else { |
| 748 | if (broadcast) { |
| 749 | /* Broadcast. */ |
| 750 | if (s->regs[R_RAF] & RAF_BCAST_REJ) { |
| 751 | return size; |
| 752 | } |
| 753 | } else { |
| 754 | int drop = 1; |
| 755 | |
| 756 | /* Multicast. */ |
| 757 | if (s->regs[R_RAF] & RAF_MCAST_REJ) { |
| 758 | return size; |
| 759 | } |
| 760 | |
| 761 | for (i = 0; i < 4; i++) { |
| 762 | if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { |
| 763 | drop = 0; |
| 764 | break; |
| 765 | } |
| 766 | } |
| 767 | |
| 768 | if (drop) { |
| 769 | return size; |
| 770 | } |
| 771 | } |
| 772 | } |
| 773 | } |
| 774 | |
| 775 | /* Extended mcast filtering enabled? */ |
| 776 | if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { |
| 777 | if (unicast) { |
| 778 | if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { |
| 779 | return size; |
| 780 | } |
| 781 | } else { |
| 782 | if (broadcast) { |
| 783 | /* Broadcast. ??? */ |
| 784 | if (s->regs[R_RAF] & RAF_BCAST_REJ) { |
| 785 | return size; |
| 786 | } |
| 787 | } else { |
| 788 | int idx, bit; |
| 789 | |
| 790 | /* Multicast. */ |
| 791 | if (!memcmp(buf, sa_ipmcast, 3)) { |
| 792 | return size; |
| 793 | } |
| 794 | |
| 795 | idx = (buf[4] & 0x7f) << 8; |
| 796 | idx |= buf[5]; |
| 797 | |
| 798 | bit = 1 << (idx & 0x1f); |
| 799 | idx >>= 5; |
| 800 | |
| 801 | if (!(s->ext_mtable[idx] & bit)) { |
| 802 | return size; |
| 803 | } |
| 804 | } |
| 805 | } |
| 806 | } |
| 807 | |
| 808 | if (size < 12) { |
| 809 | s->regs[R_IS] |= IS_RX_REJECT; |
| 810 | enet_update_irq(s); |
| 811 | return -1; |
| 812 | } |
| 813 | |
| 814 | if (size > (s->c_rxmem - 4)) { |
| 815 | size = s->c_rxmem - 4; |
| 816 | } |
| 817 | |
| 818 | memcpy(s->rxmem, buf, size); |
| 819 | memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ |
| 820 | |
| 821 | if (s->rcw[1] & RCW1_FCS) { |
| 822 | size += 4; /* fcs is inband. */ |
| 823 | } |
| 824 | |
| 825 | app[0] = 5 << 28; |
| 826 | csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); |
| 827 | /* Fold it once. */ |
| 828 | csum32 = (csum32 & 0xffff) + (csum32 >> 16); |
| 829 | /* And twice to get rid of possible carries. */ |
| 830 | csum16 = (csum32 & 0xffff) + (csum32 >> 16); |
| 831 | app[3] = csum16; |
| 832 | app[4] = size & 0xffff; |
| 833 | |
| 834 | s->stats.rx_bytes += size; |
| 835 | s->stats.rx++; |
| 836 | if (multicast) { |
| 837 | s->stats.rx_mcast++; |
| 838 | app[2] |= 1 | (ip_multicast << 1); |
| 839 | } else if (broadcast) { |
| 840 | s->stats.rx_bcast++; |
| 841 | app[2] |= 1 << 3; |
| 842 | } |
| 843 | |
| 844 | /* Good frame. */ |
| 845 | app[2] |= 1 << 6; |
| 846 | |
| 847 | s->rxsize = size; |
| 848 | s->rxpos = 0; |
| 849 | for (i = 0; i < ARRAY_SIZE(app); ++i) { |
| 850 | app[i] = cpu_to_le32(app[i]); |
| 851 | } |
| 852 | s->rxappsize = CONTROL_PAYLOAD_SIZE; |
| 853 | memcpy(s->rxapp, app, s->rxappsize); |
| 854 | axienet_eth_rx_notify(s); |
| 855 | |
| 856 | enet_update_irq(s); |
| 857 | return s->rxpos; |
| 858 | } |
| 859 | |
| 860 | static size_t |
| 861 | xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len, |
| 862 | bool eop) |
| 863 | { |
| 864 | int i; |
| 865 | XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); |
| 866 | XilinxAXIEnet *s = cs->enet; |
| 867 | |
| 868 | assert(eop); |
| 869 | if (len != CONTROL_PAYLOAD_SIZE) { |
| 870 | hw_error("AXI Enet requires %d byte control stream payload\n", |
| 871 | (int)CONTROL_PAYLOAD_SIZE); |
| 872 | } |
| 873 | |
| 874 | memcpy(s->hdr, buf, len); |
| 875 | |
| 876 | for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { |
| 877 | s->hdr[i] = le32_to_cpu(s->hdr[i]); |
| 878 | } |
| 879 | return len; |
| 880 | } |
| 881 | |
| 882 | static size_t |
| 883 | xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, |
| 884 | bool eop) |
| 885 | { |
| 886 | XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj); |
| 887 | XilinxAXIEnet *s = ds->enet; |
| 888 | |
| 889 | /* TX enable ? */ |
| 890 | if (!(s->tc & TC_TX)) { |
| 891 | return size; |
| 892 | } |
| 893 | |
| 894 | if (s->txpos + size > s->c_txmem) { |
| 895 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n", |
| 896 | TYPE_XILINX_AXI_ENET); |
| 897 | s->txpos = 0; |
| 898 | return size; |
| 899 | } |
| 900 | |
| 901 | if (s->txpos == 0 && eop) { |
| 902 | /* Fast path single fragment. */ |
| 903 | s->txpos = size; |
| 904 | } else { |
| 905 | memcpy(s->txmem + s->txpos, buf, size); |
| 906 | buf = s->txmem; |
| 907 | s->txpos += size; |
| 908 | |
| 909 | if (!eop) { |
| 910 | return size; |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | /* Jumbo or vlan sizes ? */ |
| 915 | if (!(s->tc & TC_JUM)) { |
| 916 | if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { |
| 917 | s->txpos = 0; |
| 918 | return size; |
| 919 | } |
| 920 | } |
| 921 | |
| 922 | if (s->hdr[0] & 1) { |
| 923 | unsigned int start_off = s->hdr[1] >> 16; |
| 924 | unsigned int write_off = s->hdr[1] & 0xffff; |
| 925 | |
| 926 | if (start_off > s->txpos || write_off + 2 > s->txpos) { |
| 927 | qemu_log_mask(LOG_GUEST_ERROR, |
| 928 | "%s: offsets outside packet, skipping checksum\n", |
| 929 | TYPE_XILINX_AXI_ENET); |
| 930 | } else { |
| 931 | uint32_t tmp_csum; |
| 932 | uint16_t csum; |
| 933 | |
| 934 | tmp_csum = net_checksum_add(s->txpos - start_off, |
| 935 | buf + start_off); |
| 936 | /* Accumulate the seed. */ |
| 937 | tmp_csum += s->hdr[2] & 0xffff; |
| 938 | |
| 939 | /* Fold the 32bit partial checksum. */ |
| 940 | csum = net_checksum_finish(tmp_csum); |
| 941 | |
| 942 | /* Writeback. */ |
| 943 | buf[write_off] = csum >> 8; |
| 944 | buf[write_off + 1] = csum & 0xff; |
| 945 | } |
| 946 | } |
| 947 | |
| 948 | qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); |
| 949 | |
| 950 | s->stats.tx_bytes += s->txpos; |
| 951 | s->regs[R_IS] |= IS_TX_COMPLETE; |
| 952 | enet_update_irq(s); |
| 953 | |
| 954 | s->txpos = 0; |
| 955 | return size; |
| 956 | } |
| 957 | |
| 958 | static NetClientInfo net_xilinx_enet_info = { |
| 959 | .type = NET_CLIENT_DRIVER_NIC, |
| 960 | .size = sizeof(NICState), |
| 961 | .receive = eth_rx, |
| 962 | }; |
| 963 | |
| 964 | static void xilinx_enet_realize(DeviceState *dev, Error **errp) |
| 965 | { |
| 966 | XilinxAXIEnet *s = XILINX_AXI_ENET(dev); |
| 967 | XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); |
| 968 | XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM( |
| 969 | &s->rx_control_dev); |
| 970 | |
| 971 | object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", |
| 972 | (Object **) &ds->enet, |
| 973 | object_property_allow_set_link, |
| 974 | OBJ_PROP_LINK_STRONG); |
| 975 | object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", |
| 976 | (Object **) &cs->enet, |
| 977 | object_property_allow_set_link, |
| 978 | OBJ_PROP_LINK_STRONG); |
| 979 | object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); |
| 980 | object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort); |
| 981 | |
| 982 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 983 | s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, |
| 984 | object_get_typename(OBJECT(dev)), dev->id, |
| 985 | &dev->mem_reentrancy_guard, s); |
| 986 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
| 987 | |
| 988 | tdk_init(&s->TEMAC.phy); |
| 989 | mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); |
| 990 | |
| 991 | s->TEMAC.parent = s; |
| 992 | |
| 993 | s->rxmem = g_malloc(s->c_rxmem); |
| 994 | s->txmem = g_malloc(s->c_txmem); |
| 995 | } |
| 996 | |
| 997 | static void xilinx_enet_init(Object *obj) |
| 998 | { |
| 999 | XilinxAXIEnet *s = XILINX_AXI_ENET(obj); |
| 1000 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 1001 | |
| 1002 | object_initialize_child(OBJECT(s), "axistream-connected-target", |
| 1003 | &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); |
| 1004 | object_initialize_child(OBJECT(s), "axistream-control-connected-target", |
| 1005 | &s->rx_control_dev, |
| 1006 | TYPE_XILINX_AXI_ENET_CONTROL_STREAM); |
| 1007 | sysbus_init_irq(sbd, &s->irq); |
| 1008 | |
| 1009 | memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); |
| 1010 | sysbus_init_mmio(sbd, &s->iomem); |
| 1011 | } |
| 1012 | |
| 1013 | static const Property xilinx_enet_properties[] = { |
| 1014 | DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), |
| 1015 | DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), |
| 1016 | DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), |
| 1017 | DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), |
| 1018 | DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, |
| 1019 | tx_data_dev, TYPE_STREAM_SINK, StreamSink *), |
| 1020 | DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, |
| 1021 | tx_control_dev, TYPE_STREAM_SINK, StreamSink *), |
| 1022 | }; |
| 1023 | |
| 1024 | static void xilinx_enet_class_init(ObjectClass *klass, const void *data) |
| 1025 | { |
| 1026 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1027 | |
| 1028 | dc->realize = xilinx_enet_realize; |
| 1029 | device_class_set_props(dc, xilinx_enet_properties); |
| 1030 | device_class_set_legacy_reset(dc, xilinx_axienet_reset); |
| 1031 | } |
| 1032 | |
| 1033 | static void xilinx_enet_control_stream_class_init(ObjectClass *klass, |
| 1034 | const void *data) |
| 1035 | { |
| 1036 | StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); |
| 1037 | |
| 1038 | ssc->push = xilinx_axienet_control_stream_push; |
| 1039 | } |
| 1040 | |
| 1041 | static void xilinx_enet_data_stream_class_init(ObjectClass *klass, |
| 1042 | const void *data) |
| 1043 | { |
| 1044 | StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); |
| 1045 | |
| 1046 | ssc->push = xilinx_axienet_data_stream_push; |
| 1047 | } |
| 1048 | |
| 1049 | static const TypeInfo xilinx_enet_info = { |
| 1050 | .name = TYPE_XILINX_AXI_ENET, |
| 1051 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1052 | .instance_size = sizeof(XilinxAXIEnet), |
| 1053 | .class_init = xilinx_enet_class_init, |
| 1054 | .instance_init = xilinx_enet_init, |
| 1055 | }; |
| 1056 | |
| 1057 | static const TypeInfo xilinx_enet_data_stream_info = { |
| 1058 | .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, |
| 1059 | .parent = TYPE_OBJECT, |
| 1060 | .instance_size = sizeof(XilinxAXIEnetStreamSink), |
| 1061 | .class_init = xilinx_enet_data_stream_class_init, |
| 1062 | .interfaces = (const InterfaceInfo[]) { |
| 1063 | { TYPE_STREAM_SINK }, |
| 1064 | { } |
| 1065 | } |
| 1066 | }; |
| 1067 | |
| 1068 | static const TypeInfo xilinx_enet_control_stream_info = { |
| 1069 | .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, |
| 1070 | .parent = TYPE_OBJECT, |
| 1071 | .instance_size = sizeof(XilinxAXIEnetStreamSink), |
| 1072 | .class_init = xilinx_enet_control_stream_class_init, |
| 1073 | .interfaces = (const InterfaceInfo[]) { |
| 1074 | { TYPE_STREAM_SINK }, |
| 1075 | { } |
| 1076 | } |
| 1077 | }; |
| 1078 | |
| 1079 | static void xilinx_enet_register_types(void) |
| 1080 | { |
| 1081 | type_register_static(&xilinx_enet_info); |
| 1082 | type_register_static(&xilinx_enet_data_stream_info); |
| 1083 | type_register_static(&xilinx_enet_control_stream_info); |
| 1084 | } |
| 1085 | |
| 1086 | type_init(xilinx_enet_register_types) |