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1 /*
2 * QEMU model of the Xilinx Ethernet Lite MAC.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2024 Linaro, Ltd
6 *
7 * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite
8 * LogiCORE IP XPS Ethernet Lite Media Access Controller
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qemu/module.h"
31 #include "qemu/bitops.h"
32 #include "qom/object.h"
33 #include "qapi/error.h"
34 #include "hw/core/sysbus.h"
35 #include "hw/core/irq.h"
36 #include "hw/core/qdev-properties.h"
37 #include "hw/core/qdev-properties-system.h"
38 #include "hw/misc/unimp.h"
39 #include "net/net.h"
40 #include "trace.h"
41
42 #define BUFSZ_MAX 0x07e4
43 #define A_MDIO_BASE 0x07e4
44 #define A_TX_BASE0 0x07f4
45 #define A_TX_BASE1 0x0ff4
46 #define A_RX_BASE0 0x17fc
47 #define A_RX_BASE1 0x1ffc
48
49 enum {
50 TX_LEN = 0,
51 TX_GIE = 1,
52 TX_CTRL = 2,
53 TX_MAX
54 };
55
56 enum {
57 RX_CTRL = 0,
58 RX_MAX
59 };
60
61 #define GIE_GIE 0x80000000
62
63 #define CTRL_I 0x8
64 #define CTRL_P 0x2
65 #define CTRL_S 0x1
66
67 typedef struct XlnxXpsEthLitePort {
68 MemoryRegion txio;
69 MemoryRegion rxio;
70 MemoryRegion txbuf;
71 MemoryRegion rxbuf;
72
73 struct {
74 uint32_t tx_len;
75 uint32_t tx_gie;
76 uint32_t tx_ctrl;
77
78 uint32_t rx_ctrl;
79 } reg;
80 } XlnxXpsEthLitePort;
81
82 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
83 OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE)
84
85 struct XlnxXpsEthLite
86 {
87 SysBusDevice parent_obj;
88
89 EndianMode model_endianness;
90 MemoryRegion container;
91 qemu_irq irq;
92 NICState *nic;
93 NICConf conf;
94
95 uint32_t c_tx_pingpong;
96 uint32_t c_rx_pingpong;
97 unsigned int port_index; /* dual port RAM index */
98
99 UnimplementedDeviceState rsvd;
100 UnimplementedDeviceState mdio;
101 XlnxXpsEthLitePort port[2];
102 };
103
104 static inline void eth_pulse_irq(XlnxXpsEthLite *s)
105 {
106 /* Only the first gie reg is active. */
107 if (s->port[0].reg.tx_gie & GIE_GIE) {
108 qemu_irq_pulse(s->irq);
109 }
110 }
111
112 static unsigned addr_to_port_index(hwaddr addr)
113 {
114 return extract64(addr, 11, 1);
115 }
116
117 static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
118 {
119 return memory_region_get_ram_ptr(&s->port[port_index].txbuf);
120 }
121
122 static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
123 {
124 return memory_region_get_ram_ptr(&s->port[port_index].rxbuf);
125 }
126
127 static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
128 {
129 XlnxXpsEthLite *s = opaque;
130 unsigned port_index = addr_to_port_index(addr);
131 uint32_t r = 0;
132
133 switch (addr >> 2) {
134 case TX_LEN:
135 r = s->port[port_index].reg.tx_len;
136 break;
137 case TX_GIE:
138 r = s->port[port_index].reg.tx_gie;
139 break;
140 case TX_CTRL:
141 r = s->port[port_index].reg.tx_ctrl;
142 break;
143 default:
144 g_assert_not_reached();
145 }
146
147 return r;
148 }
149
150 static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
151 unsigned int size)
152 {
153 XlnxXpsEthLite *s = opaque;
154 unsigned port_index = addr_to_port_index(addr);
155
156 switch (addr >> 2) {
157 case TX_LEN:
158 s->port[port_index].reg.tx_len = value;
159 break;
160 case TX_GIE:
161 s->port[port_index].reg.tx_gie = value;
162 break;
163 case TX_CTRL:
164 if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
165 uint32_t tx_size = s->port[port_index].reg.tx_len;
166
167 if (tx_size >= BUFSZ_MAX) {
168 trace_ethlite_pkt_tx_size_too_big(tx_size);
169 } else {
170 qemu_send_packet(qemu_get_queue(s->nic),
171 txbuf_ptr(s, port_index),
172 tx_size);
173 }
174 if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
175 eth_pulse_irq(s);
176 }
177 } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
178 memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6);
179 if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
180 eth_pulse_irq(s);
181 }
182 }
183 /*
184 * We are fast and get ready pretty much immediately
185 * so we actually never flip the S nor P bits to one.
186 */
187 s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S);
188 break;
189 default:
190 g_assert_not_reached();
191 }
192 }
193
194 static const MemoryRegionOps eth_porttx_ops[2] = {
195 [0 ... 1] = {
196 .read = port_tx_read,
197 .write = port_tx_write,
198 .impl = {
199 .min_access_size = 4,
200 .max_access_size = 4,
201 },
202 .valid = {
203 .min_access_size = 4,
204 .max_access_size = 4,
205 },
206 },
207 [0].endianness = DEVICE_LITTLE_ENDIAN,
208 [1].endianness = DEVICE_BIG_ENDIAN,
209 };
210
211 static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
212 {
213 XlnxXpsEthLite *s = opaque;
214 unsigned port_index = addr_to_port_index(addr);
215 uint32_t r = 0;
216
217 switch (addr >> 2) {
218 case RX_CTRL:
219 r = s->port[port_index].reg.rx_ctrl;
220 break;
221 default:
222 g_assert_not_reached();
223 }
224
225 return r;
226 }
227
228 static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
229 unsigned int size)
230 {
231 XlnxXpsEthLite *s = opaque;
232 unsigned port_index = addr_to_port_index(addr);
233
234 switch (addr >> 2) {
235 case RX_CTRL:
236 if (!(value & CTRL_S)) {
237 qemu_flush_queued_packets(qemu_get_queue(s->nic));
238 }
239 s->port[port_index].reg.rx_ctrl = value;
240 break;
241 default:
242 g_assert_not_reached();
243 }
244 }
245
246 static const MemoryRegionOps eth_portrx_ops[2] = {
247 [0 ... 1] = {
248 .read = port_rx_read,
249 .write = port_rx_write,
250 .impl = {
251 .min_access_size = 4,
252 .max_access_size = 4,
253 },
254 .valid = {
255 .min_access_size = 4,
256 .max_access_size = 4,
257 },
258 },
259 [0].endianness = DEVICE_LITTLE_ENDIAN,
260 [1].endianness = DEVICE_BIG_ENDIAN,
261 };
262
263 static bool eth_can_rx(NetClientState *nc)
264 {
265 XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
266
267 return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S);
268 }
269
270 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
271 {
272 XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
273 unsigned int port_index = s->port_index;
274
275 /* DA filter. */
276 if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
277 return size;
278
279 if (s->port[port_index].reg.rx_ctrl & CTRL_S) {
280 trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl);
281 return -1;
282 }
283
284 if (size >= BUFSZ_MAX) {
285 trace_ethlite_pkt_size_too_big(size);
286 return -1;
287 }
288 memcpy(rxbuf_ptr(s, port_index), buf, size);
289
290 s->port[port_index].reg.rx_ctrl |= CTRL_S;
291 if (s->port[port_index].reg.rx_ctrl & CTRL_I) {
292 eth_pulse_irq(s);
293 }
294
295 /* If c_rx_pingpong was set flip buffers. */
296 s->port_index ^= s->c_rx_pingpong;
297 return size;
298 }
299
300 static void xilinx_ethlite_reset(DeviceState *dev)
301 {
302 XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
303
304 s->port_index = 0;
305 }
306
307 static NetClientInfo net_xilinx_ethlite_info = {
308 .type = NET_CLIENT_DRIVER_NIC,
309 .size = sizeof(NICState),
310 .can_receive = eth_can_rx,
311 .receive = eth_rx,
312 };
313
314 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
315 {
316 XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
317 unsigned ops_index;
318
319 if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
320 error_setg(errp, TYPE_XILINX_ETHLITE " property 'endianness'"
321 " must be set to 'big' or 'little'");
322 return;
323 }
324 ops_index = s->model_endianness == ENDIAN_MODE_BIG ? 1 : 0;
325
326 memory_region_init(&s->container, OBJECT(dev),
327 "xlnx.xps-ethernetlite", 0x2000);
328
329 object_initialize_child(OBJECT(dev), "ethlite.reserved", &s->rsvd,
330 TYPE_UNIMPLEMENTED_DEVICE);
331 qdev_prop_set_string(DEVICE(&s->rsvd), "name", "ethlite.reserved");
332 qdev_prop_set_uint64(DEVICE(&s->rsvd), "size",
333 memory_region_size(&s->container));
334 sysbus_realize(SYS_BUS_DEVICE(&s->rsvd), &error_fatal);
335 memory_region_add_subregion_overlap(&s->container, 0,
336 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rsvd), 0),
337 -1);
338
339 object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
340 TYPE_UNIMPLEMENTED_DEVICE);
341 qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
342 qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
343 sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
344 memory_region_add_subregion(&s->container, A_MDIO_BASE,
345 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
346
347 for (unsigned i = 0; i < 2; i++) {
348 memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev),
349 i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf",
350 BUFSZ_MAX, &error_abort);
351 memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
352 memory_region_init_io(&s->port[i].txio, OBJECT(dev),
353 &eth_porttx_ops[ops_index], s,
354 i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
355 4 * TX_MAX);
356 memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
357 &s->port[i].txio);
358
359 memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev),
360 i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf",
361 BUFSZ_MAX, &error_abort);
362 memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
363 &s->port[i].rxbuf);
364 memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
365 &eth_portrx_ops[ops_index], s,
366 i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
367 4 * RX_MAX);
368 memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
369 &s->port[i].rxio);
370 }
371
372 qemu_macaddr_default_if_unset(&s->conf.macaddr);
373 s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
374 object_get_typename(OBJECT(dev)), dev->id,
375 &dev->mem_reentrancy_guard, s);
376 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
377 }
378
379 static void xilinx_ethlite_init(Object *obj)
380 {
381 XlnxXpsEthLite *s = XILINX_ETHLITE(obj);
382
383 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
384 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
385 }
386
387 static const Property xilinx_ethlite_properties[] = {
388 DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XlnxXpsEthLite, model_endianness),
389 DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
390 DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
391 DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),
392 };
393
394 static void xilinx_ethlite_class_init(ObjectClass *klass, const void *data)
395 {
396 DeviceClass *dc = DEVICE_CLASS(klass);
397
398 dc->realize = xilinx_ethlite_realize;
399 device_class_set_legacy_reset(dc, xilinx_ethlite_reset);
400 device_class_set_props(dc, xilinx_ethlite_properties);
401 }
402
403 static const TypeInfo xilinx_ethlite_types[] = {
404 {
405 .name = TYPE_XILINX_ETHLITE,
406 .parent = TYPE_SYS_BUS_DEVICE,
407 .instance_size = sizeof(XlnxXpsEthLite),
408 .instance_init = xilinx_ethlite_init,
409 .class_init = xilinx_ethlite_class_init,
410 },
411 };
412
413 DEFINE_TYPES(xilinx_ethlite_types)