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1 /*
2 * ASPEED OTP (One-Time Programmable) memory
3 *
4 * Copyright (C) 2025 Aspeed
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qapi/error.h"
12 #include "system/block-backend.h"
13 #include "hw/core/qdev-properties.h"
14 #include "hw/nvram/aspeed_otp.h"
15 #include "hw/nvram/trace.h"
16
17 static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
18 {
19 AspeedOTPState *s = opaque;
20 uint64_t val = 0;
21
22 memcpy(&val, s->storage + offset, size);
23
24 return val;
25 }
26
27 static bool valid_program_data(uint32_t otp_addr,
28 uint32_t value, uint32_t prog_bit)
29 {
30 uint32_t programmed_bits, has_programmable_bits;
31 bool is_odd = otp_addr & 1;
32
33 /*
34 * prog_bit uses 0s to indicate target bits to program:
35 * - if OTP word is even-indexed, programmed bits flip 0->1
36 * - if odd, bits flip 1->0
37 * Bit programming is one-way only and irreversible.
38 */
39 if (is_odd) {
40 programmed_bits = ~value & prog_bit;
41 } else {
42 programmed_bits = value & (~prog_bit);
43 }
44
45 /* If any bit can be programmed, accept the request */
46 has_programmable_bits = value ^ (~prog_bit);
47
48 if (programmed_bits) {
49 trace_aspeed_otp_prog_conflict(otp_addr, programmed_bits);
50 for (int i = 0; i < 32; ++i) {
51 if (programmed_bits & (1U << i)) {
52 trace_aspeed_otp_prog_bit(i);
53 }
54 }
55 }
56
57 return has_programmable_bits != 0;
58 }
59
60 static bool program_otpmem_data(void *opaque, hwaddr otp_offset,
61 uint32_t prog_bit, uint32_t *value)
62 {
63 AspeedOTPState *s = opaque;
64 uint32_t otp_addr = otp_offset >> 2;
65 bool is_odd = otp_addr & 1;
66
67 memcpy(value, s->storage + otp_offset, sizeof(uint32_t));
68
69 if (!valid_program_data(otp_addr, *value, prog_bit)) {
70 return false;
71 }
72
73 if (is_odd) {
74 *value &= ~prog_bit;
75 } else {
76 *value |= ~prog_bit;
77 }
78
79 return true;
80 }
81
82 static void aspeed_otp_write(void *opaque, hwaddr otp_offset,
83 uint64_t val, unsigned size)
84 {
85 AspeedOTPState *s = opaque;
86 uint32_t value;
87
88 if (!program_otpmem_data(s, otp_offset, val, &value)) {
89 qemu_log_mask(LOG_GUEST_ERROR,
90 "%s: Failed to program data, value = %x, bit = %"PRIx64"\n",
91 __func__, value, val);
92 return;
93 }
94
95 memcpy(s->storage + otp_offset, &value, size);
96
97 if (s->blk) {
98 if (blk_pwrite(s->blk, otp_offset, size, &value, 0) < 0) {
99 qemu_log_mask(LOG_GUEST_ERROR,
100 "%s: Failed to write %x to %"HWADDR_PRIx"\n",
101 __func__, value, otp_offset);
102
103 return;
104 }
105 }
106 trace_aspeed_otp_prog(otp_offset, val, value);
107 }
108
109 static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
110 {
111 uint32_t *p;
112 int i, num;
113 uint64_t perm;
114
115 if (s->blk) {
116 perm = BLK_PERM_CONSISTENT_READ |
117 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
118 if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
119 return false;
120 }
121 if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
122 error_setg(errp, "Failed to read the initial flash content");
123 return false;
124 }
125 } else {
126 num = s->size / sizeof(uint32_t);
127 p = (uint32_t *)s->storage;
128 for (i = 0; i < num; i++) {
129 p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
130 }
131 }
132 return true;
133 }
134
135 static const MemoryRegionOps aspeed_otp_ops = {
136 .read = aspeed_otp_read,
137 .write = aspeed_otp_write,
138 .endianness = DEVICE_LITTLE_ENDIAN,
139 .valid.min_access_size = 1,
140 .valid.max_access_size = 4,
141 .valid.unaligned = true,
142 .impl.unaligned = true
143 };
144
145 static void aspeed_otp_realize(DeviceState *dev, Error **errp)
146 {
147 AspeedOTPState *s = ASPEED_OTP(dev);
148
149 if (s->size == 0) {
150 error_setg(errp, "aspeed.otp: 'size' property must be set");
151 return;
152 }
153
154 s->storage = blk_blockalign(s->blk, s->size);
155
156 if (!aspeed_otp_init_storage(s, errp)) {
157 return;
158 }
159
160 memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
161 s, "aspeed.otp", s->size);
162 address_space_init(&s->as, &s->mmio, NULL);
163 }
164
165 static const Property aspeed_otp_properties[] = {
166 DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
167 DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk),
168 };
169
170 static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
171 {
172 DeviceClass *dc = DEVICE_CLASS(klass);
173 dc->realize = aspeed_otp_realize;
174 device_class_set_props(dc, aspeed_otp_properties);
175 }
176
177 static const TypeInfo aspeed_otp_types[] = {
178 {
179 .name = TYPE_ASPEED_OTP,
180 .parent = TYPE_DEVICE,
181 .instance_size = sizeof(AspeedOTPState),
182 .class_init = aspeed_otp_class_init,
183 }
184 };
185
186 DEFINE_TYPES(aspeed_otp_types)