| 1 | /* |
| 2 | * Emulated CXL Switch Downstream Port |
| 3 | * |
| 4 | * Copyright (c) 2022 Huawei Technologies. |
| 5 | * |
| 6 | * Based on xio3130_downstream.c |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | */ |
| 10 | |
| 11 | #include "qemu/osdep.h" |
| 12 | #include "qemu/log.h" |
| 13 | #include "hw/pci/msi.h" |
| 14 | #include "hw/pci/pcie.h" |
| 15 | #include "hw/pci/pcie_port.h" |
| 16 | #include "hw/pci-bridge/cxl_downstream_port.h" |
| 17 | #include "hw/core/qdev-properties.h" |
| 18 | #include "hw/core/qdev-properties-system.h" |
| 19 | #include "hw/cxl/cxl.h" |
| 20 | #include "hw/cxl/cxl_port.h" |
| 21 | #include "qapi/error.h" |
| 22 | |
| 23 | typedef struct CXLDownstreamPort { |
| 24 | /*< private >*/ |
| 25 | PCIESlot parent_obj; |
| 26 | |
| 27 | /*< public >*/ |
| 28 | CXLComponentState cxl_cstate; |
| 29 | CXLPhyPortPerst perst; |
| 30 | } CXLDownstreamPort; |
| 31 | |
| 32 | #define CXL_DOWNSTREAM_PORT_MSI_OFFSET 0x70 |
| 33 | #define CXL_DOWNSTREAM_PORT_MSI_NR_VECTOR 1 |
| 34 | #define CXL_DOWNSTREAM_PORT_EXP_OFFSET 0x90 |
| 35 | #define CXL_DOWNSTREAM_PORT_AER_OFFSET 0x100 |
| 36 | #define CXL_DOWNSTREAM_PORT_DVSEC_OFFSET \ |
| 37 | (CXL_DOWNSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF) |
| 38 | |
| 39 | static void latch_registers(CXLDownstreamPort *dsp) |
| 40 | { |
| 41 | uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; |
| 42 | uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask; |
| 43 | |
| 44 | cxl_component_register_init_common(reg_state, write_msk, |
| 45 | CXL2_DOWNSTREAM_PORT, true); |
| 46 | } |
| 47 | |
| 48 | /* TODO: Look at sharing this code across all CXL port types */ |
| 49 | static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr, |
| 50 | uint32_t val, int len) |
| 51 | { |
| 52 | CXLDownstreamPort *dsp = CXL_DSP(dev); |
| 53 | CXLComponentState *cxl_cstate = &dsp->cxl_cstate; |
| 54 | |
| 55 | if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { |
| 56 | uint8_t *reg = &dev->config[addr]; |
| 57 | addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob; |
| 58 | if (addr == PORT_CONTROL_OFFSET) { |
| 59 | if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) { |
| 60 | /* unmask SBR */ |
| 61 | qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); |
| 62 | } |
| 63 | if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) { |
| 64 | /* Alt Memory & ID Space Enable */ |
| 65 | qemu_log_mask(LOG_UNIMP, |
| 66 | "Alt Memory & ID space is not supported\n"); |
| 67 | |
| 68 | } |
| 69 | } |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | static void cxl_dsp_config_write(PCIDevice *d, uint32_t address, |
| 74 | uint32_t val, int len) |
| 75 | { |
| 76 | uint16_t slt_ctl, slt_sta; |
| 77 | |
| 78 | pcie_cap_slot_get(d, &slt_ctl, &slt_sta); |
| 79 | pci_bridge_write_config(d, address, val, len); |
| 80 | pcie_cap_flr_write_config(d, address, val, len); |
| 81 | pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); |
| 82 | pcie_aer_write_config(d, address, val, len); |
| 83 | |
| 84 | cxl_dsp_dvsec_write_config(d, address, val, len); |
| 85 | } |
| 86 | |
| 87 | CXLPhyPortPerst *cxl_dsp_get_perst(CXLDownstreamPort *dsp) |
| 88 | { |
| 89 | return &dsp->perst; |
| 90 | } |
| 91 | |
| 92 | static void cxl_dsp_reset(DeviceState *qdev) |
| 93 | { |
| 94 | PCIDevice *d = PCI_DEVICE(qdev); |
| 95 | CXLDownstreamPort *dsp = CXL_DSP(qdev); |
| 96 | |
| 97 | pcie_cap_deverr_reset(d); |
| 98 | pcie_cap_slot_reset(d); |
| 99 | pcie_cap_arifwd_reset(d); |
| 100 | pci_bridge_reset(qdev); |
| 101 | |
| 102 | latch_registers(dsp); |
| 103 | cxl_init_physical_port_control(&dsp->perst); |
| 104 | } |
| 105 | |
| 106 | static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) |
| 107 | { |
| 108 | PCIESlot *s = PCIE_SLOT(d); |
| 109 | uint8_t *dvsec; |
| 110 | |
| 111 | dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 }; |
| 112 | cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, |
| 113 | EXTENSIONS_PORT_DVSEC_LENGTH, |
| 114 | EXTENSIONS_PORT_DVSEC, |
| 115 | EXTENSIONS_PORT_DVSEC_REVID, dvsec); |
| 116 | |
| 117 | dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ |
| 118 | .cap = 0x27, /* Cache, IO, Mem, non-MLD */ |
| 119 | .ctrl = 0x02, /* IO always enabled */ |
| 120 | .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ |
| 121 | .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ |
| 122 | }; |
| 123 | cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, |
| 124 | PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH, |
| 125 | PCIE_FLEXBUS_PORT_DVSEC, |
| 126 | PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec); |
| 127 | |
| 128 | dvsec = (uint8_t *)&(CXLDVSECPortGPF){ |
| 129 | .rsvd = 0, |
| 130 | .phase1_ctrl = 1, /* 1μs timeout */ |
| 131 | .phase2_ctrl = 1, /* 1μs timeout */ |
| 132 | }; |
| 133 | cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, |
| 134 | GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC, |
| 135 | GPF_PORT_DVSEC_REVID, dvsec); |
| 136 | |
| 137 | dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){ |
| 138 | .rsvd = 0, |
| 139 | .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, |
| 140 | .reg0_base_hi = 0, |
| 141 | }; |
| 142 | cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, |
| 143 | REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC, |
| 144 | REG_LOC_DVSEC_REVID, dvsec); |
| 145 | } |
| 146 | |
| 147 | static void cxl_dsp_realize(PCIDevice *d, Error **errp) |
| 148 | { |
| 149 | PCIEPort *p = PCIE_PORT(d); |
| 150 | PCIESlot *s = PCIE_SLOT(d); |
| 151 | CXLDownstreamPort *dsp = CXL_DSP(d); |
| 152 | CXLComponentState *cxl_cstate = &dsp->cxl_cstate; |
| 153 | ComponentRegisters *cregs = &cxl_cstate->crb; |
| 154 | MemoryRegion *component_bar = &cregs->component_registers; |
| 155 | int rc; |
| 156 | |
| 157 | pci_bridge_initfn(d, TYPE_PCIE_BUS); |
| 158 | pcie_port_init_reg(d); |
| 159 | |
| 160 | rc = msi_init(d, CXL_DOWNSTREAM_PORT_MSI_OFFSET, |
| 161 | CXL_DOWNSTREAM_PORT_MSI_NR_VECTOR, |
| 162 | true, true, errp); |
| 163 | if (rc) { |
| 164 | assert(rc == -ENOTSUP); |
| 165 | goto err_bridge; |
| 166 | } |
| 167 | |
| 168 | rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, |
| 169 | PCI_EXP_TYPE_DOWNSTREAM, p->port, |
| 170 | errp); |
| 171 | if (rc < 0) { |
| 172 | goto err_msi; |
| 173 | } |
| 174 | |
| 175 | pcie_cap_flr_init(d); |
| 176 | pcie_cap_deverr_init(d); |
| 177 | pcie_cap_slot_init(d, s); |
| 178 | pcie_cap_arifwd_init(d); |
| 179 | |
| 180 | pcie_chassis_create(s->chassis); |
| 181 | rc = pcie_chassis_add_slot(s); |
| 182 | if (rc < 0) { |
| 183 | error_setg(errp, "Can't add chassis slot, error %d", rc); |
| 184 | goto err_pcie_cap; |
| 185 | } |
| 186 | |
| 187 | rc = pcie_aer_init(d, PCI_ERR_VER, CXL_DOWNSTREAM_PORT_AER_OFFSET, |
| 188 | PCI_ERR_SIZEOF, errp); |
| 189 | if (rc < 0) { |
| 190 | goto err_chassis; |
| 191 | } |
| 192 | |
| 193 | cxl_cstate->dvsec_offset = CXL_DOWNSTREAM_PORT_DVSEC_OFFSET; |
| 194 | cxl_cstate->pdev = d; |
| 195 | build_dvsecs(d, cxl_cstate); |
| 196 | cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_DSP); |
| 197 | pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, |
| 198 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 199 | PCI_BASE_ADDRESS_MEM_TYPE_64, |
| 200 | component_bar); |
| 201 | |
| 202 | return; |
| 203 | |
| 204 | err_chassis: |
| 205 | pcie_chassis_del_slot(s); |
| 206 | err_pcie_cap: |
| 207 | pcie_cap_exit(d); |
| 208 | err_msi: |
| 209 | msi_uninit(d); |
| 210 | err_bridge: |
| 211 | pci_bridge_exitfn(d); |
| 212 | } |
| 213 | |
| 214 | static void cxl_dsp_exitfn(PCIDevice *d) |
| 215 | { |
| 216 | PCIESlot *s = PCIE_SLOT(d); |
| 217 | |
| 218 | pcie_aer_exit(d); |
| 219 | pcie_chassis_del_slot(s); |
| 220 | pcie_cap_exit(d); |
| 221 | msi_uninit(d); |
| 222 | pci_bridge_exitfn(d); |
| 223 | } |
| 224 | |
| 225 | static const Property cxl_dsp_props[] = { |
| 226 | DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, |
| 227 | speed, PCIE_LINK_SPEED_64), |
| 228 | DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, |
| 229 | width, PCIE_LINK_WIDTH_16), |
| 230 | DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), |
| 231 | }; |
| 232 | |
| 233 | static void cxl_dsp_class_init(ObjectClass *oc, const void *data) |
| 234 | { |
| 235 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 236 | PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); |
| 237 | |
| 238 | device_class_set_props(dc, cxl_dsp_props); |
| 239 | k->config_write = cxl_dsp_config_write; |
| 240 | k->realize = cxl_dsp_realize; |
| 241 | k->exit = cxl_dsp_exitfn; |
| 242 | k->vendor_id = 0x19e5; /* Huawei */ |
| 243 | k->device_id = 0xa129; /* Emulated CXL Switch Downstream Port */ |
| 244 | k->revision = 0; |
| 245 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 246 | dc->desc = "CXL Switch Downstream Port"; |
| 247 | device_class_set_legacy_reset(dc, cxl_dsp_reset); |
| 248 | } |
| 249 | |
| 250 | static const TypeInfo cxl_dsp_info = { |
| 251 | .name = TYPE_CXL_DSP, |
| 252 | .instance_size = sizeof(CXLDownstreamPort), |
| 253 | .parent = TYPE_PCIE_SLOT, |
| 254 | .class_init = cxl_dsp_class_init, |
| 255 | .interfaces = (const InterfaceInfo[]) { |
| 256 | { INTERFACE_PCIE_DEVICE }, |
| 257 | { INTERFACE_CXL_DEVICE }, |
| 258 | { } |
| 259 | }, |
| 260 | }; |
| 261 | |
| 262 | static void cxl_dsp_register_type(void) |
| 263 | { |
| 264 | type_register_static(&cxl_dsp_info); |
| 265 | } |
| 266 | |
| 267 | type_init(cxl_dsp_register_type); |