| 1 | /* |
| 2 | * CXL 2.0 Root Port Implementation |
| 3 | * |
| 4 | * Copyright(C) 2020 Intel Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "qemu/range.h" |
| 23 | #include "hw/pci/pci_bridge.h" |
| 24 | #include "hw/pci/pcie_port.h" |
| 25 | #include "hw/pci/msi.h" |
| 26 | #include "hw/core/qdev-properties.h" |
| 27 | #include "hw/core/qdev-properties-system.h" |
| 28 | #include "hw/core/sysbus.h" |
| 29 | #include "qapi/error.h" |
| 30 | #include "hw/cxl/cxl.h" |
| 31 | |
| 32 | #define CXL_ROOT_PORT_DID 0x7075 |
| 33 | |
| 34 | #define CXL_RP_MSI_OFFSET 0x60 |
| 35 | #define CXL_RP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT |
| 36 | #define CXL_RP_MSI_NR_VECTOR 2 |
| 37 | |
| 38 | /* Copied from the gen root port which we derive */ |
| 39 | #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 |
| 40 | #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ |
| 41 | (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) |
| 42 | #define CXL_ROOT_PORT_DVSEC_OFFSET \ |
| 43 | (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) |
| 44 | |
| 45 | typedef struct CXLRootPort { |
| 46 | /*< private >*/ |
| 47 | PCIESlot parent_obj; |
| 48 | |
| 49 | CXLComponentState cxl_cstate; |
| 50 | PCIResReserve res_reserve; |
| 51 | } CXLRootPort; |
| 52 | |
| 53 | #define TYPE_CXL_ROOT_PORT "cxl-rp" |
| 54 | DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT) |
| 55 | |
| 56 | /* |
| 57 | * If two MSI vector are allocated, Advanced Error Interrupt Message Number |
| 58 | * is 1. otherwise 0. |
| 59 | * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. |
| 60 | */ |
| 61 | static uint8_t cxl_rp_aer_vector(const PCIDevice *d) |
| 62 | { |
| 63 | switch (msi_nr_vectors_allocated(d)) { |
| 64 | case 1: |
| 65 | return 0; |
| 66 | case 2: |
| 67 | return 1; |
| 68 | case 4: |
| 69 | case 8: |
| 70 | case 16: |
| 71 | case 32: |
| 72 | default: |
| 73 | break; |
| 74 | } |
| 75 | abort(); |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static int cxl_rp_interrupts_init(PCIDevice *d, Error **errp) |
| 80 | { |
| 81 | int rc; |
| 82 | |
| 83 | rc = msi_init(d, CXL_RP_MSI_OFFSET, CXL_RP_MSI_NR_VECTOR, |
| 84 | CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
| 85 | CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, |
| 86 | errp); |
| 87 | if (rc < 0) { |
| 88 | assert(rc == -ENOTSUP); |
| 89 | } |
| 90 | |
| 91 | return rc; |
| 92 | } |
| 93 | |
| 94 | static void cxl_rp_interrupts_uninit(PCIDevice *d) |
| 95 | { |
| 96 | msi_uninit(d); |
| 97 | } |
| 98 | |
| 99 | static void latch_registers(CXLRootPort *crp) |
| 100 | { |
| 101 | uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; |
| 102 | uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask; |
| 103 | |
| 104 | cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT, |
| 105 | true); |
| 106 | } |
| 107 | |
| 108 | static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) |
| 109 | { |
| 110 | PCIESlot *s = PCIE_SLOT(d); |
| 111 | uint8_t *dvsec; |
| 112 | |
| 113 | dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 }; |
| 114 | cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, |
| 115 | EXTENSIONS_PORT_DVSEC_LENGTH, |
| 116 | EXTENSIONS_PORT_DVSEC, |
| 117 | EXTENSIONS_PORT_DVSEC_REVID, dvsec); |
| 118 | |
| 119 | dvsec = (uint8_t *)&(CXLDVSECPortGPF){ |
| 120 | .rsvd = 0, |
| 121 | .phase1_ctrl = 1, /* 1μs timeout */ |
| 122 | .phase2_ctrl = 1, /* 1μs timeout */ |
| 123 | }; |
| 124 | cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, |
| 125 | GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC, |
| 126 | GPF_PORT_DVSEC_REVID, dvsec); |
| 127 | |
| 128 | dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ |
| 129 | .cap = 0x26, /* IO, Mem, non-MLD */ |
| 130 | .ctrl = 0x2, |
| 131 | .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ |
| 132 | .rcvd_mod_ts_data_phase1 = 0xef, |
| 133 | }; |
| 134 | cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, |
| 135 | PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH, |
| 136 | PCIE_FLEXBUS_PORT_DVSEC, |
| 137 | PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec); |
| 138 | |
| 139 | dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){ |
| 140 | .rsvd = 0, |
| 141 | .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, |
| 142 | .reg0_base_hi = 0, |
| 143 | }; |
| 144 | cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, |
| 145 | REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC, |
| 146 | REG_LOC_DVSEC_REVID, dvsec); |
| 147 | } |
| 148 | |
| 149 | static void cxl_rp_realize(DeviceState *dev, Error **errp) |
| 150 | { |
| 151 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
| 152 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); |
| 153 | CXLRootPort *crp = CXL_ROOT_PORT(dev); |
| 154 | CXLComponentState *cxl_cstate = &crp->cxl_cstate; |
| 155 | ComponentRegisters *cregs = &cxl_cstate->crb; |
| 156 | MemoryRegion *component_bar = &cregs->component_registers; |
| 157 | Error *local_err = NULL; |
| 158 | |
| 159 | rpc->parent_realize(dev, &local_err); |
| 160 | if (local_err) { |
| 161 | error_propagate(errp, local_err); |
| 162 | return; |
| 163 | } |
| 164 | |
| 165 | int rc = |
| 166 | pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, errp); |
| 167 | if (rc < 0) { |
| 168 | rpc->parent_class.exit(pci_dev); |
| 169 | return; |
| 170 | } |
| 171 | |
| 172 | if (!crp->res_reserve.io || crp->res_reserve.io == -1) { |
| 173 | pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND, |
| 174 | PCI_COMMAND_IO); |
| 175 | pci_dev->wmask[PCI_IO_BASE] = 0; |
| 176 | pci_dev->wmask[PCI_IO_LIMIT] = 0; |
| 177 | } |
| 178 | |
| 179 | cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET; |
| 180 | cxl_cstate->pdev = pci_dev; |
| 181 | build_dvsecs(pci_dev, cxl_cstate); |
| 182 | |
| 183 | cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, |
| 184 | TYPE_CXL_ROOT_PORT); |
| 185 | |
| 186 | pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX, |
| 187 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 188 | PCI_BASE_ADDRESS_MEM_TYPE_64, |
| 189 | component_bar); |
| 190 | } |
| 191 | |
| 192 | static void cxl_rp_reset_hold(Object *obj, ResetType type) |
| 193 | { |
| 194 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); |
| 195 | CXLRootPort *crp = CXL_ROOT_PORT(obj); |
| 196 | |
| 197 | if (rpc->parent_phases.hold) { |
| 198 | rpc->parent_phases.hold(obj, type); |
| 199 | } |
| 200 | |
| 201 | latch_registers(crp); |
| 202 | } |
| 203 | |
| 204 | static const Property gen_rp_props[] = { |
| 205 | DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1), |
| 206 | DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1), |
| 207 | DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref, -1), |
| 208 | DEFINE_PROP_SIZE("pref32-reserve", CXLRootPort, res_reserve.mem_pref_32, |
| 209 | -1), |
| 210 | DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64, |
| 211 | -1), |
| 212 | DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, |
| 213 | speed, PCIE_LINK_SPEED_64), |
| 214 | DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, |
| 215 | width, PCIE_LINK_WIDTH_32), |
| 216 | DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), |
| 217 | }; |
| 218 | |
| 219 | static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, |
| 220 | uint32_t val, int len) |
| 221 | { |
| 222 | CXLRootPort *crp = CXL_ROOT_PORT(dev); |
| 223 | |
| 224 | if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { |
| 225 | uint8_t *reg = &dev->config[addr]; |
| 226 | addr -= crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; |
| 227 | if (addr == PORT_CONTROL_OFFSET) { |
| 228 | if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) { |
| 229 | /* unmask SBR */ |
| 230 | qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); |
| 231 | } |
| 232 | if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) { |
| 233 | /* Alt Memory & ID Space Enable */ |
| 234 | qemu_log_mask(LOG_UNIMP, |
| 235 | "Alt Memory & ID space is not supported\n"); |
| 236 | } |
| 237 | } |
| 238 | } |
| 239 | } |
| 240 | |
| 241 | static void cxl_rp_aer_vector_update(PCIDevice *d) |
| 242 | { |
| 243 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); |
| 244 | |
| 245 | if (rpc->aer_vector) { |
| 246 | pcie_aer_root_set_vector(d, rpc->aer_vector(d)); |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val, |
| 251 | int len) |
| 252 | { |
| 253 | uint16_t slt_ctl, slt_sta; |
| 254 | uint32_t root_cmd = |
| 255 | pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); |
| 256 | |
| 257 | pcie_cap_slot_get(d, &slt_ctl, &slt_sta); |
| 258 | pci_bridge_write_config(d, address, val, len); |
| 259 | cxl_rp_aer_vector_update(d); |
| 260 | pcie_cap_flr_write_config(d, address, val, len); |
| 261 | pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); |
| 262 | pcie_aer_write_config(d, address, val, len); |
| 263 | pcie_aer_root_write_config(d, address, val, len, root_cmd); |
| 264 | |
| 265 | cxl_rp_dvsec_write_config(d, address, val, len); |
| 266 | } |
| 267 | |
| 268 | static void cxl_root_port_class_init(ObjectClass *oc, const void *data) |
| 269 | { |
| 270 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 271 | PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); |
| 272 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 273 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc); |
| 274 | |
| 275 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 276 | k->device_id = CXL_ROOT_PORT_DID; |
| 277 | dc->desc = "CXL Root Port"; |
| 278 | k->revision = 0; |
| 279 | device_class_set_props(dc, gen_rp_props); |
| 280 | k->config_write = cxl_rp_write_config; |
| 281 | |
| 282 | device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize); |
| 283 | resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL, |
| 284 | &rpc->parent_phases); |
| 285 | |
| 286 | rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; |
| 287 | rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; |
| 288 | rpc->aer_vector = cxl_rp_aer_vector; |
| 289 | rpc->interrupts_init = cxl_rp_interrupts_init; |
| 290 | rpc->interrupts_uninit = cxl_rp_interrupts_uninit; |
| 291 | |
| 292 | dc->hotpluggable = false; |
| 293 | } |
| 294 | |
| 295 | static const TypeInfo cxl_root_port_info = { |
| 296 | .name = TYPE_CXL_ROOT_PORT, |
| 297 | .parent = TYPE_PCIE_ROOT_PORT, |
| 298 | .instance_size = sizeof(CXLRootPort), |
| 299 | .class_init = cxl_root_port_class_init, |
| 300 | .interfaces = (const InterfaceInfo[]) { |
| 301 | { INTERFACE_CXL_DEVICE }, |
| 302 | { } |
| 303 | }, |
| 304 | }; |
| 305 | |
| 306 | static void cxl_register(void) |
| 307 | { |
| 308 | type_register_static(&cxl_root_port_info); |
| 309 | } |
| 310 | |
| 311 | type_init(cxl_register); |