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1 /*
2 * Generic PCI Express Root Port emulation
3 *
4 * Copyright (C) 2017 Red Hat Inc
5 *
6 * Authors:
7 * Marcel Apfelbaum <marcel@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/pci/msix.h"
17 #include "hw/pci/pcie_port.h"
18 #include "hw/core/qdev-properties.h"
19 #include "hw/core/qdev-properties-system.h"
20 #include "migration/vmstate.h"
21 #include "qom/object.h"
22
23 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
24 OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
25
26 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
27 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
28 (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
29
30 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
31 #define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096
32
33 struct GenPCIERootPort {
34 /*< private >*/
35 PCIESlot parent_obj;
36 /*< public >*/
37
38 /* additional resources to reserve */
39 PCIResReserve res_reserve;
40 };
41
42 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
43 {
44 return 0;
45 }
46
47 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
48 {
49 int rc;
50
51 rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
52
53 if (rc < 0) {
54 assert(rc == -ENOTSUP);
55 } else {
56 msix_vector_use(d, 0);
57 }
58
59 return rc;
60 }
61
62 static void gen_rp_interrupts_uninit(PCIDevice *d)
63 {
64 msix_uninit_exclusive_bar(d);
65 }
66
67 static void gen_rp_realize(DeviceState *dev, Error **errp)
68 {
69 PCIDevice *d = PCI_DEVICE(dev);
70 PCIESlot *s = PCIE_SLOT(d);
71 GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
72 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
73 Error *local_err = NULL;
74
75 rpc->parent_realize(dev, &local_err);
76 if (local_err) {
77 error_propagate(errp, local_err);
78 return;
79 }
80
81 /*
82 * reserving IO space led to worse issues in 6.1, when this hunk was
83 * introduced. (see commit: 211afe5c69b59). Keep this broken for 6.1
84 * machine type ABI compatibility only
85 */
86 if (s->hide_native_hotplug_cap && grp->res_reserve.io == -1 && s->hotplug) {
87 grp->res_reserve.io = GEN_PCIE_ROOT_DEFAULT_IO_RANGE;
88 }
89 int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
90 grp->res_reserve, errp);
91
92 if (rc < 0) {
93 rpc->parent_class.exit(d);
94 return;
95 }
96
97 if (!grp->res_reserve.io) {
98 pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
99 PCI_COMMAND_IO);
100 d->wmask[PCI_IO_BASE] = 0;
101 d->wmask[PCI_IO_LIMIT] = 0;
102 }
103 }
104
105 static const VMStateDescription vmstate_rp_dev = {
106 .name = "pcie-root-port",
107 .priority = MIG_PRI_PCI_BUS,
108 .version_id = 1,
109 .minimum_version_id = 1,
110 .post_load = pcie_cap_slot_post_load,
111 .fields = (const VMStateField[]) {
112 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
113 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
114 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
115 VMSTATE_MSIX(parent_obj.parent_obj.parent_obj.parent_obj,
116 GenPCIERootPort),
117 VMSTATE_END_OF_LIST()
118 }
119 };
120
121 static const Property gen_rp_props[] = {
122 DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
123 res_reserve.bus, -1),
124 DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
125 res_reserve.io, -1),
126 DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
127 res_reserve.mem_non_pref, -1),
128 DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
129 res_reserve.mem_pref_32, -1),
130 DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
131 res_reserve.mem_pref_64, -1),
132 DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
133 speed, PCIE_LINK_SPEED_16),
134 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
135 width, PCIE_LINK_WIDTH_32),
136 };
137
138 static void gen_rp_dev_class_init(ObjectClass *klass, const void *data)
139 {
140 DeviceClass *dc = DEVICE_CLASS(klass);
141 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
142 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
143
144 k->vendor_id = PCI_VENDOR_ID_REDHAT;
145 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
146 dc->desc = "PCI Express Root Port";
147 dc->vmsd = &vmstate_rp_dev;
148 device_class_set_props(dc, gen_rp_props);
149
150 device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
151
152 rpc->aer_vector = gen_rp_aer_vector;
153 rpc->interrupts_init = gen_rp_interrupts_init;
154 rpc->interrupts_uninit = gen_rp_interrupts_uninit;
155 rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
156 rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
157 }
158
159 static const TypeInfo gen_rp_dev_info = {
160 .name = TYPE_GEN_PCIE_ROOT_PORT,
161 .parent = TYPE_PCIE_ROOT_PORT,
162 .instance_size = sizeof(GenPCIERootPort),
163 .class_init = gen_rp_dev_class_init,
164 };
165
166 static void gen_rp_register_types(void)
167 {
168 type_register_static(&gen_rp_dev_info);
169 }
170 type_init(gen_rp_register_types)