| 1 | /* |
| 2 | * PCI Expander Bridge Device Emulation |
| 3 | * |
| 4 | * Copyright (C) 2015 Red Hat Inc |
| 5 | * |
| 6 | * Authors: |
| 7 | * Marcel Apfelbaum <marcel@redhat.com> |
| 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | */ |
| 12 | |
| 13 | #include "qemu/osdep.h" |
| 14 | #include "qapi/error.h" |
| 15 | #include "hw/pci/pci.h" |
| 16 | #include "hw/pci/pci_bus.h" |
| 17 | #include "hw/pci/pci_host.h" |
| 18 | #include "hw/pci/pcie_port.h" |
| 19 | #include "hw/core/qdev-properties.h" |
| 20 | #include "hw/pci/pci_bridge.h" |
| 21 | #include "hw/pci-bridge/pci_expander_bridge.h" |
| 22 | #include "hw/cxl/cxl.h" |
| 23 | #include "qemu/range.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "qemu/module.h" |
| 26 | #include "system/numa.h" |
| 27 | #include "hw/core/boards.h" |
| 28 | #include "qom/object.h" |
| 29 | |
| 30 | enum BusType { PCI, PCIE, CXL }; |
| 31 | |
| 32 | #define TYPE_PXB_BUS "pxb-bus" |
| 33 | typedef struct PXBBus PXBBus; |
| 34 | DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, |
| 35 | TYPE_PXB_BUS) |
| 36 | |
| 37 | DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, |
| 38 | TYPE_PXB_PCIE_BUS) |
| 39 | |
| 40 | DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, |
| 41 | TYPE_PXB_CXL_BUS) |
| 42 | |
| 43 | struct PXBBus { |
| 44 | /*< private >*/ |
| 45 | PCIBus parent_obj; |
| 46 | /*< public >*/ |
| 47 | |
| 48 | char bus_path[8]; |
| 49 | }; |
| 50 | |
| 51 | OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV) |
| 52 | |
| 53 | static GList *pxb_dev_list; |
| 54 | |
| 55 | #define TYPE_PXB_HOST "pxb-host" |
| 56 | |
| 57 | CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb) |
| 58 | { |
| 59 | CXLHost *host = PXB_CXL_HOST(hb); |
| 60 | |
| 61 | return &host->cxl_cstate; |
| 62 | } |
| 63 | |
| 64 | bool cxl_get_hb_passthrough(PCIHostState *hb) |
| 65 | { |
| 66 | CXLHost *host = PXB_CXL_HOST(hb); |
| 67 | |
| 68 | return host->passthrough; |
| 69 | } |
| 70 | |
| 71 | static int pxb_bus_num(PCIBus *bus) |
| 72 | { |
| 73 | PXBDev *pxb = PXB_DEV(bus->parent_dev); |
| 74 | |
| 75 | return pxb->bus_nr; |
| 76 | } |
| 77 | |
| 78 | static uint16_t pxb_bus_numa_node(PCIBus *bus) |
| 79 | { |
| 80 | PXBDev *pxb = PXB_DEV(bus->parent_dev); |
| 81 | |
| 82 | return pxb->numa_node; |
| 83 | } |
| 84 | |
| 85 | static void prop_pxb_uid_get(Object *obj, Visitor *v, const char *name, |
| 86 | void *opaque, Error **errp) |
| 87 | { |
| 88 | PCIBus *bus = PCI_BUS(obj); |
| 89 | uint32_t uid; |
| 90 | |
| 91 | if (!bus->parent_dev) { |
| 92 | error_setg(errp, "bus not attached to a device"); |
| 93 | return; |
| 94 | } |
| 95 | uid = pci_bus_num(bus); |
| 96 | visit_type_uint32(v, name, &uid, errp); |
| 97 | } |
| 98 | |
| 99 | static void pxb_bus_class_init(ObjectClass *class, const void *data) |
| 100 | { |
| 101 | PCIBusClass *pbc = PCI_BUS_CLASS(class); |
| 102 | |
| 103 | pbc->bus_num = pxb_bus_num; |
| 104 | pbc->numa_node = pxb_bus_numa_node; |
| 105 | |
| 106 | object_class_property_add(class, "acpi_uid", "uint32", |
| 107 | prop_pxb_uid_get, NULL, NULL, NULL); |
| 108 | object_class_property_set_description(class, "acpi_uid", |
| 109 | "ACPI Unique ID used to distinguish this PCI Host Bridge / ACPI00016"); |
| 110 | } |
| 111 | |
| 112 | static const TypeInfo pxb_bus_info = { |
| 113 | .name = TYPE_PXB_BUS, |
| 114 | .parent = TYPE_PCI_BUS, |
| 115 | .instance_size = sizeof(PXBBus), |
| 116 | .class_init = pxb_bus_class_init, |
| 117 | }; |
| 118 | |
| 119 | static const TypeInfo pxb_pcie_bus_info = { |
| 120 | .name = TYPE_PXB_PCIE_BUS, |
| 121 | .parent = TYPE_PCIE_BUS, |
| 122 | .instance_size = sizeof(PXBBus), |
| 123 | .class_init = pxb_bus_class_init, |
| 124 | }; |
| 125 | |
| 126 | static const TypeInfo pxb_cxl_bus_info = { |
| 127 | .name = TYPE_PXB_CXL_BUS, |
| 128 | .parent = TYPE_CXL_BUS, |
| 129 | .instance_size = sizeof(PXBBus), |
| 130 | .class_init = pxb_bus_class_init, |
| 131 | }; |
| 132 | |
| 133 | static const char *pxb_host_root_bus_path(PCIHostState *host_bridge, |
| 134 | PCIBus *rootbus) |
| 135 | { |
| 136 | PXBBus *bus = pci_bus_is_cxl(rootbus) ? |
| 137 | PXB_CXL_BUS(rootbus) : |
| 138 | pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) : |
| 139 | PXB_BUS(rootbus); |
| 140 | |
| 141 | snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus)); |
| 142 | return bus->bus_path; |
| 143 | } |
| 144 | |
| 145 | static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) |
| 146 | { |
| 147 | const PCIHostState *pxb_host; |
| 148 | const PCIBus *pxb_bus; |
| 149 | const PXBDev *pxb_dev; |
| 150 | int position; |
| 151 | const DeviceState *pxb_dev_base; |
| 152 | const PCIHostState *main_host; |
| 153 | const SysBusDevice *main_host_sbd; |
| 154 | |
| 155 | pxb_host = PCI_HOST_BRIDGE(dev); |
| 156 | pxb_bus = pxb_host->bus; |
| 157 | pxb_dev = PXB_DEV(pxb_bus->parent_dev); |
| 158 | position = g_list_index(pxb_dev_list, pxb_dev); |
| 159 | assert(position >= 0); |
| 160 | |
| 161 | pxb_dev_base = DEVICE(pxb_dev); |
| 162 | main_host = PCI_HOST_BRIDGE(pxb_dev_base->parent_bus->parent); |
| 163 | main_host_sbd = SYS_BUS_DEVICE(main_host); |
| 164 | |
| 165 | if (main_host_sbd->num_mmio > 0) { |
| 166 | return g_strdup_printf(HWADDR_FMT_plx ",%x", |
| 167 | main_host_sbd->mmio[0].addr, position + 1); |
| 168 | } |
| 169 | if (main_host_sbd->num_pio > 0) { |
| 170 | return g_strdup_printf("i%04x,%x", |
| 171 | main_host_sbd->pio[0], position + 1); |
| 172 | } |
| 173 | return NULL; |
| 174 | } |
| 175 | |
| 176 | static void pxb_host_class_init(ObjectClass *class, const void *data) |
| 177 | { |
| 178 | DeviceClass *dc = DEVICE_CLASS(class); |
| 179 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class); |
| 180 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class); |
| 181 | |
| 182 | dc->fw_name = "pci"; |
| 183 | /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ |
| 184 | dc->user_creatable = false; |
| 185 | sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address; |
| 186 | hc->root_bus_path = pxb_host_root_bus_path; |
| 187 | } |
| 188 | |
| 189 | static const TypeInfo pxb_host_info = { |
| 190 | .name = TYPE_PXB_HOST, |
| 191 | .parent = TYPE_PCI_HOST_BRIDGE, |
| 192 | .class_init = pxb_host_class_init, |
| 193 | }; |
| 194 | |
| 195 | static void pxb_cxl_realize(DeviceState *dev, Error **errp) |
| 196 | { |
| 197 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 198 | CXLHost *cxl = PXB_CXL_HOST(dev); |
| 199 | CXLComponentState *cxl_cstate = &cxl->cxl_cstate; |
| 200 | struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; |
| 201 | |
| 202 | cxl_component_register_block_init(OBJECT(dev), cxl_cstate, |
| 203 | TYPE_PXB_CXL_HOST); |
| 204 | sysbus_init_mmio(sbd, mr); |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * Host bridge realization has no means of knowning state associated |
| 209 | * with a particular machine. As such, it is nececssary to delay |
| 210 | * final setup of the host bridge register space until later in the |
| 211 | * machine bring up. |
| 212 | */ |
| 213 | void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp) |
| 214 | { |
| 215 | PXBCXLDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(bus)); |
| 216 | CXLHost *cxl = pxb->cxl_host_bridge; |
| 217 | CXLComponentState *cxl_cstate = &cxl->cxl_cstate; |
| 218 | struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; |
| 219 | hwaddr offset; |
| 220 | |
| 221 | offset = memory_region_size(mr) * cxl_state->next_mr_idx; |
| 222 | if (offset > memory_region_size(&cxl_state->host_mr)) { |
| 223 | error_setg(errp, "Insufficient space for pxb cxl host register space"); |
| 224 | return; |
| 225 | } |
| 226 | |
| 227 | memory_region_add_subregion(&cxl_state->host_mr, offset, mr); |
| 228 | cxl_state->next_mr_idx++; |
| 229 | } |
| 230 | |
| 231 | static void pxb_cxl_host_class_init(ObjectClass *class, const void *data) |
| 232 | { |
| 233 | DeviceClass *dc = DEVICE_CLASS(class); |
| 234 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class); |
| 235 | |
| 236 | hc->root_bus_path = pxb_host_root_bus_path; |
| 237 | dc->fw_name = "cxl"; |
| 238 | dc->realize = pxb_cxl_realize; |
| 239 | /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ |
| 240 | dc->user_creatable = false; |
| 241 | } |
| 242 | |
| 243 | /* |
| 244 | * This is a device to handle the MMIO for a CXL host bridge. It does nothing |
| 245 | * else. |
| 246 | */ |
| 247 | static const TypeInfo cxl_host_info = { |
| 248 | .name = TYPE_PXB_CXL_HOST, |
| 249 | .parent = TYPE_PCI_HOST_BRIDGE, |
| 250 | .instance_size = sizeof(CXLHost), |
| 251 | .class_init = pxb_cxl_host_class_init, |
| 252 | }; |
| 253 | |
| 254 | /* |
| 255 | * Registers the PXB bus as a child of pci host root bus. |
| 256 | */ |
| 257 | static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp) |
| 258 | { |
| 259 | PCIBus *bus = pci_get_bus(dev); |
| 260 | int pxb_bus_num = pci_bus_num(pxb_bus); |
| 261 | |
| 262 | if (bus->parent_dev) { |
| 263 | error_setg(errp, "PXB devices can be attached only to root bus"); |
| 264 | return; |
| 265 | } |
| 266 | |
| 267 | QLIST_FOREACH(bus, &bus->child, sibling) { |
| 268 | if (pci_bus_num(bus) == pxb_bus_num) { |
| 269 | error_setg(errp, "Bus %d is already in use", pxb_bus_num); |
| 270 | return; |
| 271 | } |
| 272 | } |
| 273 | QLIST_INSERT_HEAD(&pci_get_bus(dev)->child, pxb_bus, sibling); |
| 274 | } |
| 275 | |
| 276 | static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin) |
| 277 | { |
| 278 | PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev; |
| 279 | |
| 280 | /* |
| 281 | * First carry out normal swizzle to handle |
| 282 | * multiple root ports on a pxb instance. |
| 283 | */ |
| 284 | pin = pci_swizzle_map_irq_fn(pci_dev, pin); |
| 285 | |
| 286 | /* |
| 287 | * The bios does not index the pxb slot number when |
| 288 | * it computes the IRQ because it resides on bus 0 |
| 289 | * and not on the current bus. |
| 290 | * However QEMU routes the irq through bus 0 and adds |
| 291 | * the pxb slot to the IRQ computation of the PXB |
| 292 | * device. |
| 293 | * |
| 294 | * Synchronize between bios and QEMU by canceling |
| 295 | * pxb's effect. |
| 296 | */ |
| 297 | return pin - PCI_SLOT(pxb->devfn); |
| 298 | } |
| 299 | |
| 300 | static void pxb_cxl_dev_reset(DeviceState *dev) |
| 301 | { |
| 302 | CXLHost *cxl = PXB_CXL_DEV(dev)->cxl_host_bridge; |
| 303 | CXLComponentState *cxl_cstate = &cxl->cxl_cstate; |
| 304 | PCIHostState *hb = PCI_HOST_BRIDGE(cxl); |
| 305 | uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers; |
| 306 | uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask; |
| 307 | int dsp_count = 0; |
| 308 | |
| 309 | cxl_component_register_init_common(reg_state, write_msk, CXL2_RC, false); |
| 310 | /* |
| 311 | * The CXL specification allows for host bridges with no HDM decoders |
| 312 | * if they only have a single root port. |
| 313 | */ |
| 314 | if (!PXB_CXL_DEV(dev)->hdm_for_passthrough) { |
| 315 | dsp_count = pcie_count_ds_ports(hb->bus); |
| 316 | } |
| 317 | /* Initial reset will have 0 dsp so wait until > 0 */ |
| 318 | if (dsp_count == 1) { |
| 319 | cxl->passthrough = true; |
| 320 | /* Set Capability ID in header to NONE */ |
| 321 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0); |
| 322 | } else { |
| 323 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, |
| 324 | 8); |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | static gint pxb_compare(gconstpointer a, gconstpointer b) |
| 329 | { |
| 330 | const PXBDev *pxb_a = a, *pxb_b = b; |
| 331 | |
| 332 | return pxb_a->bus_nr < pxb_b->bus_nr ? -1 : |
| 333 | pxb_a->bus_nr > pxb_b->bus_nr ? 1 : |
| 334 | 0; |
| 335 | } |
| 336 | |
| 337 | static bool pxb_dev_realize_common(PCIDevice *dev, enum BusType type, |
| 338 | Error **errp) |
| 339 | { |
| 340 | PXBDev *pxb = PXB_DEV(dev); |
| 341 | DeviceState *ds, *bds = NULL; |
| 342 | PCIBus *bus; |
| 343 | const char *dev_name = NULL; |
| 344 | Error *local_err = NULL; |
| 345 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 346 | |
| 347 | if (ms->numa_state == NULL) { |
| 348 | error_setg(errp, "NUMA is not supported by this machine-type"); |
| 349 | return false; |
| 350 | } |
| 351 | |
| 352 | if (pxb->numa_node != NUMA_NODE_UNASSIGNED && |
| 353 | pxb->numa_node >= ms->numa_state->num_nodes) { |
| 354 | error_setg(errp, "Illegal numa node %d", pxb->numa_node); |
| 355 | return false; |
| 356 | } |
| 357 | |
| 358 | if (dev->qdev.id && *dev->qdev.id) { |
| 359 | dev_name = dev->qdev.id; |
| 360 | } |
| 361 | |
| 362 | ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST); |
| 363 | if (type == PCIE) { |
| 364 | bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); |
| 365 | } else if (type == CXL) { |
| 366 | bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS); |
| 367 | bus->flags |= PCI_BUS_CXL; |
| 368 | PXB_CXL_DEV(dev)->cxl_host_bridge = PXB_CXL_HOST(ds); |
| 369 | } else { |
| 370 | bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS); |
| 371 | bds = qdev_new("pci-bridge"); |
| 372 | bds->id = g_strdup(dev_name); |
| 373 | qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr); |
| 374 | qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false); |
| 375 | } |
| 376 | |
| 377 | bus->parent_dev = dev; |
| 378 | bus->address_space_mem = pci_get_bus(dev)->address_space_mem; |
| 379 | bus->address_space_io = pci_get_bus(dev)->address_space_io; |
| 380 | bus->map_irq = pxb_map_irq_fn; |
| 381 | |
| 382 | PCI_HOST_BRIDGE(ds)->bus = bus; |
| 383 | PCI_HOST_BRIDGE(ds)->bypass_iommu = pxb->bypass_iommu; |
| 384 | |
| 385 | pxb_register_bus(dev, bus, &local_err); |
| 386 | if (local_err) { |
| 387 | error_propagate(errp, local_err); |
| 388 | goto err_register_bus; |
| 389 | } |
| 390 | |
| 391 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal); |
| 392 | if (bds) { |
| 393 | qdev_realize_and_unref(bds, &bus->qbus, &error_fatal); |
| 394 | } |
| 395 | |
| 396 | pci_word_test_and_set_mask(dev->config + PCI_STATUS, |
| 397 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
| 398 | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST); |
| 399 | |
| 400 | pxb_dev_list = g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare); |
| 401 | return true; |
| 402 | |
| 403 | err_register_bus: |
| 404 | object_unref(OBJECT(bds)); |
| 405 | object_unparent(OBJECT(bus)); |
| 406 | object_unref(OBJECT(ds)); |
| 407 | return false; |
| 408 | } |
| 409 | |
| 410 | static void pxb_dev_realize(PCIDevice *dev, Error **errp) |
| 411 | { |
| 412 | if (pci_bus_is_express(pci_get_bus(dev))) { |
| 413 | error_setg(errp, "pxb devices cannot reside on a PCIe bus"); |
| 414 | return; |
| 415 | } |
| 416 | |
| 417 | pxb_dev_realize_common(dev, PCI, errp); |
| 418 | } |
| 419 | |
| 420 | static void pxb_dev_exitfn(PCIDevice *pci_dev) |
| 421 | { |
| 422 | PXBDev *pxb = PXB_DEV(pci_dev); |
| 423 | |
| 424 | pxb_dev_list = g_list_remove(pxb_dev_list, pxb); |
| 425 | } |
| 426 | |
| 427 | static const Property pxb_dev_properties[] = { |
| 428 | /* Note: 0 is not a legal PXB bus number. */ |
| 429 | DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), |
| 430 | DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), |
| 431 | DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false), |
| 432 | }; |
| 433 | |
| 434 | static void pxb_dev_class_init(ObjectClass *klass, const void *data) |
| 435 | { |
| 436 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 437 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 438 | |
| 439 | k->realize = pxb_dev_realize; |
| 440 | k->exit = pxb_dev_exitfn; |
| 441 | k->vendor_id = PCI_VENDOR_ID_REDHAT; |
| 442 | k->device_id = PCI_DEVICE_ID_REDHAT_PXB; |
| 443 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 444 | |
| 445 | dc->desc = "PCI Expander Bridge"; |
| 446 | device_class_set_props(dc, pxb_dev_properties); |
| 447 | dc->hotpluggable = false; |
| 448 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 449 | } |
| 450 | |
| 451 | static const TypeInfo pxb_dev_info = { |
| 452 | .name = TYPE_PXB_DEV, |
| 453 | .parent = TYPE_PCI_DEVICE, |
| 454 | .instance_size = sizeof(PXBDev), |
| 455 | .class_init = pxb_dev_class_init, |
| 456 | .interfaces = (const InterfaceInfo[]) { |
| 457 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 458 | { }, |
| 459 | }, |
| 460 | }; |
| 461 | |
| 462 | static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp) |
| 463 | { |
| 464 | if (!pci_bus_is_express(pci_get_bus(dev))) { |
| 465 | error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus"); |
| 466 | return; |
| 467 | } |
| 468 | |
| 469 | pxb_dev_realize_common(dev, PCIE, errp); |
| 470 | } |
| 471 | |
| 472 | static void pxb_pcie_dev_class_init(ObjectClass *klass, const void *data) |
| 473 | { |
| 474 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 475 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 476 | |
| 477 | k->realize = pxb_pcie_dev_realize; |
| 478 | k->exit = pxb_dev_exitfn; |
| 479 | k->vendor_id = PCI_VENDOR_ID_REDHAT; |
| 480 | k->device_id = PCI_DEVICE_ID_REDHAT_PXB_PCIE; |
| 481 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 482 | |
| 483 | dc->desc = "PCI Express Expander Bridge"; |
| 484 | dc->hotpluggable = false; |
| 485 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 486 | } |
| 487 | |
| 488 | static const TypeInfo pxb_pcie_dev_info = { |
| 489 | .name = TYPE_PXB_PCIE_DEV, |
| 490 | .parent = TYPE_PXB_DEV, |
| 491 | .instance_size = sizeof(PXBPCIEDev), |
| 492 | .class_init = pxb_pcie_dev_class_init, |
| 493 | .interfaces = (const InterfaceInfo[]) { |
| 494 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 495 | { }, |
| 496 | }, |
| 497 | }; |
| 498 | |
| 499 | static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) |
| 500 | { |
| 501 | /* A CXL PXB's parent bus is still PCIe */ |
| 502 | if (!pci_bus_is_express(pci_get_bus(dev))) { |
| 503 | error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); |
| 504 | return; |
| 505 | } |
| 506 | |
| 507 | if (!pxb_dev_realize_common(dev, CXL, errp)) { |
| 508 | return; |
| 509 | } |
| 510 | pxb_cxl_dev_reset(DEVICE(dev)); |
| 511 | } |
| 512 | |
| 513 | static const Property pxb_cxl_dev_properties[] = { |
| 514 | DEFINE_PROP_BOOL("hdm_for_passthrough", PXBCXLDev, hdm_for_passthrough, false), |
| 515 | }; |
| 516 | |
| 517 | static void pxb_cxl_dev_class_init(ObjectClass *klass, const void *data) |
| 518 | { |
| 519 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 520 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 521 | |
| 522 | k->realize = pxb_cxl_dev_realize; |
| 523 | k->exit = pxb_dev_exitfn; |
| 524 | /* |
| 525 | * XXX: These types of bridges don't actually show up in the hierarchy so |
| 526 | * vendor, device, class, etc. ids are intentionally left out. |
| 527 | */ |
| 528 | |
| 529 | dc->desc = "CXL Host Bridge"; |
| 530 | device_class_set_props(dc, pxb_cxl_dev_properties); |
| 531 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 532 | |
| 533 | /* Host bridges aren't hotpluggable. FIXME: spec reference */ |
| 534 | dc->hotpluggable = false; |
| 535 | device_class_set_legacy_reset(dc, pxb_cxl_dev_reset); |
| 536 | } |
| 537 | |
| 538 | static const TypeInfo pxb_cxl_dev_info = { |
| 539 | .name = TYPE_PXB_CXL_DEV, |
| 540 | .parent = TYPE_PXB_PCIE_DEV, |
| 541 | .instance_size = sizeof(PXBCXLDev), |
| 542 | .class_init = pxb_cxl_dev_class_init, |
| 543 | .interfaces = |
| 544 | (const InterfaceInfo[]){ |
| 545 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 546 | {}, |
| 547 | }, |
| 548 | }; |
| 549 | |
| 550 | static void pxb_register_types(void) |
| 551 | { |
| 552 | type_register_static(&pxb_bus_info); |
| 553 | type_register_static(&pxb_pcie_bus_info); |
| 554 | type_register_static(&pxb_cxl_bus_info); |
| 555 | type_register_static(&pxb_host_info); |
| 556 | type_register_static(&cxl_host_info); |
| 557 | type_register_static(&pxb_dev_info); |
| 558 | type_register_static(&pxb_pcie_dev_info); |
| 559 | type_register_static(&pxb_cxl_dev_info); |
| 560 | } |
| 561 | |
| 562 | type_init(pxb_register_types) |