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1 /*
2 * QEMU Generic PCIE-PCI Bridge
3 *
4 * Copyright (c) 2017 Aleksandr Bezzubikov
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "qemu/module.h"
13 #include "hw/pci/pci.h"
14 #include "hw/pci/pci_bus.h"
15 #include "hw/pci/pci_bridge.h"
16 #include "hw/pci/msi.h"
17 #include "hw/pci/shpc.h"
18 #include "hw/pci/slotid_cap.h"
19 #include "hw/core/qdev-properties.h"
20 #include "qom/object.h"
21
22 struct PCIEPCIBridge {
23 /*< private >*/
24 PCIBridge parent_obj;
25
26 OnOffAuto msi;
27 MemoryRegion shpc_bar;
28 /*< public >*/
29 };
30
31 #define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge"
32 OBJECT_DECLARE_SIMPLE_TYPE(PCIEPCIBridge, PCIE_PCI_BRIDGE_DEV)
33
34 static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
35 {
36 PCIBridge *br = PCI_BRIDGE(d);
37 PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d);
38 int rc, pos;
39
40 pci_bridge_initfn(d, TYPE_PCI_BUS);
41
42 d->config[PCI_INTERRUPT_PIN] = 0x1;
43 memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar",
44 shpc_bar_size(d));
45 rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp);
46 if (rc) {
47 goto error;
48 }
49
50 rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp);
51 if (rc < 0) {
52 goto cap_error;
53 }
54
55 pos = pci_pm_init(d, 0, errp);
56 if (pos < 0) {
57 goto pm_error;
58 }
59 pci_set_word(d->config + pos + PCI_PM_PMC, 0x3);
60
61 pcie_cap_arifwd_init(d);
62 pcie_cap_deverr_init(d);
63
64 rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp);
65 if (rc < 0) {
66 goto aer_error;
67 }
68
69 Error *local_err = NULL;
70 if (pcie_br->msi != ON_OFF_AUTO_OFF) {
71 rc = msi_init(d, 0, 1, true, true, &local_err);
72 if (rc < 0) {
73 assert(rc == -ENOTSUP);
74 if (pcie_br->msi != ON_OFF_AUTO_ON) {
75 error_free(local_err);
76 } else {
77 /* failed to satisfy user's explicit request for MSI */
78 error_propagate(errp, local_err);
79 goto msi_error;
80 }
81 }
82 }
83 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
84 PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar);
85 return;
86
87 msi_error:
88 pcie_aer_exit(d);
89 aer_error:
90 pm_error:
91 pcie_cap_exit(d);
92 cap_error:
93 shpc_cleanup(d, &pcie_br->shpc_bar);
94 error:
95 pci_bridge_exitfn(d);
96 }
97
98 static void pcie_pci_bridge_exit(PCIDevice *d)
99 {
100 PCIEPCIBridge *bridge_dev = PCIE_PCI_BRIDGE_DEV(d);
101 pcie_cap_exit(d);
102 shpc_cleanup(d, &bridge_dev->shpc_bar);
103 pci_bridge_exitfn(d);
104 }
105
106 static void pcie_pci_bridge_reset(DeviceState *qdev)
107 {
108 PCIDevice *d = PCI_DEVICE(qdev);
109 pci_bridge_reset(qdev);
110 if (msi_present(d)) {
111 msi_reset(d);
112 }
113 shpc_reset(d);
114 }
115
116 static void pcie_pci_bridge_write_config(PCIDevice *d,
117 uint32_t address, uint32_t val, int len)
118 {
119 pci_bridge_write_config(d, address, val, len);
120 if (msi_present(d)) {
121 msi_write_config(d, address, val, len);
122 }
123 shpc_cap_write_config(d, address, val, len);
124 }
125
126 static const Property pcie_pci_bridge_dev_properties[] = {
127 DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
128 };
129
130 static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
131 .name = TYPE_PCIE_PCI_BRIDGE_DEV,
132 .priority = MIG_PRI_PCI_BUS,
133 .fields = (const VMStateField[]) {
134 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
135 SHPC_VMSTATE(shpc, PCIDevice, NULL),
136 VMSTATE_END_OF_LIST()
137 }
138 };
139
140 static void pcie_pci_bridge_class_init(ObjectClass *klass, const void *data)
141 {
142 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
143 DeviceClass *dc = DEVICE_CLASS(klass);
144 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
145
146 k->vendor_id = PCI_VENDOR_ID_REDHAT;
147 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
148 k->realize = pcie_pci_bridge_realize;
149 k->exit = pcie_pci_bridge_exit;
150 k->config_write = pcie_pci_bridge_write_config;
151 dc->vmsd = &pcie_pci_bridge_dev_vmstate;
152 device_class_set_props(dc, pcie_pci_bridge_dev_properties);
153 device_class_set_legacy_reset(dc, pcie_pci_bridge_reset);
154 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
155 hc->plug = pci_bridge_dev_plug_cb;
156 hc->unplug = pci_bridge_dev_unplug_cb;
157 hc->unplug_request = pci_bridge_dev_unplug_request_cb;
158 }
159
160 static const TypeInfo pcie_pci_bridge_info = {
161 .name = TYPE_PCIE_PCI_BRIDGE_DEV,
162 .parent = TYPE_PCI_BRIDGE,
163 .instance_size = sizeof(PCIEPCIBridge),
164 .class_init = pcie_pci_bridge_class_init,
165 .interfaces = (const InterfaceInfo[]) {
166 { TYPE_HOTPLUG_HANDLER },
167 { INTERFACE_PCIE_DEVICE },
168 { },
169 }
170 };
171
172 static void pciepci_register(void)
173 {
174 type_register_static(&pcie_pci_bridge_info);
175 }
176
177 type_init(pciepci_register);