| 1 | /* |
| 2 | * ASPEED PCIe Host Controller |
| 3 | * |
| 4 | * Copyright (C) 2025 ASPEED Technology Inc. |
| 5 | * Copyright (c) 2022 Cédric Le Goater <clg@kaod.org> |
| 6 | * |
| 7 | * Authors: |
| 8 | * Cédric Le Goater <clg@kaod.org> |
| 9 | * Jamin Lin <jamin_lin@aspeedtech.com> |
| 10 | * |
| 11 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 12 | * |
| 13 | * Based on previous work from Cédric Le Goater. |
| 14 | * Modifications extend support for the ASPEED AST2600 and AST2700 platforms. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "qemu/log.h" |
| 19 | #include "qapi/error.h" |
| 20 | #include "hw/core/qdev-properties.h" |
| 21 | #include "hw/core/registerfields.h" |
| 22 | #include "hw/core/irq.h" |
| 23 | #include "hw/pci/pci_host.h" |
| 24 | #include "hw/pci/pcie_port.h" |
| 25 | #include "hw/pci-host/aspeed_pcie.h" |
| 26 | #include "hw/pci/msi.h" |
| 27 | #include "trace.h" |
| 28 | |
| 29 | /* |
| 30 | * PCIe Root Port |
| 31 | */ |
| 32 | |
| 33 | #define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50 |
| 34 | #define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1 |
| 35 | #define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0 |
| 36 | #define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80 |
| 37 | #define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100 |
| 38 | |
| 39 | static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp) |
| 45 | { |
| 46 | int rc; |
| 47 | |
| 48 | rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET, |
| 49 | ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR, |
| 50 | PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT, |
| 51 | PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT, |
| 52 | errp); |
| 53 | if (rc < 0) { |
| 54 | assert(rc == -ENOTSUP); |
| 55 | } |
| 56 | |
| 57 | return rc; |
| 58 | } |
| 59 | |
| 60 | static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d) |
| 61 | { |
| 62 | msi_uninit(d); |
| 63 | } |
| 64 | |
| 65 | static void aspeed_pcie_root_port_class_init(ObjectClass *klass, |
| 66 | const void *data) |
| 67 | { |
| 68 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 69 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 70 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); |
| 71 | |
| 72 | dc->desc = "ASPEED PCIe Root Port"; |
| 73 | k->vendor_id = PCI_VENDOR_ID_ASPEED; |
| 74 | k->device_id = 0x1150; |
| 75 | dc->user_creatable = true; |
| 76 | |
| 77 | rpc->aer_vector = aspeed_pcie_root_port_aer_vector; |
| 78 | rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init; |
| 79 | rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit; |
| 80 | rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET; |
| 81 | rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET; |
| 82 | rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET; |
| 83 | rpc->ssid = 0x1150; |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * PCIe Root Complex (RC) |
| 88 | */ |
| 89 | |
| 90 | #define ASPEED_PCIE_CFG_RC_MAX_MSI 64 |
| 91 | |
| 92 | static void aspeed_pcie_rc_set_irq(void *opaque, int irq, int level) |
| 93 | { |
| 94 | AspeedPCIERcState *rc = (AspeedPCIERcState *) opaque; |
| 95 | AspeedPCIECfgState *cfg = |
| 96 | container_of(rc, AspeedPCIECfgState, rc); |
| 97 | bool intx; |
| 98 | |
| 99 | assert(irq < PCI_NUM_PINS); |
| 100 | |
| 101 | if (level) { |
| 102 | cfg->regs[cfg->rc_regs->int_sts_reg] |= BIT(irq); |
| 103 | } else { |
| 104 | cfg->regs[cfg->rc_regs->int_sts_reg] &= ~BIT(irq); |
| 105 | } |
| 106 | |
| 107 | intx = !!(cfg->regs[cfg->rc_regs->int_sts_reg] & |
| 108 | cfg->regs[cfg->rc_regs->int_en_reg]); |
| 109 | trace_aspeed_pcie_rc_intx_set_irq(cfg->id, irq, intx); |
| 110 | qemu_set_irq(rc->irq, intx); |
| 111 | } |
| 112 | |
| 113 | static int aspeed_pcie_rc_map_irq(PCIDevice *pci_dev, int irq_num) |
| 114 | { |
| 115 | return irq_num % PCI_NUM_PINS; |
| 116 | } |
| 117 | |
| 118 | static void aspeed_pcie_rc_msi_notify(AspeedPCIERcState *rc, uint64_t data) |
| 119 | { |
| 120 | AspeedPCIECfgState *cfg = |
| 121 | container_of(rc, AspeedPCIECfgState, rc); |
| 122 | uint32_t reg; |
| 123 | |
| 124 | /* Written data is the HW IRQ number */ |
| 125 | assert(data < ASPEED_PCIE_CFG_RC_MAX_MSI); |
| 126 | |
| 127 | reg = (data < 32) ? |
| 128 | cfg->rc_regs->msi_sts0_reg : cfg->rc_regs->msi_sts1_reg; |
| 129 | cfg->regs[reg] |= BIT(data % 32); |
| 130 | |
| 131 | trace_aspeed_pcie_rc_msi_set_irq(cfg->id, data, 1); |
| 132 | qemu_set_irq(rc->irq, 1); |
| 133 | } |
| 134 | |
| 135 | static void aspeed_pcie_rc_msi_write(void *opaque, hwaddr addr, uint64_t data, |
| 136 | unsigned int size) |
| 137 | { |
| 138 | AspeedPCIERcState *rc = ASPEED_PCIE_RC(opaque); |
| 139 | AspeedPCIECfgState *cfg = |
| 140 | container_of(rc, AspeedPCIECfgState, rc); |
| 141 | |
| 142 | trace_aspeed_pcie_rc_msi_notify(cfg->id, addr + rc->msi_addr, data); |
| 143 | aspeed_pcie_rc_msi_notify(rc, data); |
| 144 | } |
| 145 | |
| 146 | static const MemoryRegionOps aspeed_pcie_rc_msi_ops = { |
| 147 | .write = aspeed_pcie_rc_msi_write, |
| 148 | .read = NULL, |
| 149 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 150 | .valid = { |
| 151 | .min_access_size = 4, |
| 152 | .max_access_size = 4, |
| 153 | }, |
| 154 | .impl = { |
| 155 | .min_access_size = 4, |
| 156 | .max_access_size = 4, |
| 157 | }, |
| 158 | }; |
| 159 | |
| 160 | static AddressSpace *aspeed_pcie_rc_get_as(PCIBus *bus, void *opaque, int devfn) |
| 161 | { |
| 162 | AspeedPCIERcState *rc = ASPEED_PCIE_RC(opaque); |
| 163 | return &rc->iommu_as; |
| 164 | } |
| 165 | |
| 166 | static const PCIIOMMUOps aspeed_pcie_rc_iommu_ops = { |
| 167 | .get_address_space = aspeed_pcie_rc_get_as, |
| 168 | }; |
| 169 | |
| 170 | static void aspeed_pcie_rc_realize(DeviceState *dev, Error **errp) |
| 171 | { |
| 172 | PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); |
| 173 | AspeedPCIERcState *rc = ASPEED_PCIE_RC(dev); |
| 174 | AspeedPCIECfgState *cfg = |
| 175 | container_of(rc, AspeedPCIECfgState, rc); |
| 176 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
| 177 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 178 | g_autofree char *ioport_window_name = NULL; |
| 179 | g_autofree char *mmio_window_name = NULL; |
| 180 | g_autofree char *iommu_root_name = NULL; |
| 181 | g_autofree char *dram_alias_name = NULL; |
| 182 | g_autofree char *root_bus_name = NULL; |
| 183 | |
| 184 | /* PCI configuration space */ |
| 185 | pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); |
| 186 | sysbus_init_mmio(sbd, &pex->mmio); |
| 187 | |
| 188 | /* MMIO and IO region */ |
| 189 | memory_region_init(&rc->mmio, OBJECT(rc), "mmio", UINT64_MAX); |
| 190 | memory_region_init(&rc->io, OBJECT(rc), "io", 0x10000); |
| 191 | |
| 192 | mmio_window_name = g_strdup_printf("pcie.%d.mmio_window", cfg->id); |
| 193 | memory_region_init_io(&rc->mmio_window, OBJECT(rc), &unassigned_io_ops, |
| 194 | OBJECT(rc), mmio_window_name, UINT64_MAX); |
| 195 | ioport_window_name = g_strdup_printf("pcie.%d.ioport_window", cfg->id); |
| 196 | memory_region_init_io(&rc->io_window, OBJECT(rc), &unassigned_io_ops, |
| 197 | OBJECT(rc), ioport_window_name, 0x10000); |
| 198 | |
| 199 | memory_region_add_subregion(&rc->mmio_window, 0, &rc->mmio); |
| 200 | memory_region_add_subregion(&rc->io_window, 0, &rc->io); |
| 201 | sysbus_init_mmio(sbd, &rc->mmio_window); |
| 202 | sysbus_init_mmio(sbd, &rc->io_window); |
| 203 | |
| 204 | sysbus_init_irq(sbd, &rc->irq); |
| 205 | root_bus_name = g_strdup_printf("pcie.rc%d", cfg->id); |
| 206 | pci->bus = pci_register_root_bus(dev, root_bus_name, |
| 207 | aspeed_pcie_rc_set_irq, |
| 208 | aspeed_pcie_rc_map_irq, rc, &rc->mmio, |
| 209 | &rc->io, 0, 4, TYPE_PCIE_BUS); |
| 210 | pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; |
| 211 | |
| 212 | /* |
| 213 | * PCIe memory view setup |
| 214 | * |
| 215 | * Background: |
| 216 | * - On AST2700, all Root Complexes use the same MSI address. This MSI |
| 217 | * address is not normal system RAM - it is a PCI system memory address. |
| 218 | * If we map the MSI/MSI-X window into real system memory, a write from |
| 219 | * one EP can be seen by all RCs and wrongly trigger interrupts on them. |
| 220 | * |
| 221 | * Design: |
| 222 | * - MSI/MSI-X here is just a placeholder address so RC and EP can talk. |
| 223 | * We make a separate MMIO space (iommu_root) for the MSI window so the |
| 224 | * writes stay local to each RC. |
| 225 | * |
| 226 | * DMA: |
| 227 | * - EPs still need access to real system memory for DMA. We add a DRAM |
| 228 | * alias in the PCI space so DMA works as expected. |
| 229 | */ |
| 230 | iommu_root_name = g_strdup_printf("pcie.%d.iommu_root", cfg->id); |
| 231 | memory_region_init(&rc->iommu_root, OBJECT(rc), iommu_root_name, |
| 232 | UINT64_MAX); |
| 233 | address_space_init(&rc->iommu_as, &rc->iommu_root, iommu_root_name); |
| 234 | /* setup MSI */ |
| 235 | memory_region_init_io(&rc->msi_window, OBJECT(rc), |
| 236 | &aspeed_pcie_rc_msi_ops, rc, |
| 237 | "msi_window", 4); |
| 238 | memory_region_add_subregion(&rc->iommu_root, rc->msi_addr, |
| 239 | &rc->msi_window); |
| 240 | /* setup DRAM for DMA */ |
| 241 | assert(rc->dram_mr != NULL); |
| 242 | dram_alias_name = g_strdup_printf("pcie.%d.dram_alias", cfg->id); |
| 243 | memory_region_init_alias(&rc->dram_alias, OBJECT(rc), dram_alias_name, |
| 244 | rc->dram_mr, 0, memory_region_size(rc->dram_mr)); |
| 245 | memory_region_add_subregion(&rc->iommu_root, rc->dram_base, |
| 246 | &rc->dram_alias); |
| 247 | pci_setup_iommu(pci->bus, &aspeed_pcie_rc_iommu_ops, rc); |
| 248 | |
| 249 | /* setup root port */ |
| 250 | qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr); |
| 251 | qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id); |
| 252 | if (!qdev_realize(DEVICE(&rc->root_port), BUS(pci->bus), errp)) { |
| 253 | return; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge, |
| 258 | PCIBus *rootbus) |
| 259 | { |
| 260 | AspeedPCIERcState *rc = ASPEED_PCIE_RC(host_bridge); |
| 261 | AspeedPCIECfgState *cfg = |
| 262 | container_of(rc, AspeedPCIECfgState, rc); |
| 263 | |
| 264 | snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id); |
| 265 | |
| 266 | return rc->name; |
| 267 | } |
| 268 | |
| 269 | static void aspeed_pcie_rc_instance_init(Object *obj) |
| 270 | { |
| 271 | AspeedPCIERcState *rc = ASPEED_PCIE_RC(obj); |
| 272 | AspeedPCIERootPortState *root_port = &rc->root_port; |
| 273 | |
| 274 | object_initialize_child(obj, "root_port", root_port, |
| 275 | TYPE_ASPEED_PCIE_ROOT_PORT); |
| 276 | } |
| 277 | |
| 278 | static const Property aspeed_pcie_rc_props[] = { |
| 279 | DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0), |
| 280 | DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0), |
| 281 | DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0), |
| 282 | DEFINE_PROP_LINK("dram", AspeedPCIERcState, dram_mr, TYPE_MEMORY_REGION, |
| 283 | MemoryRegion *), |
| 284 | }; |
| 285 | |
| 286 | static void aspeed_pcie_rc_class_init(ObjectClass *klass, const void *data) |
| 287 | { |
| 288 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
| 289 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 290 | |
| 291 | dc->desc = "ASPEED PCIe RC"; |
| 292 | dc->realize = aspeed_pcie_rc_realize; |
| 293 | dc->fw_name = "pci"; |
| 294 | |
| 295 | hc->root_bus_path = aspeed_pcie_rc_root_bus_path; |
| 296 | device_class_set_props(dc, aspeed_pcie_rc_props); |
| 297 | |
| 298 | msi_nonbroken = true; |
| 299 | } |
| 300 | |
| 301 | /* |
| 302 | * PCIe Config |
| 303 | * |
| 304 | * AHB to PCIe Bus Bridge (H2X) |
| 305 | * |
| 306 | * On the AST2600: |
| 307 | * NOTE: rc_l is not supported by this model. |
| 308 | * - Registers 0x00 - 0x7F are shared by both PCIe0 (rc_l) and PCIe1 (rc_h). |
| 309 | * - Registers 0x80 - 0xBF are specific to PCIe0. |
| 310 | * - Registers 0xC0 - 0xFF are specific to PCIe1. |
| 311 | * |
| 312 | * On the AST2700: |
| 313 | * - The register range 0x00 - 0xFF is assigned to a single PCIe configuration. |
| 314 | * - There are three PCIe Root Complexes (RCs), each with its own dedicated H2X |
| 315 | * register set of size 0x100 (covering offsets 0x00 to 0xFF). |
| 316 | */ |
| 317 | |
| 318 | /* AST2600 */ |
| 319 | REG32(H2X_CTRL, 0x00) |
| 320 | FIELD(H2X_CTRL, CLEAR_RX, 4, 1) |
| 321 | REG32(H2X_TX_CLEAR, 0x08) |
| 322 | FIELD(H2X_TX_CLEAR, IDLE, 0, 1) |
| 323 | REG32(H2X_RDATA, 0x0C) |
| 324 | REG32(H2X_TX_DESC0, 0x10) |
| 325 | REG32(H2X_TX_DESC1, 0x14) |
| 326 | REG32(H2X_TX_DESC2, 0x18) |
| 327 | REG32(H2X_TX_DESC3, 0x1C) |
| 328 | REG32(H2X_TX_DATA, 0x20) |
| 329 | REG32(H2X_TX_STS, 0x24) |
| 330 | FIELD(H2X_TX_STS, IDLE, 31, 1) |
| 331 | FIELD(H2X_TX_STS, RC_L_TX_COMP, 24, 1) |
| 332 | FIELD(H2X_TX_STS, RC_H_TX_COMP, 25, 1) |
| 333 | FIELD(H2X_TX_STS, TRIG, 0, 1) |
| 334 | REG32(H2X_RC_H_CTRL, 0xC0) |
| 335 | REG32(H2X_RC_H_INT_EN, 0xC4) |
| 336 | REG32(H2X_RC_H_INT_STS, 0xC8) |
| 337 | SHARED_FIELD(H2X_RC_INT_INTDONE, 4, 1) |
| 338 | SHARED_FIELD(H2X_RC_INT_INTX, 0, 4) |
| 339 | REG32(H2X_RC_H_RDATA, 0xCC) |
| 340 | REG32(H2X_RC_H_MSI_EN0, 0xE0) |
| 341 | REG32(H2X_RC_H_MSI_EN1, 0xE4) |
| 342 | REG32(H2X_RC_H_MSI_STS0, 0xE8) |
| 343 | REG32(H2X_RC_H_MSI_STS1, 0xEC) |
| 344 | |
| 345 | /* AST2700 */ |
| 346 | REG32(H2X_CFGE_INT_STS, 0x08) |
| 347 | FIELD(H2X_CFGE_INT_STS, TX_IDEL, 0, 1) |
| 348 | FIELD(H2X_CFGE_INT_STS, RX_BUSY, 1, 1) |
| 349 | REG32(H2X_CFGI_TLP, 0x20) |
| 350 | FIELD(H2X_CFGI_TLP, ADDR, 0, 16) |
| 351 | FIELD(H2X_CFGI_TLP, BEN, 16, 4) |
| 352 | FIELD(H2X_CFGI_TLP, WR, 20, 1) |
| 353 | REG32(H2X_CFGI_WDATA, 0x24) |
| 354 | REG32(H2X_CFGI_CTRL, 0x28) |
| 355 | FIELD(H2X_CFGI_CTRL, FIRE, 0, 1) |
| 356 | REG32(H2X_CFGI_RDATA, 0x2C) |
| 357 | REG32(H2X_CFGE_TLP1, 0x30) |
| 358 | REG32(H2X_CFGE_TLPN, 0x34) |
| 359 | REG32(H2X_CFGE_CTRL, 0x38) |
| 360 | FIELD(H2X_CFGE_CTRL, FIRE, 0, 1) |
| 361 | REG32(H2X_CFGE_RDATA, 0x3C) |
| 362 | REG32(H2X_INT_EN, 0x40) |
| 363 | REG32(H2X_INT_STS, 0x48) |
| 364 | FIELD(H2X_INT_STS, INTX, 0, 4) |
| 365 | REG32(H2X_MSI_EN0, 0x50) |
| 366 | REG32(H2X_MSI_EN1, 0x54) |
| 367 | REG32(H2X_MSI_STS0, 0x58) |
| 368 | REG32(H2X_MSI_STS1, 0x5C) |
| 369 | |
| 370 | #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ |
| 371 | #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ |
| 372 | #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ |
| 373 | #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ |
| 374 | |
| 375 | #define PCIE_CFG_FMTTYPE_MASK(x) (((x) >> 24) & 0xff) |
| 376 | #define PCIE_CFG_BYTE_EN(x) ((x) & 0xf) |
| 377 | |
| 378 | static const AspeedPCIERegMap aspeed_regmap = { |
| 379 | .rc = { |
| 380 | .int_en_reg = R_H2X_RC_H_INT_EN, |
| 381 | .int_sts_reg = R_H2X_RC_H_INT_STS, |
| 382 | .msi_sts0_reg = R_H2X_RC_H_MSI_STS0, |
| 383 | .msi_sts1_reg = R_H2X_RC_H_MSI_STS1, |
| 384 | }, |
| 385 | }; |
| 386 | |
| 387 | static const AspeedPCIERegMap aspeed_2700_regmap = { |
| 388 | .rc = { |
| 389 | .int_en_reg = R_H2X_INT_EN, |
| 390 | .int_sts_reg = R_H2X_INT_STS, |
| 391 | .msi_sts0_reg = R_H2X_MSI_STS0, |
| 392 | .msi_sts1_reg = R_H2X_MSI_STS1, |
| 393 | }, |
| 394 | }; |
| 395 | |
| 396 | static uint64_t aspeed_pcie_cfg_read(void *opaque, hwaddr addr, |
| 397 | unsigned int size) |
| 398 | { |
| 399 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(opaque); |
| 400 | uint32_t reg = addr >> 2; |
| 401 | uint32_t value = 0; |
| 402 | |
| 403 | value = s->regs[reg]; |
| 404 | |
| 405 | trace_aspeed_pcie_cfg_read(s->id, addr, value); |
| 406 | |
| 407 | return value; |
| 408 | } |
| 409 | |
| 410 | static void aspeed_pcie_cfg_translate_write(uint8_t byte_en, uint32_t *addr, |
| 411 | uint64_t *val, int *len) |
| 412 | { |
| 413 | uint64_t packed_val = 0; |
| 414 | int first_bit = -1; |
| 415 | int index = 0; |
| 416 | int i; |
| 417 | |
| 418 | *len = ctpop8(byte_en); |
| 419 | |
| 420 | if (*len == 0 || *len > 4) { |
| 421 | qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid byte enable: 0x%x\n", |
| 422 | __func__, byte_en); |
| 423 | return; |
| 424 | } |
| 425 | |
| 426 | /* Special case: full 4-byte write must be 4-byte aligned */ |
| 427 | if (byte_en == 0x0f) { |
| 428 | if ((*addr & 0x3) != 0) { |
| 429 | qemu_log_mask(LOG_GUEST_ERROR, |
| 430 | "%s: 4-byte write not 4-byte aligned: addr=0x%x\n", |
| 431 | __func__, *addr); |
| 432 | return; |
| 433 | } |
| 434 | *val &= 0xffffffffULL; |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | for (i = 0; i < 4; i++) { |
| 439 | if (byte_en & (1 << i)) { |
| 440 | if (first_bit < 0) { |
| 441 | first_bit = i; |
| 442 | } |
| 443 | packed_val |= ((*val >> (i * 8)) & 0xff) << (index * 8); |
| 444 | index++; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | *addr += first_bit; |
| 449 | *val = packed_val; |
| 450 | } |
| 451 | |
| 452 | static void aspeed_pcie_cfg_readwrite(AspeedPCIECfgState *s, |
| 453 | const AspeedPCIECfgTxDesc *desc) |
| 454 | { |
| 455 | AspeedPCIERcState *rc = &s->rc; |
| 456 | PCIHostState *pci = NULL; |
| 457 | PCIDevice *pdev = NULL; |
| 458 | uint32_t cfg_addr; |
| 459 | uint32_t offset; |
| 460 | uint8_t byte_en; |
| 461 | bool is_write; |
| 462 | uint8_t devfn; |
| 463 | uint64_t val; |
| 464 | uint8_t bus; |
| 465 | int len; |
| 466 | |
| 467 | val = ~0; |
| 468 | is_write = !!(desc->desc0 & BIT(30)); |
| 469 | cfg_addr = desc->desc2; |
| 470 | |
| 471 | bus = (cfg_addr >> 24) & 0xff; |
| 472 | devfn = (cfg_addr >> 16) & 0xff; |
| 473 | offset = cfg_addr & 0xffc; |
| 474 | |
| 475 | pci = PCI_HOST_BRIDGE(rc); |
| 476 | pdev = pci_find_device(pci->bus, bus, devfn); |
| 477 | if (!pdev) { |
| 478 | s->regs[desc->rdata_reg] = ~0; |
| 479 | goto out; |
| 480 | } |
| 481 | |
| 482 | switch (PCIE_CFG_FMTTYPE_MASK(desc->desc0)) { |
| 483 | case TLP_FMTTYPE_CFGWR0: |
| 484 | case TLP_FMTTYPE_CFGWR1: |
| 485 | byte_en = PCIE_CFG_BYTE_EN(desc->desc1); |
| 486 | val = desc->wdata; |
| 487 | aspeed_pcie_cfg_translate_write(byte_en, &offset, &val, &len); |
| 488 | pci_host_config_write_common(pdev, offset, pci_config_size(pdev), |
| 489 | val, len); |
| 490 | break; |
| 491 | case TLP_FMTTYPE_CFGRD0: |
| 492 | case TLP_FMTTYPE_CFGRD1: |
| 493 | val = pci_host_config_read_common(pdev, offset, |
| 494 | pci_config_size(pdev), 4); |
| 495 | s->regs[desc->rdata_reg] = val; |
| 496 | break; |
| 497 | default: |
| 498 | qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid CFG type. DESC0=0x%x\n", |
| 499 | __func__, desc->desc0); |
| 500 | } |
| 501 | |
| 502 | out: |
| 503 | trace_aspeed_pcie_cfg_rw(s->id, is_write ? "write" : "read", bus, devfn, |
| 504 | cfg_addr, val); |
| 505 | } |
| 506 | |
| 507 | static void aspeed_pcie_cfg_write(void *opaque, hwaddr addr, uint64_t data, |
| 508 | unsigned int size) |
| 509 | { |
| 510 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(opaque); |
| 511 | AspeedPCIECfgTxDesc desc; |
| 512 | uint32_t reg = addr >> 2; |
| 513 | uint32_t rc_reg; |
| 514 | |
| 515 | trace_aspeed_pcie_cfg_write(s->id, addr, data); |
| 516 | |
| 517 | switch (reg) { |
| 518 | case R_H2X_CTRL: |
| 519 | if (data & R_H2X_CTRL_CLEAR_RX_MASK) { |
| 520 | s->regs[R_H2X_RDATA] = ~0; |
| 521 | } |
| 522 | break; |
| 523 | case R_H2X_TX_CLEAR: |
| 524 | if (data & R_H2X_TX_CLEAR_IDLE_MASK) { |
| 525 | s->regs[R_H2X_TX_STS] &= ~R_H2X_TX_STS_IDLE_MASK; |
| 526 | } |
| 527 | break; |
| 528 | case R_H2X_TX_STS: |
| 529 | if (data & R_H2X_TX_STS_TRIG_MASK) { |
| 530 | desc.desc0 = s->regs[R_H2X_TX_DESC0]; |
| 531 | desc.desc1 = s->regs[R_H2X_TX_DESC1]; |
| 532 | desc.desc2 = s->regs[R_H2X_TX_DESC2]; |
| 533 | desc.desc3 = s->regs[R_H2X_TX_DESC3]; |
| 534 | desc.wdata = s->regs[R_H2X_TX_DATA]; |
| 535 | desc.rdata_reg = R_H2X_RC_H_RDATA; |
| 536 | aspeed_pcie_cfg_readwrite(s, &desc); |
| 537 | rc_reg = s->rc_regs->int_sts_reg; |
| 538 | s->regs[rc_reg] |= H2X_RC_INT_INTDONE_MASK; |
| 539 | s->regs[R_H2X_TX_STS] |= |
| 540 | BIT(R_H2X_TX_STS_RC_H_TX_COMP_SHIFT); |
| 541 | s->regs[R_H2X_TX_STS] |= R_H2X_TX_STS_IDLE_MASK; |
| 542 | } |
| 543 | break; |
| 544 | /* preserve INTx status */ |
| 545 | case R_H2X_RC_H_INT_STS: |
| 546 | if (data & H2X_RC_INT_INTDONE_MASK) { |
| 547 | s->regs[R_H2X_TX_STS] &= ~R_H2X_TX_STS_RC_H_TX_COMP_MASK; |
| 548 | } |
| 549 | s->regs[reg] &= ~data | H2X_RC_INT_INTX_MASK; |
| 550 | break; |
| 551 | /* |
| 552 | * These status registers are used for notify sources ISR are executed. |
| 553 | * If one source ISR is executed, it will clear one bit. |
| 554 | * If it clear all bits, it means to initialize this register status |
| 555 | * rather than sources ISR are executed. |
| 556 | */ |
| 557 | case R_H2X_RC_H_MSI_STS0: |
| 558 | case R_H2X_RC_H_MSI_STS1: |
| 559 | if (data == 0) { |
| 560 | return ; |
| 561 | } |
| 562 | |
| 563 | s->regs[reg] &= ~data; |
| 564 | if (data == 0xffffffff) { |
| 565 | return; |
| 566 | } |
| 567 | |
| 568 | if (!s->regs[R_H2X_RC_H_MSI_STS0] && |
| 569 | !s->regs[R_H2X_RC_H_MSI_STS1]) { |
| 570 | trace_aspeed_pcie_rc_msi_clear_irq(s->id, 0); |
| 571 | qemu_set_irq(s->rc.irq, 0); |
| 572 | } |
| 573 | break; |
| 574 | default: |
| 575 | s->regs[reg] = data; |
| 576 | break; |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | static const MemoryRegionOps aspeed_pcie_cfg_ops = { |
| 581 | .read = aspeed_pcie_cfg_read, |
| 582 | .write = aspeed_pcie_cfg_write, |
| 583 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 584 | .valid = { |
| 585 | .min_access_size = 1, |
| 586 | .max_access_size = 4, |
| 587 | }, |
| 588 | }; |
| 589 | |
| 590 | static void aspeed_pcie_cfg_instance_init(Object *obj) |
| 591 | { |
| 592 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(obj); |
| 593 | |
| 594 | object_initialize_child(obj, "rc", &s->rc, TYPE_ASPEED_PCIE_RC); |
| 595 | object_property_add_alias(obj, "dram", OBJECT(&s->rc), "dram"); |
| 596 | object_property_add_alias(obj, "dram-base", OBJECT(&s->rc), "dram-base"); |
| 597 | |
| 598 | return; |
| 599 | } |
| 600 | |
| 601 | static void aspeed_pcie_cfg_reset_hold(Object *obj, ResetType type) |
| 602 | { |
| 603 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(obj); |
| 604 | AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_GET_CLASS(s); |
| 605 | |
| 606 | memset(s->regs, 0, apc->nr_regs << 2); |
| 607 | memset(s->tlpn_fifo, 0, sizeof(s->tlpn_fifo)); |
| 608 | s->tlpn_idx = 0; |
| 609 | } |
| 610 | |
| 611 | static void aspeed_pcie_cfg_realize(DeviceState *dev, Error **errp) |
| 612 | { |
| 613 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 614 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(dev); |
| 615 | AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_GET_CLASS(s); |
| 616 | g_autofree char *name = NULL; |
| 617 | |
| 618 | s->rc_regs = &apc->reg_map->rc; |
| 619 | s->regs = g_new(uint32_t, apc->nr_regs); |
| 620 | name = g_strdup_printf(TYPE_ASPEED_PCIE_CFG ".regs.%d", s->id); |
| 621 | memory_region_init_io(&s->mmio, OBJECT(s), apc->reg_ops, s, name, |
| 622 | apc->nr_regs << 2); |
| 623 | sysbus_init_mmio(sbd, &s->mmio); |
| 624 | |
| 625 | object_property_set_int(OBJECT(&s->rc), "rp-addr", |
| 626 | apc->rc_rp_addr, |
| 627 | &error_abort); |
| 628 | object_property_set_int(OBJECT(&s->rc), "msi-addr", |
| 629 | apc->rc_msi_addr, |
| 630 | &error_abort); |
| 631 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rc), errp)) { |
| 632 | return; |
| 633 | } |
| 634 | } |
| 635 | |
| 636 | static void aspeed_pcie_cfg_unrealize(DeviceState *dev) |
| 637 | { |
| 638 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(dev); |
| 639 | |
| 640 | g_free(s->regs); |
| 641 | s->regs = NULL; |
| 642 | } |
| 643 | |
| 644 | static const Property aspeed_pcie_cfg_props[] = { |
| 645 | DEFINE_PROP_UINT32("id", AspeedPCIECfgState, id, 0), |
| 646 | }; |
| 647 | |
| 648 | static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data) |
| 649 | { |
| 650 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 651 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 652 | AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_CLASS(klass); |
| 653 | |
| 654 | dc->desc = "ASPEED PCIe Config"; |
| 655 | dc->realize = aspeed_pcie_cfg_realize; |
| 656 | dc->unrealize = aspeed_pcie_cfg_unrealize; |
| 657 | rc->phases.hold = aspeed_pcie_cfg_reset_hold; |
| 658 | device_class_set_props(dc, aspeed_pcie_cfg_props); |
| 659 | |
| 660 | apc->reg_ops = &aspeed_pcie_cfg_ops; |
| 661 | apc->reg_map = &aspeed_regmap; |
| 662 | apc->nr_regs = 0x100 >> 2; |
| 663 | apc->rc_msi_addr = 0x1e77005C; |
| 664 | apc->rc_rp_addr = PCI_DEVFN(8, 0); |
| 665 | } |
| 666 | |
| 667 | static void aspeed_2700_pcie_cfg_write(void *opaque, hwaddr addr, |
| 668 | uint64_t data, unsigned int size) |
| 669 | { |
| 670 | AspeedPCIECfgState *s = ASPEED_PCIE_CFG(opaque); |
| 671 | AspeedPCIECfgTxDesc desc; |
| 672 | uint32_t reg = addr >> 2; |
| 673 | |
| 674 | trace_aspeed_pcie_cfg_write(s->id, addr, data); |
| 675 | |
| 676 | switch (reg) { |
| 677 | case R_H2X_CFGE_INT_STS: |
| 678 | if (data & R_H2X_CFGE_INT_STS_TX_IDEL_MASK) { |
| 679 | s->regs[R_H2X_CFGE_INT_STS] &= ~R_H2X_CFGE_INT_STS_TX_IDEL_MASK; |
| 680 | } |
| 681 | |
| 682 | if (data & R_H2X_CFGE_INT_STS_RX_BUSY_MASK) { |
| 683 | s->regs[R_H2X_CFGE_INT_STS] &= ~R_H2X_CFGE_INT_STS_RX_BUSY_MASK; |
| 684 | } |
| 685 | break; |
| 686 | case R_H2X_CFGI_CTRL: |
| 687 | if (data & R_H2X_CFGI_CTRL_FIRE_MASK) { |
| 688 | /* |
| 689 | * Internal access to bridge |
| 690 | * Type and BDF are 0 |
| 691 | */ |
| 692 | desc.desc0 = 0x04000001 | |
| 693 | (ARRAY_FIELD_EX32(s->regs, H2X_CFGI_TLP, WR) << 30); |
| 694 | desc.desc1 = 0x00401000 | |
| 695 | ARRAY_FIELD_EX32(s->regs, H2X_CFGI_TLP, BEN); |
| 696 | desc.desc2 = 0x00000000 | |
| 697 | ARRAY_FIELD_EX32(s->regs, H2X_CFGI_TLP, ADDR); |
| 698 | desc.wdata = s->regs[R_H2X_CFGI_WDATA]; |
| 699 | desc.rdata_reg = R_H2X_CFGI_RDATA; |
| 700 | aspeed_pcie_cfg_readwrite(s, &desc); |
| 701 | } |
| 702 | break; |
| 703 | case R_H2X_CFGE_TLPN: |
| 704 | s->tlpn_fifo[s->tlpn_idx] = data; |
| 705 | s->tlpn_idx = (s->tlpn_idx + 1) % ARRAY_SIZE(s->tlpn_fifo); |
| 706 | break; |
| 707 | case R_H2X_CFGE_CTRL: |
| 708 | if (data & R_H2X_CFGE_CTRL_FIRE_MASK) { |
| 709 | desc.desc0 = s->regs[R_H2X_CFGE_TLP1]; |
| 710 | desc.desc1 = s->tlpn_fifo[0]; |
| 711 | desc.desc2 = s->tlpn_fifo[1]; |
| 712 | desc.wdata = s->tlpn_fifo[2]; |
| 713 | desc.rdata_reg = R_H2X_CFGE_RDATA; |
| 714 | aspeed_pcie_cfg_readwrite(s, &desc); |
| 715 | s->regs[R_H2X_CFGE_INT_STS] |= R_H2X_CFGE_INT_STS_TX_IDEL_MASK; |
| 716 | s->regs[R_H2X_CFGE_INT_STS] |= R_H2X_CFGE_INT_STS_RX_BUSY_MASK; |
| 717 | s->tlpn_idx = 0; |
| 718 | } |
| 719 | break; |
| 720 | |
| 721 | case R_H2X_INT_STS: |
| 722 | s->regs[reg] &= ~data | R_H2X_INT_STS_INTX_MASK; |
| 723 | break; |
| 724 | /* |
| 725 | * These status registers are used for notify sources ISR are executed. |
| 726 | * If one source ISR is executed, it will clear one bit. |
| 727 | * If it clear all bits, it means to initialize this register status |
| 728 | * rather than sources ISR are executed. |
| 729 | */ |
| 730 | case R_H2X_MSI_STS0: |
| 731 | case R_H2X_MSI_STS1: |
| 732 | if (data == 0) { |
| 733 | return ; |
| 734 | } |
| 735 | |
| 736 | s->regs[reg] &= ~data; |
| 737 | if (data == 0xffffffff) { |
| 738 | return; |
| 739 | } |
| 740 | |
| 741 | if (!s->regs[R_H2X_MSI_STS0] && |
| 742 | !s->regs[R_H2X_MSI_STS1]) { |
| 743 | trace_aspeed_pcie_rc_msi_clear_irq(s->id, 0); |
| 744 | qemu_set_irq(s->rc.irq, 0); |
| 745 | } |
| 746 | break; |
| 747 | default: |
| 748 | s->regs[reg] = data; |
| 749 | break; |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | static const MemoryRegionOps aspeed_2700_pcie_cfg_ops = { |
| 754 | .read = aspeed_pcie_cfg_read, |
| 755 | .write = aspeed_2700_pcie_cfg_write, |
| 756 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 757 | .valid = { |
| 758 | .min_access_size = 1, |
| 759 | .max_access_size = 4, |
| 760 | }, |
| 761 | }; |
| 762 | |
| 763 | static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass, |
| 764 | const void *data) |
| 765 | { |
| 766 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 767 | AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_CLASS(klass); |
| 768 | |
| 769 | dc->desc = "ASPEED 2700 PCIe Config"; |
| 770 | apc->reg_ops = &aspeed_2700_pcie_cfg_ops; |
| 771 | apc->reg_map = &aspeed_2700_regmap; |
| 772 | apc->nr_regs = 0x100 >> 2; |
| 773 | apc->rc_msi_addr = 0x000000F0; |
| 774 | apc->rc_rp_addr = PCI_DEVFN(0, 0); |
| 775 | } |
| 776 | |
| 777 | /* |
| 778 | * PCIe PHY |
| 779 | * |
| 780 | * PCIe Host Controller (PCIEH) |
| 781 | */ |
| 782 | |
| 783 | /* AST2600 */ |
| 784 | REG32(PEHR_ID, 0x00) |
| 785 | FIELD(PEHR_ID, DEV, 16, 16) |
| 786 | REG32(PEHR_CLASS_CODE, 0x04) |
| 787 | REG32(PEHR_DATALINK, 0x10) |
| 788 | REG32(PEHR_PROTECT, 0x7C) |
| 789 | FIELD(PEHR_PROTECT, LOCK, 0, 8) |
| 790 | REG32(PEHR_LINK, 0xC0) |
| 791 | FIELD(PEHR_LINK, STS, 5, 1) |
| 792 | |
| 793 | /* AST2700 */ |
| 794 | REG32(PEHR_2700_LINK_GEN2, 0x344) |
| 795 | FIELD(PEHR_2700_LINK_GEN2, STS, 18, 1) |
| 796 | REG32(PEHR_2700_LINK_GEN4, 0x358) |
| 797 | FIELD(PEHR_2700_LINK_GEN4, STS, 8, 1) |
| 798 | |
| 799 | #define ASPEED_PCIE_PHY_UNLOCK 0xA8 |
| 800 | |
| 801 | static uint64_t aspeed_pcie_phy_read(void *opaque, hwaddr addr, |
| 802 | unsigned int size) |
| 803 | { |
| 804 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(opaque); |
| 805 | uint32_t reg = addr >> 2; |
| 806 | uint32_t value = 0; |
| 807 | |
| 808 | value = s->regs[reg]; |
| 809 | |
| 810 | trace_aspeed_pcie_phy_read(s->id, addr, value); |
| 811 | |
| 812 | return value; |
| 813 | } |
| 814 | |
| 815 | static void aspeed_pcie_phy_write(void *opaque, hwaddr addr, uint64_t data, |
| 816 | unsigned int size) |
| 817 | { |
| 818 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(opaque); |
| 819 | uint32_t reg = addr >> 2; |
| 820 | |
| 821 | trace_aspeed_pcie_phy_write(s->id, addr, data); |
| 822 | |
| 823 | switch (reg) { |
| 824 | case R_PEHR_PROTECT: |
| 825 | data &= R_PEHR_PROTECT_LOCK_MASK; |
| 826 | s->regs[reg] = !!(data == ASPEED_PCIE_PHY_UNLOCK); |
| 827 | break; |
| 828 | default: |
| 829 | s->regs[reg] = data; |
| 830 | break; |
| 831 | } |
| 832 | } |
| 833 | |
| 834 | static const MemoryRegionOps aspeed_pcie_phy_ops = { |
| 835 | .read = aspeed_pcie_phy_read, |
| 836 | .write = aspeed_pcie_phy_write, |
| 837 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 838 | .valid = { |
| 839 | .min_access_size = 1, |
| 840 | .max_access_size = 4, |
| 841 | }, |
| 842 | }; |
| 843 | |
| 844 | static void aspeed_pcie_phy_reset_hold(Object *obj, ResetType type) |
| 845 | { |
| 846 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(obj); |
| 847 | AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_GET_CLASS(s); |
| 848 | |
| 849 | memset(s->regs, 0, apc->nr_regs << 2); |
| 850 | |
| 851 | s->regs[R_PEHR_ID] = |
| 852 | (0x1150 << R_PEHR_ID_DEV_SHIFT) | PCI_VENDOR_ID_ASPEED; |
| 853 | s->regs[R_PEHR_CLASS_CODE] = 0x06040006; |
| 854 | s->regs[R_PEHR_DATALINK] = 0xD7040022; |
| 855 | s->regs[R_PEHR_LINK] = R_PEHR_LINK_STS_MASK; |
| 856 | } |
| 857 | |
| 858 | static void aspeed_pcie_phy_realize(DeviceState *dev, Error **errp) |
| 859 | { |
| 860 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(dev); |
| 861 | AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_GET_CLASS(s); |
| 862 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 863 | g_autofree char *name = NULL; |
| 864 | |
| 865 | s->regs = g_new(uint32_t, apc->nr_regs); |
| 866 | name = g_strdup_printf(TYPE_ASPEED_PCIE_PHY ".regs.%d", s->id); |
| 867 | memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_pcie_phy_ops, s, name, |
| 868 | apc->nr_regs << 2); |
| 869 | sysbus_init_mmio(sbd, &s->mmio); |
| 870 | } |
| 871 | |
| 872 | static void aspeed_pcie_phy_unrealize(DeviceState *dev) |
| 873 | { |
| 874 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(dev); |
| 875 | |
| 876 | g_free(s->regs); |
| 877 | s->regs = NULL; |
| 878 | } |
| 879 | |
| 880 | static const Property aspeed_pcie_phy_props[] = { |
| 881 | DEFINE_PROP_UINT32("id", AspeedPCIEPhyState, id, 0), |
| 882 | }; |
| 883 | |
| 884 | static void aspeed_pcie_phy_class_init(ObjectClass *klass, const void *data) |
| 885 | { |
| 886 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 887 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 888 | AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_CLASS(klass); |
| 889 | |
| 890 | dc->desc = "ASPEED PCIe Phy"; |
| 891 | dc->realize = aspeed_pcie_phy_realize; |
| 892 | dc->unrealize = aspeed_pcie_phy_unrealize; |
| 893 | rc->phases.hold = aspeed_pcie_phy_reset_hold; |
| 894 | device_class_set_props(dc, aspeed_pcie_phy_props); |
| 895 | |
| 896 | apc->nr_regs = 0x100 >> 2; |
| 897 | } |
| 898 | |
| 899 | static void aspeed_2700_pcie_phy_reset_hold(Object *obj, ResetType type) |
| 900 | { |
| 901 | AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(obj); |
| 902 | AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_GET_CLASS(s); |
| 903 | |
| 904 | memset(s->regs, 0, apc->nr_regs << 2); |
| 905 | |
| 906 | s->regs[R_PEHR_ID] = |
| 907 | (0x1150 << R_PEHR_ID_DEV_SHIFT) | PCI_VENDOR_ID_ASPEED; |
| 908 | s->regs[R_PEHR_CLASS_CODE] = 0x06040011; |
| 909 | s->regs[R_PEHR_2700_LINK_GEN2] = R_PEHR_2700_LINK_GEN2_STS_MASK; |
| 910 | s->regs[R_PEHR_2700_LINK_GEN4] = R_PEHR_2700_LINK_GEN4_STS_MASK; |
| 911 | } |
| 912 | |
| 913 | static void aspeed_2700_pcie_phy_class_init(ObjectClass *klass, |
| 914 | const void *data) |
| 915 | { |
| 916 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 917 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 918 | AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_CLASS(klass); |
| 919 | |
| 920 | dc->desc = "ASPEED AST2700 PCIe Phy"; |
| 921 | rc->phases.hold = aspeed_2700_pcie_phy_reset_hold; |
| 922 | |
| 923 | apc->nr_regs = 0x800 >> 2; |
| 924 | } |
| 925 | |
| 926 | static const TypeInfo aspeed_pcie_types[] = { |
| 927 | { |
| 928 | .name = TYPE_ASPEED_PCIE_RC, |
| 929 | .parent = TYPE_PCIE_HOST_BRIDGE, |
| 930 | .instance_size = sizeof(AspeedPCIERcState), |
| 931 | .instance_init = aspeed_pcie_rc_instance_init, |
| 932 | .class_init = aspeed_pcie_rc_class_init, |
| 933 | }, |
| 934 | { |
| 935 | .name = TYPE_ASPEED_PCIE_ROOT_PORT, |
| 936 | .parent = TYPE_PCIE_ROOT_PORT, |
| 937 | .instance_size = sizeof(AspeedPCIERootPortState), |
| 938 | .class_init = aspeed_pcie_root_port_class_init, |
| 939 | }, |
| 940 | { |
| 941 | .name = TYPE_ASPEED_PCIE_CFG, |
| 942 | .parent = TYPE_SYS_BUS_DEVICE, |
| 943 | .instance_init = aspeed_pcie_cfg_instance_init, |
| 944 | .instance_size = sizeof(AspeedPCIECfgState), |
| 945 | .class_init = aspeed_pcie_cfg_class_init, |
| 946 | .class_size = sizeof(AspeedPCIECfgClass), |
| 947 | }, |
| 948 | { |
| 949 | .name = TYPE_ASPEED_PCIE_PHY, |
| 950 | .parent = TYPE_SYS_BUS_DEVICE, |
| 951 | .instance_size = sizeof(AspeedPCIEPhyState), |
| 952 | .class_init = aspeed_pcie_phy_class_init, |
| 953 | .class_size = sizeof(AspeedPCIEPhyClass), |
| 954 | }, |
| 955 | { |
| 956 | .name = TYPE_ASPEED_2700_PCIE_PHY, |
| 957 | .parent = TYPE_ASPEED_PCIE_PHY, |
| 958 | .class_init = aspeed_2700_pcie_phy_class_init, |
| 959 | }, |
| 960 | { |
| 961 | .name = TYPE_ASPEED_2700_PCIE_CFG, |
| 962 | .parent = TYPE_ASPEED_PCIE_CFG, |
| 963 | .class_init = aspeed_2700_pcie_cfg_class_init, |
| 964 | } |
| 965 | |
| 966 | }; |
| 967 | |
| 968 | DEFINE_TYPES(aspeed_pcie_types) |
| 969 |