| 1 | /* |
| 2 | * bonito north bridge support |
| 3 | * |
| 4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) |
| 5 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) |
| 6 | * |
| 7 | * This code is licensed under the GNU GPL v2. |
| 8 | * |
| 9 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 10 | * GNU GPL, version 2 or (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * fuloong 2e mini pc has a bonito north bridge. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? |
| 19 | * |
| 20 | * devfn pci_slot<<3 + funno |
| 21 | * one pci bus can have 32 devices and each device can have 8 functions. |
| 22 | * |
| 23 | * In bonito north bridge, pci slot = IDSEL bit - 12. |
| 24 | * For example, PCI_IDSEL_VIA686B = 17, |
| 25 | * pci slot = 17-12=5 |
| 26 | * |
| 27 | * so |
| 28 | * VT686B_FUN0's devfn = (5<<3)+0 |
| 29 | * VT686B_FUN1's devfn = (5<<3)+1 |
| 30 | * |
| 31 | * qemu also uses pci address for north bridge to access pci config register. |
| 32 | * bus_no [23:16] |
| 33 | * dev_no [15:11] |
| 34 | * fun_no [10:8] |
| 35 | * reg_no [7:2] |
| 36 | * |
| 37 | * so function bonito_sbridge_pciaddr for the translation from |
| 38 | * north bridge address to pci address. |
| 39 | */ |
| 40 | |
| 41 | #include "qemu/osdep.h" |
| 42 | #include "qemu/units.h" |
| 43 | #include "qapi/error.h" |
| 44 | #include "qemu/error-report.h" |
| 45 | #include "hw/pci/pci_device.h" |
| 46 | #include "hw/core/irq.h" |
| 47 | #include "hw/mips/mips.h" |
| 48 | #include "hw/pci-host/bonito.h" |
| 49 | #include "hw/pci/pci_host.h" |
| 50 | #include "migration/vmstate.h" |
| 51 | #include "system/runstate.h" |
| 52 | #include "hw/misc/unimp.h" |
| 53 | #include "hw/core/registerfields.h" |
| 54 | #include "qom/object.h" |
| 55 | #include "trace.h" |
| 56 | |
| 57 | /* #define DEBUG_BONITO */ |
| 58 | |
| 59 | #ifdef DEBUG_BONITO |
| 60 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
| 61 | #else |
| 62 | #define DPRINTF(fmt, ...) |
| 63 | #endif |
| 64 | |
| 65 | /* from linux source code. include/asm-mips/mips-boards/bonito64.h*/ |
| 66 | #define BONITO_BOOT_BASE 0x1fc00000 |
| 67 | #define BONITO_BOOT_SIZE 0x00100000 |
| 68 | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) |
| 69 | #define BONITO_FLASH_BASE 0x1c000000 |
| 70 | #define BONITO_FLASH_SIZE 0x03000000 |
| 71 | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) |
| 72 | #define BONITO_SOCKET_BASE 0x1f800000 |
| 73 | #define BONITO_SOCKET_SIZE 0x00400000 |
| 74 | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) |
| 75 | #define BONITO_REG_BASE 0x1fe00000 |
| 76 | #define BONITO_REG_SIZE 0x00040000 |
| 77 | #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) |
| 78 | #define BONITO_DEV_BASE 0x1ff00000 |
| 79 | #define BONITO_DEV_SIZE 0x00100000 |
| 80 | #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) |
| 81 | #define BONITO_PCILO_BASE 0x10000000 |
| 82 | #define BONITO_PCILO_BASE_VA 0xb0000000 |
| 83 | #define BONITO_PCILO_SIZE 0x0c000000 |
| 84 | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) |
| 85 | #define BONITO_PCILO0_BASE 0x10000000 |
| 86 | #define BONITO_PCILO1_BASE 0x14000000 |
| 87 | #define BONITO_PCILO2_BASE 0x18000000 |
| 88 | #define BONITO_PCIHI_BASE 0x20000000 |
| 89 | #define BONITO_PCIHI_SIZE 0x60000000 |
| 90 | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) |
| 91 | #define BONITO_PCIIO_BASE 0x1fd00000 |
| 92 | #define BONITO_PCIIO_BASE_VA 0xbfd00000 |
| 93 | #define BONITO_PCIIO_SIZE 0x00010000 |
| 94 | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) |
| 95 | #define BONITO_PCICFG_BASE 0x1fe80000 |
| 96 | #define BONITO_PCICFG_SIZE 0x00080000 |
| 97 | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) |
| 98 | |
| 99 | |
| 100 | #define BONITO_PCICONFIGBASE 0x00 |
| 101 | #define BONITO_REGBASE 0x100 |
| 102 | |
| 103 | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) |
| 104 | #define BONITO_PCICONFIG_SIZE (0x100) |
| 105 | |
| 106 | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) |
| 107 | #define BONITO_INTERNAL_REG_SIZE (0x70) |
| 108 | |
| 109 | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) |
| 110 | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) |
| 111 | |
| 112 | |
| 113 | |
| 114 | /* 1. Bonito h/w Configuration */ |
| 115 | /* Power on register */ |
| 116 | |
| 117 | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ |
| 118 | |
| 119 | /* PCI configuration register */ |
| 120 | #define BONITO_BONGENCFG_OFFSET 0x4 |
| 121 | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ |
| 122 | REG32(BONGENCFG, 0x104) |
| 123 | FIELD(BONGENCFG, DEBUGMODE, 0, 1) |
| 124 | FIELD(BONGENCFG, SNOOP, 1, 1) |
| 125 | FIELD(BONGENCFG, CPUSELFRESET, 2, 1) |
| 126 | FIELD(BONGENCFG, BYTESWAP, 6, 1) |
| 127 | FIELD(BONGENCFG, UNCACHED, 7, 1) |
| 128 | FIELD(BONGENCFG, PREFETCH, 8, 1) |
| 129 | FIELD(BONGENCFG, WRITEBEHIND, 9, 1) |
| 130 | FIELD(BONGENCFG, PCIQUEUE, 12, 1) |
| 131 | |
| 132 | /* 2. IO & IDE configuration */ |
| 133 | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ |
| 134 | |
| 135 | /* 3. IO & IDE configuration */ |
| 136 | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ |
| 137 | |
| 138 | /* 4. PCI address map control */ |
| 139 | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ |
| 140 | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ |
| 141 | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ |
| 142 | |
| 143 | /* 5. ICU & GPIO regs */ |
| 144 | /* GPIO Regs - r/w */ |
| 145 | #define BONITO_GPIODATA_OFFSET 0x1c |
| 146 | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ |
| 147 | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ |
| 148 | |
| 149 | /* ICU Configuration Regs - r/w */ |
| 150 | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ |
| 151 | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ |
| 152 | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ |
| 153 | |
| 154 | /* ICU Enable Regs - IntEn & IntISR are r/o. */ |
| 155 | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ |
| 156 | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ |
| 157 | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ |
| 158 | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ |
| 159 | |
| 160 | /* PCI mail boxes */ |
| 161 | #define BONITO_PCIMAIL0_OFFSET 0x40 |
| 162 | #define BONITO_PCIMAIL1_OFFSET 0x44 |
| 163 | #define BONITO_PCIMAIL2_OFFSET 0x48 |
| 164 | #define BONITO_PCIMAIL3_OFFSET 0x4c |
| 165 | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ |
| 166 | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ |
| 167 | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ |
| 168 | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ |
| 169 | |
| 170 | /* 6. PCI cache */ |
| 171 | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ |
| 172 | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ |
| 173 | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ |
| 174 | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ |
| 175 | |
| 176 | /* 7. other*/ |
| 177 | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ |
| 178 | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ |
| 179 | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ |
| 180 | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ |
| 181 | |
| 182 | #define BONITO_REGS (0x70 >> 2) |
| 183 | |
| 184 | /* PCI config for south bridge. type 0 */ |
| 185 | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ |
| 186 | #define BONITO_PCICONF_IDSEL_OFFSET 11 |
| 187 | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ |
| 188 | #define BONITO_PCICONF_FUN_OFFSET 8 |
| 189 | #define BONITO_PCICONF_REG_MASK_DS (~3) /* Per datasheet */ |
| 190 | #define BONITO_PCICONF_REG_MASK_HW 0xff /* As seen running PMON */ |
| 191 | #define BONITO_PCICONF_REG_OFFSET 0 |
| 192 | |
| 193 | |
| 194 | /* idsel BIT = pci slot number +12 */ |
| 195 | #define PCI_SLOT_BASE 12 |
| 196 | #define PCI_IDSEL_VIA686B_BIT (17) |
| 197 | #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) |
| 198 | |
| 199 | #define PCI_ADDR(busno , devno , funno , regno) \ |
| 200 | ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno)) |
| 201 | |
| 202 | typedef struct BonitoState BonitoState; |
| 203 | |
| 204 | struct PCIBonitoState { |
| 205 | PCIDevice dev; |
| 206 | |
| 207 | BonitoState *pcihost; |
| 208 | uint32_t regs[BONITO_REGS]; |
| 209 | |
| 210 | struct bonldma { |
| 211 | uint32_t ldmactrl; |
| 212 | uint32_t ldmastat; |
| 213 | uint32_t ldmaaddr; |
| 214 | uint32_t ldmago; |
| 215 | } bonldma; |
| 216 | |
| 217 | /* Based at 1fe00300, bonito Copier */ |
| 218 | struct boncop { |
| 219 | uint32_t copctrl; |
| 220 | uint32_t copstat; |
| 221 | uint32_t coppaddr; |
| 222 | uint32_t copgo; |
| 223 | } boncop; |
| 224 | |
| 225 | /* Bonito registers */ |
| 226 | MemoryRegion iomem; |
| 227 | MemoryRegion iomem_ldma; |
| 228 | MemoryRegion iomem_cop; |
| 229 | MemoryRegion bonito_pciio; |
| 230 | MemoryRegion bonito_localio; |
| 231 | |
| 232 | }; |
| 233 | |
| 234 | #define TYPE_PCI_BONITO "Bonito" |
| 235 | OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO) |
| 236 | |
| 237 | struct BonitoState { |
| 238 | PCIHostState parent_obj; |
| 239 | qemu_irq *pic; |
| 240 | PCIBonitoState *pci_dev; |
| 241 | MemoryRegion pci_mem; |
| 242 | }; |
| 243 | |
| 244 | static void bonito_writel(void *opaque, hwaddr addr, |
| 245 | uint64_t val, unsigned size) |
| 246 | { |
| 247 | PCIBonitoState *s = opaque; |
| 248 | uint32_t saddr; |
| 249 | int reset = 0; |
| 250 | |
| 251 | saddr = addr >> 2; |
| 252 | |
| 253 | DPRINTF("bonito_writel "HWADDR_FMT_plx" val %lx saddr %x\n", |
| 254 | addr, val, saddr); |
| 255 | switch (saddr) { |
| 256 | case BONITO_BONPONCFG: |
| 257 | case BONITO_IODEVCFG: |
| 258 | case BONITO_SDCFG: |
| 259 | case BONITO_PCIMAP: |
| 260 | case BONITO_PCIMEMBASECFG: |
| 261 | case BONITO_PCIMAP_CFG: |
| 262 | case BONITO_GPIODATA: |
| 263 | case BONITO_GPIOIE: |
| 264 | case BONITO_INTEDGE: |
| 265 | case BONITO_INTSTEER: |
| 266 | case BONITO_INTPOL: |
| 267 | case BONITO_PCIMAIL0: |
| 268 | case BONITO_PCIMAIL1: |
| 269 | case BONITO_PCIMAIL2: |
| 270 | case BONITO_PCIMAIL3: |
| 271 | case BONITO_PCICACHECTRL: |
| 272 | case BONITO_PCICACHETAG: |
| 273 | case BONITO_PCIBADADDR: |
| 274 | case BONITO_PCIMSTAT: |
| 275 | case BONITO_TIMECFG: |
| 276 | case BONITO_CPUCFG: |
| 277 | case BONITO_DQCFG: |
| 278 | case BONITO_MEMSIZE: |
| 279 | s->regs[saddr] = val; |
| 280 | break; |
| 281 | case BONITO_BONGENCFG: |
| 282 | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { |
| 283 | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ |
| 284 | } |
| 285 | s->regs[saddr] = val; |
| 286 | if (reset) { |
| 287 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 288 | } |
| 289 | break; |
| 290 | case BONITO_INTENSET: |
| 291 | s->regs[BONITO_INTENSET] = val; |
| 292 | s->regs[BONITO_INTEN] |= val; |
| 293 | break; |
| 294 | case BONITO_INTENCLR: |
| 295 | s->regs[BONITO_INTENCLR] = val; |
| 296 | s->regs[BONITO_INTEN] &= ~val; |
| 297 | break; |
| 298 | case BONITO_INTEN: |
| 299 | case BONITO_INTISR: |
| 300 | DPRINTF("write to readonly bonito register %x\n", saddr); |
| 301 | break; |
| 302 | default: |
| 303 | DPRINTF("write to unknown bonito register %x\n", saddr); |
| 304 | break; |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | static uint64_t bonito_readl(void *opaque, hwaddr addr, |
| 309 | unsigned size) |
| 310 | { |
| 311 | PCIBonitoState *s = opaque; |
| 312 | uint32_t saddr; |
| 313 | |
| 314 | saddr = addr >> 2; |
| 315 | |
| 316 | DPRINTF("bonito_readl "HWADDR_FMT_plx"\n", addr); |
| 317 | switch (saddr) { |
| 318 | case BONITO_INTISR: |
| 319 | return s->regs[saddr]; |
| 320 | default: |
| 321 | return s->regs[saddr]; |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static const MemoryRegionOps bonito_ops = { |
| 326 | .read = bonito_readl, |
| 327 | .write = bonito_writel, |
| 328 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 329 | .valid = { |
| 330 | .min_access_size = 4, |
| 331 | .max_access_size = 4, |
| 332 | }, |
| 333 | }; |
| 334 | |
| 335 | static void bonito_pciconf_writel(void *opaque, hwaddr addr, |
| 336 | uint64_t val, unsigned size) |
| 337 | { |
| 338 | PCIBonitoState *s = opaque; |
| 339 | PCIDevice *d = PCI_DEVICE(s); |
| 340 | |
| 341 | DPRINTF("bonito_pciconf_writel "HWADDR_FMT_plx" val %lx\n", addr, val); |
| 342 | d->config_write(d, addr, val, 4); |
| 343 | } |
| 344 | |
| 345 | static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, |
| 346 | unsigned size) |
| 347 | { |
| 348 | |
| 349 | PCIBonitoState *s = opaque; |
| 350 | PCIDevice *d = PCI_DEVICE(s); |
| 351 | |
| 352 | DPRINTF("bonito_pciconf_readl "HWADDR_FMT_plx"\n", addr); |
| 353 | return d->config_read(d, addr, 4); |
| 354 | } |
| 355 | |
| 356 | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ |
| 357 | |
| 358 | static const MemoryRegionOps bonito_pciconf_ops = { |
| 359 | .read = bonito_pciconf_readl, |
| 360 | .write = bonito_pciconf_writel, |
| 361 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 362 | .valid = { |
| 363 | .min_access_size = 4, |
| 364 | .max_access_size = 4, |
| 365 | }, |
| 366 | }; |
| 367 | |
| 368 | static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, |
| 369 | unsigned size) |
| 370 | { |
| 371 | uint32_t val; |
| 372 | PCIBonitoState *s = opaque; |
| 373 | |
| 374 | if (addr >= sizeof(s->bonldma)) { |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; |
| 379 | |
| 380 | return val; |
| 381 | } |
| 382 | |
| 383 | static void bonito_ldma_writel(void *opaque, hwaddr addr, |
| 384 | uint64_t val, unsigned size) |
| 385 | { |
| 386 | PCIBonitoState *s = opaque; |
| 387 | |
| 388 | if (addr >= sizeof(s->bonldma)) { |
| 389 | return; |
| 390 | } |
| 391 | |
| 392 | ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
| 393 | } |
| 394 | |
| 395 | static const MemoryRegionOps bonito_ldma_ops = { |
| 396 | .read = bonito_ldma_readl, |
| 397 | .write = bonito_ldma_writel, |
| 398 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 399 | .valid = { |
| 400 | .min_access_size = 4, |
| 401 | .max_access_size = 4, |
| 402 | }, |
| 403 | }; |
| 404 | |
| 405 | static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, |
| 406 | unsigned size) |
| 407 | { |
| 408 | uint32_t val; |
| 409 | PCIBonitoState *s = opaque; |
| 410 | |
| 411 | if (addr >= sizeof(s->boncop)) { |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; |
| 416 | |
| 417 | return val; |
| 418 | } |
| 419 | |
| 420 | static void bonito_cop_writel(void *opaque, hwaddr addr, |
| 421 | uint64_t val, unsigned size) |
| 422 | { |
| 423 | PCIBonitoState *s = opaque; |
| 424 | |
| 425 | if (addr >= sizeof(s->boncop)) { |
| 426 | return; |
| 427 | } |
| 428 | |
| 429 | ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
| 430 | } |
| 431 | |
| 432 | static const MemoryRegionOps bonito_cop_ops = { |
| 433 | .read = bonito_cop_readl, |
| 434 | .write = bonito_cop_writel, |
| 435 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 436 | .valid = { |
| 437 | .min_access_size = 4, |
| 438 | .max_access_size = 4, |
| 439 | }, |
| 440 | }; |
| 441 | |
| 442 | static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) |
| 443 | { |
| 444 | PCIBonitoState *s = opaque; |
| 445 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
| 446 | uint32_t cfgaddr; |
| 447 | uint32_t idsel; |
| 448 | uint32_t devno; |
| 449 | uint32_t funno; |
| 450 | uint32_t regno; |
| 451 | uint32_t pciaddr; |
| 452 | |
| 453 | /* support type0 pci config */ |
| 454 | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { |
| 455 | return 0xffffffff; |
| 456 | } |
| 457 | |
| 458 | cfgaddr = addr & 0xffff; |
| 459 | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; |
| 460 | |
| 461 | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> |
| 462 | BONITO_PCICONF_IDSEL_OFFSET; |
| 463 | devno = ctz32(idsel); |
| 464 | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; |
| 465 | regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET; |
| 466 | |
| 467 | if (idsel == 0) { |
| 468 | error_report("error in bonito pci config address 0x" HWADDR_FMT_plx |
| 469 | ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]); |
| 470 | exit(1); |
| 471 | } |
| 472 | pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); |
| 473 | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", |
| 474 | cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); |
| 475 | |
| 476 | return pciaddr; |
| 477 | } |
| 478 | |
| 479 | static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, |
| 480 | unsigned size) |
| 481 | { |
| 482 | PCIBonitoState *s = opaque; |
| 483 | PCIDevice *d = PCI_DEVICE(s); |
| 484 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
| 485 | uint32_t pciaddr; |
| 486 | uint16_t status; |
| 487 | |
| 488 | DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n", |
| 489 | addr, size, val); |
| 490 | |
| 491 | pciaddr = bonito_sbridge_pciaddr(s, addr); |
| 492 | |
| 493 | if (pciaddr == 0xffffffff) { |
| 494 | return; |
| 495 | } |
| 496 | if (addr & ~BONITO_PCICONF_REG_MASK_DS) { |
| 497 | trace_bonito_spciconf_small_access(addr, size); |
| 498 | } |
| 499 | |
| 500 | /* set the pci address in s->config_reg */ |
| 501 | phb->config_reg = (pciaddr) | (1u << 31); |
| 502 | pci_data_write(phb->bus, phb->config_reg, val, size); |
| 503 | |
| 504 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ |
| 505 | status = pci_get_word(d->config + PCI_STATUS); |
| 506 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
| 507 | pci_set_word(d->config + PCI_STATUS, status); |
| 508 | } |
| 509 | |
| 510 | static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) |
| 511 | { |
| 512 | PCIBonitoState *s = opaque; |
| 513 | PCIDevice *d = PCI_DEVICE(s); |
| 514 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
| 515 | uint32_t pciaddr; |
| 516 | uint16_t status; |
| 517 | |
| 518 | DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size); |
| 519 | |
| 520 | pciaddr = bonito_sbridge_pciaddr(s, addr); |
| 521 | |
| 522 | if (pciaddr == 0xffffffff) { |
| 523 | return MAKE_64BIT_MASK(0, size * 8); |
| 524 | } |
| 525 | if (addr & ~BONITO_PCICONF_REG_MASK_DS) { |
| 526 | trace_bonito_spciconf_small_access(addr, size); |
| 527 | } |
| 528 | |
| 529 | /* set the pci address in s->config_reg */ |
| 530 | phb->config_reg = (pciaddr) | (1u << 31); |
| 531 | |
| 532 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ |
| 533 | status = pci_get_word(d->config + PCI_STATUS); |
| 534 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
| 535 | pci_set_word(d->config + PCI_STATUS, status); |
| 536 | |
| 537 | return pci_data_read(phb->bus, phb->config_reg, size); |
| 538 | } |
| 539 | |
| 540 | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ |
| 541 | static const MemoryRegionOps bonito_spciconf_ops = { |
| 542 | .read = bonito_spciconf_read, |
| 543 | .write = bonito_spciconf_write, |
| 544 | .valid.min_access_size = 1, |
| 545 | .valid.max_access_size = 4, |
| 546 | .impl.min_access_size = 1, |
| 547 | .impl.max_access_size = 4, |
| 548 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 549 | }; |
| 550 | |
| 551 | #define BONITO_IRQ_BASE 32 |
| 552 | |
| 553 | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) |
| 554 | { |
| 555 | BonitoState *s = opaque; |
| 556 | qemu_irq *pic = s->pic; |
| 557 | PCIBonitoState *bonito_state = s->pci_dev; |
| 558 | int internal_irq = irq_num - BONITO_IRQ_BASE; |
| 559 | |
| 560 | if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { |
| 561 | qemu_irq_pulse(*pic); |
| 562 | } else { /* level triggered */ |
| 563 | if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { |
| 564 | qemu_irq_raise(*pic); |
| 565 | } else { |
| 566 | qemu_irq_lower(*pic); |
| 567 | } |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ |
| 572 | static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) |
| 573 | { |
| 574 | int slot; |
| 575 | |
| 576 | slot = PCI_SLOT(pci_dev->devfn); |
| 577 | |
| 578 | switch (slot) { |
| 579 | case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ |
| 580 | return irq_num % 4 + BONITO_IRQ_BASE; |
| 581 | case 6: /* FULOONG2E_ATI_SLOT, VGA */ |
| 582 | return 4 + BONITO_IRQ_BASE; |
| 583 | case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */ |
| 584 | return 5 + BONITO_IRQ_BASE; |
| 585 | case 8 ... 12: /* PCI slot 1 to 4 */ |
| 586 | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; |
| 587 | default: /* Unknown device, don't do any translation */ |
| 588 | return irq_num; |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | static void bonito_reset_hold(Object *obj, ResetType type) |
| 593 | { |
| 594 | PCIBonitoState *s = PCI_BONITO(obj); |
| 595 | uint32_t val = 0; |
| 596 | |
| 597 | /* set the default value of north bridge registers */ |
| 598 | |
| 599 | s->regs[BONITO_BONPONCFG] = 0xc40; |
| 600 | val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1); |
| 601 | val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1); |
| 602 | val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1); |
| 603 | val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1); |
| 604 | val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1); |
| 605 | s->regs[BONITO_BONGENCFG] = val; |
| 606 | |
| 607 | s->regs[BONITO_IODEVCFG] = 0x2bff8010; |
| 608 | s->regs[BONITO_SDCFG] = 0x255e0091; |
| 609 | |
| 610 | s->regs[BONITO_GPIODATA] = 0x1ff; |
| 611 | s->regs[BONITO_GPIOIE] = 0x1ff; |
| 612 | s->regs[BONITO_DQCFG] = 0x8; |
| 613 | s->regs[BONITO_MEMSIZE] = 0x10000000; |
| 614 | s->regs[BONITO_PCIMAP] = 0x6140; |
| 615 | } |
| 616 | |
| 617 | static const VMStateDescription vmstate_bonito = { |
| 618 | .name = "Bonito", |
| 619 | .version_id = 1, |
| 620 | .minimum_version_id = 1, |
| 621 | .fields = (const VMStateField[]) { |
| 622 | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), |
| 623 | VMSTATE_END_OF_LIST() |
| 624 | } |
| 625 | }; |
| 626 | |
| 627 | static void bonito_host_realize(DeviceState *dev, Error **errp) |
| 628 | { |
| 629 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
| 630 | BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); |
| 631 | MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3); |
| 632 | |
| 633 | memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE); |
| 634 | phb->bus = pci_register_root_bus(dev, "pci", |
| 635 | pci_bonito_set_irq, pci_bonito_map_irq, |
| 636 | dev, &bs->pci_mem, get_system_io(), |
| 637 | PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS); |
| 638 | |
| 639 | for (size_t i = 0; i < 3; i++) { |
| 640 | char *name = g_strdup_printf("pci.lomem%zu", i); |
| 641 | |
| 642 | memory_region_init_alias(&pcimem_lo_alias[i], NULL, name, |
| 643 | &bs->pci_mem, i * 64 * MiB, 64 * MiB); |
| 644 | memory_region_add_subregion(get_system_memory(), |
| 645 | BONITO_PCILO_BASE + i * 64 * MiB, |
| 646 | &pcimem_lo_alias[i]); |
| 647 | g_free(name); |
| 648 | } |
| 649 | |
| 650 | create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB); |
| 651 | } |
| 652 | |
| 653 | static void bonito_pci_realize(PCIDevice *dev, Error **errp) |
| 654 | { |
| 655 | PCIBonitoState *s = PCI_BONITO(dev); |
| 656 | MemoryRegion *host_mem = get_system_memory(); |
| 657 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
| 658 | BonitoState *bs = s->pcihost; |
| 659 | MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1); |
| 660 | |
| 661 | /* |
| 662 | * Bonito North Bridge, built on FPGA, |
| 663 | * VENDOR_ID/DEVICE_ID are "undefined" |
| 664 | */ |
| 665 | pci_config_set_prog_interface(dev->config, 0x00); |
| 666 | |
| 667 | /* set the north bridge register mapping */ |
| 668 | memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, |
| 669 | "north-bridge-register", BONITO_INTERNAL_REG_SIZE); |
| 670 | memory_region_add_subregion(host_mem, BONITO_INTERNAL_REG_BASE, &s->iomem); |
| 671 | |
| 672 | /* set the north bridge pci configure mapping */ |
| 673 | memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, |
| 674 | "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); |
| 675 | memory_region_add_subregion(host_mem, BONITO_PCICONFIG_BASE, |
| 676 | &phb->conf_mem); |
| 677 | |
| 678 | /* set the south bridge pci configure mapping */ |
| 679 | memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, |
| 680 | "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); |
| 681 | memory_region_add_subregion(host_mem, BONITO_SPCICONFIG_BASE, |
| 682 | &phb->data_mem); |
| 683 | |
| 684 | create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE); |
| 685 | |
| 686 | memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, |
| 687 | "ldma", 0x100); |
| 688 | memory_region_add_subregion(host_mem, 0x1fe00200, &s->iomem_ldma); |
| 689 | |
| 690 | /* PCI copier */ |
| 691 | memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, |
| 692 | "cop", 0x100); |
| 693 | memory_region_add_subregion(host_mem, 0x1fe00300, &s->iomem_cop); |
| 694 | |
| 695 | create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB); |
| 696 | |
| 697 | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ |
| 698 | memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", |
| 699 | get_system_io(), 0, BONITO_PCIIO_SIZE); |
| 700 | memory_region_add_subregion(host_mem, BONITO_PCIIO_BASE, |
| 701 | &s->bonito_pciio); |
| 702 | |
| 703 | /* add pci local io mapping */ |
| 704 | |
| 705 | memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]", |
| 706 | get_system_io(), 0, 256 * KiB); |
| 707 | memory_region_add_subregion(host_mem, BONITO_DEV_BASE, |
| 708 | &s->bonito_localio); |
| 709 | create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB, |
| 710 | 256 * KiB); |
| 711 | create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB, |
| 712 | 256 * KiB); |
| 713 | create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB, |
| 714 | 256 * KiB); |
| 715 | |
| 716 | memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias", |
| 717 | &bs->pci_mem, 0, BONITO_PCIHI_SIZE); |
| 718 | memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_alias); |
| 719 | create_unimplemented_device("PCI_2", |
| 720 | (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE, |
| 721 | 2 * GiB); |
| 722 | |
| 723 | /* set the default value of north bridge pci config */ |
| 724 | pci_set_word(dev->config + PCI_COMMAND, 0x0000); |
| 725 | pci_set_word(dev->config + PCI_STATUS, 0x0000); |
| 726 | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); |
| 727 | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); |
| 728 | |
| 729 | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); |
| 730 | pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */ |
| 731 | |
| 732 | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); |
| 733 | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); |
| 734 | } |
| 735 | |
| 736 | PCIBus *bonito_init(qemu_irq *pic) |
| 737 | { |
| 738 | DeviceState *dev; |
| 739 | BonitoState *pcihost; |
| 740 | PCIHostState *phb; |
| 741 | PCIBonitoState *s; |
| 742 | PCIDevice *d; |
| 743 | |
| 744 | dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE); |
| 745 | phb = PCI_HOST_BRIDGE(dev); |
| 746 | pcihost = BONITO_PCI_HOST_BRIDGE(dev); |
| 747 | pcihost->pic = pic; |
| 748 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 749 | |
| 750 | d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); |
| 751 | s = PCI_BONITO(d); |
| 752 | s->pcihost = pcihost; |
| 753 | pcihost->pci_dev = s; |
| 754 | pci_realize_and_unref(d, phb->bus, &error_fatal); |
| 755 | |
| 756 | return phb->bus; |
| 757 | } |
| 758 | |
| 759 | static void bonito_pci_class_init(ObjectClass *klass, const void *data) |
| 760 | { |
| 761 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 762 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 763 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 764 | |
| 765 | rc->phases.hold = bonito_reset_hold; |
| 766 | k->realize = bonito_pci_realize; |
| 767 | k->vendor_id = 0xdf53; |
| 768 | k->device_id = 0x00d5; |
| 769 | k->revision = 0x01; |
| 770 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 771 | dc->desc = "Host bridge"; |
| 772 | dc->vmsd = &vmstate_bonito; |
| 773 | /* |
| 774 | * PCI-facing part of the host bridge, not usable without the |
| 775 | * host-facing part, which can't be device_add'ed, yet. |
| 776 | */ |
| 777 | dc->user_creatable = false; |
| 778 | } |
| 779 | |
| 780 | static const TypeInfo bonito_pci_info = { |
| 781 | .name = TYPE_PCI_BONITO, |
| 782 | .parent = TYPE_PCI_DEVICE, |
| 783 | .instance_size = sizeof(PCIBonitoState), |
| 784 | .class_init = bonito_pci_class_init, |
| 785 | .interfaces = (const InterfaceInfo[]) { |
| 786 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 787 | { }, |
| 788 | }, |
| 789 | }; |
| 790 | |
| 791 | static void bonito_host_class_init(ObjectClass *klass, const void *data) |
| 792 | { |
| 793 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 794 | |
| 795 | dc->realize = bonito_host_realize; |
| 796 | } |
| 797 | |
| 798 | static const TypeInfo bonito_host_info = { |
| 799 | .name = TYPE_BONITO_PCI_HOST_BRIDGE, |
| 800 | .parent = TYPE_PCI_HOST_BRIDGE, |
| 801 | .instance_size = sizeof(BonitoState), |
| 802 | .class_init = bonito_host_class_init, |
| 803 | }; |
| 804 | |
| 805 | static void bonito_register_types(void) |
| 806 | { |
| 807 | type_register_static(&bonito_host_info); |
| 808 | type_register_static(&bonito_pci_info); |
| 809 | } |
| 810 | |
| 811 | type_init(bonito_register_types) |