| 1 | /* |
| 2 | * QEMU Generic PCI Express Bridge Emulation |
| 3 | * |
| 4 | * Copyright (C) 2015 Alexander Graf <agraf@suse.de> |
| 5 | * |
| 6 | * Code loosely based on q35.c. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | * |
| 26 | * Check out these documents for more information on the device: |
| 27 | * |
| 28 | * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt |
| 29 | * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf |
| 30 | */ |
| 31 | |
| 32 | #include "qemu/osdep.h" |
| 33 | #include "qapi/error.h" |
| 34 | #include "hw/core/irq.h" |
| 35 | #include "hw/pci/pci_bus.h" |
| 36 | #include "hw/pci-host/gpex.h" |
| 37 | #include "hw/core/qdev-properties.h" |
| 38 | #include "migration/vmstate.h" |
| 39 | #include "qemu/module.h" |
| 40 | |
| 41 | /**************************************************************************** |
| 42 | * GPEX host |
| 43 | */ |
| 44 | |
| 45 | struct GPEXIrq { |
| 46 | qemu_irq irq; |
| 47 | int irq_num; |
| 48 | }; |
| 49 | |
| 50 | static void gpex_set_irq(void *opaque, int irq_num, int level) |
| 51 | { |
| 52 | GPEXHost *s = opaque; |
| 53 | |
| 54 | qemu_set_irq(s->irq[irq_num].irq, level); |
| 55 | } |
| 56 | |
| 57 | int gpex_set_irq_num(GPEXHost *s, int index, int gsi) |
| 58 | { |
| 59 | if (index >= s->num_irqs) { |
| 60 | return -EINVAL; |
| 61 | } |
| 62 | |
| 63 | s->irq[index].irq_num = gsi; |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) |
| 68 | { |
| 69 | PCIINTxRoute route; |
| 70 | GPEXHost *s = opaque; |
| 71 | int gsi = s->irq[pin].irq_num; |
| 72 | |
| 73 | route.irq = gsi; |
| 74 | if (gsi < 0) { |
| 75 | route.mode = PCI_INTX_DISABLED; |
| 76 | } else { |
| 77 | route.mode = PCI_INTX_ENABLED; |
| 78 | } |
| 79 | |
| 80 | return route; |
| 81 | } |
| 82 | |
| 83 | static int gpex_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) |
| 84 | { |
| 85 | PCIBus *bus = pci_device_root_bus(pci_dev); |
| 86 | |
| 87 | return (PCI_SLOT(pci_dev->devfn) + pin) % bus->nirq; |
| 88 | } |
| 89 | |
| 90 | static void gpex_host_realize(DeviceState *dev, Error **errp) |
| 91 | { |
| 92 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
| 93 | GPEXHost *s = GPEX_HOST(dev); |
| 94 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 95 | PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); |
| 96 | int i; |
| 97 | |
| 98 | s->irq = g_malloc0_n(s->num_irqs, sizeof(*s->irq)); |
| 99 | |
| 100 | pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); |
| 101 | sysbus_init_mmio(sbd, &pex->mmio); |
| 102 | |
| 103 | /* |
| 104 | * Note that the MemoryRegions io_mmio and io_ioport that we pass |
| 105 | * to pci_register_root_bus() are not the same as the |
| 106 | * MemoryRegions io_mmio_window and io_ioport_window that we |
| 107 | * expose as SysBus MRs. The difference is in the behaviour of |
| 108 | * accesses to addresses where no PCI device has been mapped. |
| 109 | * |
| 110 | * io_mmio and io_ioport are the underlying PCI view of the PCI |
| 111 | * address space, and when a PCI device does a bus master access |
| 112 | * to a bad address this is reported back to it as a transaction |
| 113 | * failure. |
| 114 | * |
| 115 | * io_mmio_window and io_ioport_window implement "unmapped |
| 116 | * addresses read as -1 and ignore writes"; this is traditional |
| 117 | * x86 PC behaviour, which is not mandated by the PCI spec proper |
| 118 | * but expected by much PCI-using guest software, including Linux. |
| 119 | * |
| 120 | * In the interests of not being unnecessarily surprising, we |
| 121 | * implement it in the gpex PCI host controller, by providing the |
| 122 | * _window MRs, which are containers with io ops that implement |
| 123 | * the 'background' behaviour and which hold the real PCI MRs as |
| 124 | * subregions. |
| 125 | */ |
| 126 | memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX); |
| 127 | memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024); |
| 128 | |
| 129 | if (s->allow_unmapped_accesses) { |
| 130 | memory_region_init_io(&s->io_mmio_window, OBJECT(s), |
| 131 | &unassigned_io_ops, OBJECT(s), |
| 132 | "gpex_mmio_window", UINT64_MAX); |
| 133 | memory_region_init_io(&s->io_ioport_window, OBJECT(s), |
| 134 | &unassigned_io_ops, OBJECT(s), |
| 135 | "gpex_ioport_window", 64 * 1024); |
| 136 | |
| 137 | memory_region_add_subregion(&s->io_mmio_window, 0, &s->io_mmio); |
| 138 | memory_region_add_subregion(&s->io_ioport_window, 0, &s->io_ioport); |
| 139 | sysbus_init_mmio(sbd, &s->io_mmio_window); |
| 140 | sysbus_init_mmio(sbd, &s->io_ioport_window); |
| 141 | } else { |
| 142 | sysbus_init_mmio(sbd, &s->io_mmio); |
| 143 | sysbus_init_mmio(sbd, &s->io_ioport); |
| 144 | } |
| 145 | |
| 146 | for (i = 0; i < s->num_irqs; i++) { |
| 147 | sysbus_init_irq(sbd, &s->irq[i].irq); |
| 148 | s->irq[i].irq_num = -1; |
| 149 | } |
| 150 | |
| 151 | pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq, |
| 152 | gpex_swizzle_map_irq_fn, |
| 153 | s, &s->io_mmio, &s->io_ioport, 0, |
| 154 | s->num_irqs, TYPE_PCIE_BUS); |
| 155 | |
| 156 | pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); |
| 157 | qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal); |
| 158 | } |
| 159 | |
| 160 | static void gpex_host_unrealize(DeviceState *dev) |
| 161 | { |
| 162 | GPEXHost *s = GPEX_HOST(dev); |
| 163 | |
| 164 | g_free(s->irq); |
| 165 | } |
| 166 | |
| 167 | static const char *gpex_host_root_bus_path(PCIHostState *host_bridge, |
| 168 | PCIBus *rootbus) |
| 169 | { |
| 170 | return "0000:00"; |
| 171 | } |
| 172 | |
| 173 | static const Property gpex_host_properties[] = { |
| 174 | /* |
| 175 | * Permit CPU accesses to unmapped areas of the PIO and MMIO windows |
| 176 | * (discarding writes and returning -1 for reads) rather than aborting. |
| 177 | */ |
| 178 | DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, |
| 179 | allow_unmapped_accesses, true), |
| 180 | DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), |
| 181 | DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), |
| 182 | DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), |
| 183 | DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), |
| 184 | DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, |
| 185 | gpex_cfg.mmio32.base, 0), |
| 186 | DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, |
| 187 | gpex_cfg.mmio32.size, 0), |
| 188 | DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, |
| 189 | gpex_cfg.mmio64.base, 0), |
| 190 | DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, |
| 191 | gpex_cfg.mmio64.size, 0), |
| 192 | DEFINE_PROP_UINT8("num-irqs", GPEXHost, num_irqs, PCI_NUM_PINS), |
| 193 | }; |
| 194 | |
| 195 | static void gpex_host_class_init(ObjectClass *klass, const void *data) |
| 196 | { |
| 197 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 198 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
| 199 | |
| 200 | hc->root_bus_path = gpex_host_root_bus_path; |
| 201 | dc->realize = gpex_host_realize; |
| 202 | dc->unrealize = gpex_host_unrealize; |
| 203 | dc->fw_name = "pci"; |
| 204 | device_class_set_props(dc, gpex_host_properties); |
| 205 | } |
| 206 | |
| 207 | static void gpex_host_initfn(Object *obj) |
| 208 | { |
| 209 | GPEXHost *s = GPEX_HOST(obj); |
| 210 | GPEXRootState *root = &s->gpex_root; |
| 211 | |
| 212 | object_initialize_child(obj, "gpex_root", root, TYPE_GPEX_ROOT_DEVICE); |
| 213 | qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); |
| 214 | qdev_prop_set_bit(DEVICE(root), "multifunction", false); |
| 215 | } |
| 216 | |
| 217 | static const TypeInfo gpex_host_info = { |
| 218 | .name = TYPE_GPEX_HOST, |
| 219 | .parent = TYPE_PCIE_HOST_BRIDGE, |
| 220 | .instance_size = sizeof(GPEXHost), |
| 221 | .instance_init = gpex_host_initfn, |
| 222 | .class_init = gpex_host_class_init, |
| 223 | }; |
| 224 | |
| 225 | /**************************************************************************** |
| 226 | * GPEX Root D0:F0 |
| 227 | */ |
| 228 | |
| 229 | static const VMStateDescription vmstate_gpex_root = { |
| 230 | .name = "gpex_root", |
| 231 | .version_id = 1, |
| 232 | .minimum_version_id = 1, |
| 233 | .fields = (const VMStateField[]) { |
| 234 | VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState), |
| 235 | VMSTATE_END_OF_LIST() |
| 236 | } |
| 237 | }; |
| 238 | |
| 239 | static void gpex_root_class_init(ObjectClass *klass, const void *data) |
| 240 | { |
| 241 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 242 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 243 | |
| 244 | dc->desc = "QEMU generic PCIe host bridge"; |
| 245 | dc->vmsd = &vmstate_gpex_root; |
| 246 | k->vendor_id = PCI_VENDOR_ID_REDHAT; |
| 247 | k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST; |
| 248 | k->revision = 0; |
| 249 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 250 | /* |
| 251 | * PCI-facing part of the host bridge, not usable without the |
| 252 | * host-facing part, which can't be device_add'ed, yet. |
| 253 | */ |
| 254 | dc->user_creatable = false; |
| 255 | } |
| 256 | |
| 257 | static const TypeInfo gpex_root_info = { |
| 258 | .name = TYPE_GPEX_ROOT_DEVICE, |
| 259 | .parent = TYPE_PCI_DEVICE, |
| 260 | .instance_size = sizeof(GPEXRootState), |
| 261 | .class_init = gpex_root_class_init, |
| 262 | .interfaces = (const InterfaceInfo[]) { |
| 263 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 264 | { }, |
| 265 | }, |
| 266 | }; |
| 267 | |
| 268 | static void gpex_register(void) |
| 269 | { |
| 270 | type_register_static(&gpex_root_info); |
| 271 | type_register_static(&gpex_host_info); |
| 272 | } |
| 273 | |
| 274 | type_init(gpex_register) |