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1 /*
2 * QEMU GT64120 PCI host
3 *
4 * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999)
5 *
6 * Copyright (c) 2006,2007 Aurelien Jarno
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qemu/units.h"
30 #include "qemu/log.h"
31 #include "qemu/bswap.h"
32 #include "hw/core/qdev-properties.h"
33 #include "hw/core/registerfields.h"
34 #include "hw/pci/pci_device.h"
35 #include "hw/pci/pci_host.h"
36 #include "hw/misc/empty_slot.h"
37 #include "migration/vmstate.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/core/irq.h"
40 #include "trace.h"
41 #include "qom/object.h"
42
43 #define GT_REGS (0x1000 >> 2)
44
45 /* CPU Configuration */
46 #define GT_CPU (0x000 >> 2)
47 #define GT_MULTI (0x120 >> 2)
48
49 REG32(GT_CPU, 0x000)
50 FIELD(GT_CPU, Endianness, 12, 1)
51
52 /* CPU Address Decode */
53 #define GT_SCS10LD (0x008 >> 2)
54 #define GT_SCS10HD (0x010 >> 2)
55 #define GT_SCS32LD (0x018 >> 2)
56 #define GT_SCS32HD (0x020 >> 2)
57 #define GT_CS20LD (0x028 >> 2)
58 #define GT_CS20HD (0x030 >> 2)
59 #define GT_CS3BOOTLD (0x038 >> 2)
60 #define GT_CS3BOOTHD (0x040 >> 2)
61 #define GT_PCI0IOLD (0x048 >> 2)
62 #define GT_PCI0IOHD (0x050 >> 2)
63 #define GT_PCI0M0LD (0x058 >> 2)
64 #define GT_PCI0M0HD (0x060 >> 2)
65 #define GT_PCI0M1LD (0x080 >> 2)
66 #define GT_PCI0M1HD (0x088 >> 2)
67 #define GT_PCI1IOLD (0x090 >> 2)
68 #define GT_PCI1IOHD (0x098 >> 2)
69 #define GT_PCI1M0LD (0x0a0 >> 2)
70 #define GT_PCI1M0HD (0x0a8 >> 2)
71 #define GT_PCI1M1LD (0x0b0 >> 2)
72 #define GT_PCI1M1HD (0x0b8 >> 2)
73 #define GT_ISD (0x068 >> 2)
74
75 #define GT_SCS10AR (0x0d0 >> 2)
76 #define GT_SCS32AR (0x0d8 >> 2)
77 #define GT_CS20R (0x0e0 >> 2)
78 #define GT_CS3BOOTR (0x0e8 >> 2)
79
80 #define GT_PCI0IOREMAP (0x0f0 >> 2)
81 #define GT_PCI0M0REMAP (0x0f8 >> 2)
82 #define GT_PCI0M1REMAP (0x100 >> 2)
83 #define GT_PCI1IOREMAP (0x108 >> 2)
84 #define GT_PCI1M0REMAP (0x110 >> 2)
85 #define GT_PCI1M1REMAP (0x118 >> 2)
86
87 /* CPU Error Report */
88 #define GT_CPUERR_ADDRLO (0x070 >> 2)
89 #define GT_CPUERR_ADDRHI (0x078 >> 2)
90 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
91 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
92 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
93
94 /* CPU Sync Barrier */
95 #define GT_PCI0SYNC (0x0c0 >> 2)
96 #define GT_PCI1SYNC (0x0c8 >> 2)
97
98 /* SDRAM and Device Address Decode */
99 #define GT_SCS0LD (0x400 >> 2)
100 #define GT_SCS0HD (0x404 >> 2)
101 #define GT_SCS1LD (0x408 >> 2)
102 #define GT_SCS1HD (0x40c >> 2)
103 #define GT_SCS2LD (0x410 >> 2)
104 #define GT_SCS2HD (0x414 >> 2)
105 #define GT_SCS3LD (0x418 >> 2)
106 #define GT_SCS3HD (0x41c >> 2)
107 #define GT_CS0LD (0x420 >> 2)
108 #define GT_CS0HD (0x424 >> 2)
109 #define GT_CS1LD (0x428 >> 2)
110 #define GT_CS1HD (0x42c >> 2)
111 #define GT_CS2LD (0x430 >> 2)
112 #define GT_CS2HD (0x434 >> 2)
113 #define GT_CS3LD (0x438 >> 2)
114 #define GT_CS3HD (0x43c >> 2)
115 #define GT_BOOTLD (0x440 >> 2)
116 #define GT_BOOTHD (0x444 >> 2)
117 #define GT_ADERR (0x470 >> 2)
118
119 /* SDRAM Configuration */
120 #define GT_SDRAM_CFG (0x448 >> 2)
121 #define GT_SDRAM_OPMODE (0x474 >> 2)
122 #define GT_SDRAM_BM (0x478 >> 2)
123 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
124
125 /* SDRAM Parameters */
126 #define GT_SDRAM_B0 (0x44c >> 2)
127 #define GT_SDRAM_B1 (0x450 >> 2)
128 #define GT_SDRAM_B2 (0x454 >> 2)
129 #define GT_SDRAM_B3 (0x458 >> 2)
130
131 /* Device Parameters */
132 #define GT_DEV_B0 (0x45c >> 2)
133 #define GT_DEV_B1 (0x460 >> 2)
134 #define GT_DEV_B2 (0x464 >> 2)
135 #define GT_DEV_B3 (0x468 >> 2)
136 #define GT_DEV_BOOT (0x46c >> 2)
137
138 /* ECC */
139 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
140 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
141 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
142 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
143 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
144
145 /* DMA Record */
146 #define GT_DMA0_CNT (0x800 >> 2)
147 #define GT_DMA1_CNT (0x804 >> 2)
148 #define GT_DMA2_CNT (0x808 >> 2)
149 #define GT_DMA3_CNT (0x80c >> 2)
150 #define GT_DMA0_SA (0x810 >> 2)
151 #define GT_DMA1_SA (0x814 >> 2)
152 #define GT_DMA2_SA (0x818 >> 2)
153 #define GT_DMA3_SA (0x81c >> 2)
154 #define GT_DMA0_DA (0x820 >> 2)
155 #define GT_DMA1_DA (0x824 >> 2)
156 #define GT_DMA2_DA (0x828 >> 2)
157 #define GT_DMA3_DA (0x82c >> 2)
158 #define GT_DMA0_NEXT (0x830 >> 2)
159 #define GT_DMA1_NEXT (0x834 >> 2)
160 #define GT_DMA2_NEXT (0x838 >> 2)
161 #define GT_DMA3_NEXT (0x83c >> 2)
162 #define GT_DMA0_CUR (0x870 >> 2)
163 #define GT_DMA1_CUR (0x874 >> 2)
164 #define GT_DMA2_CUR (0x878 >> 2)
165 #define GT_DMA3_CUR (0x87c >> 2)
166
167 /* DMA Channel Control */
168 #define GT_DMA0_CTRL (0x840 >> 2)
169 #define GT_DMA1_CTRL (0x844 >> 2)
170 #define GT_DMA2_CTRL (0x848 >> 2)
171 #define GT_DMA3_CTRL (0x84c >> 2)
172
173 /* DMA Arbiter */
174 #define GT_DMA_ARB (0x860 >> 2)
175
176 /* Timer/Counter */
177 #define GT_TC0 (0x850 >> 2)
178 #define GT_TC1 (0x854 >> 2)
179 #define GT_TC2 (0x858 >> 2)
180 #define GT_TC3 (0x85c >> 2)
181 #define GT_TC_CONTROL (0x864 >> 2)
182
183 /* PCI Internal */
184 #define GT_PCI0_CMD (0xc00 >> 2)
185 #define GT_PCI0_TOR (0xc04 >> 2)
186 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
187 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
188 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
189 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
190 #define GT_PCI1_IACK (0xc30 >> 2)
191 #define GT_PCI0_IACK (0xc34 >> 2)
192 #define GT_PCI0_BARE (0xc3c >> 2)
193 #define GT_PCI0_PREFMBR (0xc40 >> 2)
194 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
195 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
196 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
197 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
198 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
199 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
200 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
201 #define GT_PCI1_CMD (0xc80 >> 2)
202 #define GT_PCI1_TOR (0xc84 >> 2)
203 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
204 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
205 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
206 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
207 #define GT_PCI1_BARE (0xcbc >> 2)
208 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
209 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
210 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
211 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
212 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
213 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
214 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
215 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
216 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
217 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
218 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
219 #define GT_PCI0_CFGDATA (0xcfc >> 2)
220
221 REG32(GT_PCI0_CMD, 0xc00)
222 FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
223 FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
224 #define R_GT_PCI0_CMD_ByteSwap_MASK \
225 (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
226 REG32(GT_PCI1_CMD, 0xc80)
227 FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
228 FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
229 #define R_GT_PCI1_CMD_ByteSwap_MASK \
230 (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
231
232 /* Interrupts */
233 #define GT_INTRCAUSE (0xc18 >> 2)
234 #define GT_INTRMASK (0xc1c >> 2)
235 #define GT_PCI0_ICMASK (0xc24 >> 2)
236 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
237 #define GT_CPU_INTSEL (0xc70 >> 2)
238 #define GT_PCI0_INTSEL (0xc74 >> 2)
239 #define GT_HINTRCAUSE (0xc98 >> 2)
240 #define GT_HINTRMASK (0xc9c >> 2)
241 #define GT_PCI0_HICMASK (0xca4 >> 2)
242 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
243
244 #define PCI_MAPPING_ENTRY(regname) \
245 hwaddr regname ##_start; \
246 hwaddr regname ##_length; \
247 MemoryRegion regname ##_mem
248
249 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
250
251 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
252
253 struct GT64120State {
254 PCIHostState parent_obj;
255
256 uint32_t regs[GT_REGS];
257 PCI_MAPPING_ENTRY(PCI0IO);
258 PCI_MAPPING_ENTRY(PCI0M0);
259 PCI_MAPPING_ENTRY(PCI0M1);
260 PCI_MAPPING_ENTRY(ISD);
261 MemoryRegion pci0_mem;
262 AddressSpace pci0_mem_as;
263
264 /* properties */
265 bool cpu_little_endian;
266 };
267
268 /* Adjust range to avoid touching space which isn't mappable via PCI */
269 /*
270 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
271 * 0x1fc00000 - 0x1fd00000
272 */
273 static void check_reserved_space(hwaddr *start, hwaddr *length)
274 {
275 hwaddr begin = *start;
276 hwaddr end = *start + *length;
277
278 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
279 end = 0x1e000000LL;
280 }
281 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
282 begin = 0x1f100000LL;
283 }
284 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
285 end = 0x1fc00000LL;
286 }
287 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
288 begin = 0x1fd00000LL;
289 }
290 /* XXX: This is broken when a reserved range splits the requested range */
291 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
292 end = 0x1e000000LL;
293 }
294 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
295 end = 0x1fc00000LL;
296 }
297
298 *start = begin;
299 *length = end - begin;
300 }
301
302 static void gt64120_isd_mapping(GT64120State *s)
303 {
304 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
305 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
306 hwaddr length = 0x1000;
307
308 memory_region_transaction_begin();
309
310 if (s->ISD_length) {
311 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
312 }
313 check_reserved_space(&start, &length);
314 length = 0x1000;
315 /* Map new address */
316 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
317 s->ISD_start = start;
318 s->ISD_length = length;
319 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
320
321 memory_region_transaction_commit();
322 }
323
324 static void gt64120_pci_mapping(GT64120State *s)
325 {
326 memory_region_transaction_begin();
327
328 /* Update PCI0IO mapping */
329 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
330 /* Unmap old IO address */
331 if (s->PCI0IO_length) {
332 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
333 object_unparent(OBJECT(&s->PCI0IO_mem));
334 }
335 /* Map new IO address */
336 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
337 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
338 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
339 if (s->PCI0IO_length) {
340 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
341 get_system_io(), 0, s->PCI0IO_length);
342 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
343 &s->PCI0IO_mem);
344 }
345 }
346
347 /* Update PCI0M0 mapping */
348 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
349 /* Unmap old MEM address */
350 if (s->PCI0M0_length) {
351 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
352 object_unparent(OBJECT(&s->PCI0M0_mem));
353 }
354 /* Map new mem address */
355 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
356 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
357 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
358 if (s->PCI0M0_length) {
359 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
360 &s->pci0_mem, s->PCI0M0_start,
361 s->PCI0M0_length);
362 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
363 &s->PCI0M0_mem);
364 }
365 }
366
367 /* Update PCI0M1 mapping */
368 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
369 /* Unmap old MEM address */
370 if (s->PCI0M1_length) {
371 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
372 object_unparent(OBJECT(&s->PCI0M1_mem));
373 }
374 /* Map new mem address */
375 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
376 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
377 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
378 if (s->PCI0M1_length) {
379 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
380 &s->pci0_mem, s->PCI0M1_start,
381 s->PCI0M1_length);
382 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
383 &s->PCI0M1_mem);
384 }
385 }
386
387 memory_region_transaction_commit();
388 }
389
390 static int gt64120_post_load(void *opaque, int version_id)
391 {
392 GT64120State *s = opaque;
393
394 gt64120_isd_mapping(s);
395 gt64120_pci_mapping(s);
396
397 return 0;
398 }
399
400 static const VMStateDescription vmstate_gt64120 = {
401 .name = "gt64120",
402 .version_id = 1,
403 .minimum_version_id = 1,
404 .post_load = gt64120_post_load,
405 .fields = (const VMStateField[]) {
406 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
407 VMSTATE_END_OF_LIST()
408 }
409 };
410
411 static void gt64120_writel(void *opaque, hwaddr addr,
412 uint64_t val, unsigned size)
413 {
414 GT64120State *s = opaque;
415 uint32_t saddr = addr >> 2;
416
417 trace_gt64120_write(addr, val);
418 if (!(s->regs[GT_CPU] & 0x00001000)) {
419 val = bswap32(val);
420 }
421
422 switch (saddr) {
423
424 /* CPU Configuration */
425 case GT_CPU:
426 s->regs[GT_CPU] = val;
427 break;
428 case GT_MULTI:
429 /* Read-only register as only one GT64xxx is present on the CPU bus */
430 break;
431
432 /* CPU Address Decode */
433 case GT_PCI0IOLD:
434 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
435 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
436 gt64120_pci_mapping(s);
437 break;
438 case GT_PCI0M0LD:
439 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
440 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
441 gt64120_pci_mapping(s);
442 break;
443 case GT_PCI0M1LD:
444 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
445 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
446 gt64120_pci_mapping(s);
447 break;
448 case GT_PCI1IOLD:
449 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
450 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
451 break;
452 case GT_PCI1M0LD:
453 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
454 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
455 break;
456 case GT_PCI1M1LD:
457 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
458 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
459 break;
460 case GT_PCI0M0HD:
461 case GT_PCI0M1HD:
462 case GT_PCI0IOHD:
463 s->regs[saddr] = val & 0x0000007f;
464 gt64120_pci_mapping(s);
465 break;
466 case GT_PCI1IOHD:
467 case GT_PCI1M0HD:
468 case GT_PCI1M1HD:
469 s->regs[saddr] = val & 0x0000007f;
470 break;
471 case GT_ISD:
472 s->regs[saddr] = val & 0x00007fff;
473 gt64120_isd_mapping(s);
474 break;
475
476 case GT_PCI0IOREMAP:
477 case GT_PCI0M0REMAP:
478 case GT_PCI0M1REMAP:
479 case GT_PCI1IOREMAP:
480 case GT_PCI1M0REMAP:
481 case GT_PCI1M1REMAP:
482 s->regs[saddr] = val & 0x000007ff;
483 break;
484
485 /* CPU Error Report */
486 case GT_CPUERR_ADDRLO:
487 case GT_CPUERR_ADDRHI:
488 case GT_CPUERR_DATALO:
489 case GT_CPUERR_DATAHI:
490 case GT_CPUERR_PARITY:
491 /* Read-only registers, do nothing */
492 qemu_log_mask(LOG_GUEST_ERROR,
493 "gt64120: Read-only register write "
494 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
495 saddr << 2, size, size << 1, val);
496 break;
497
498 /* CPU Sync Barrier */
499 case GT_PCI0SYNC:
500 case GT_PCI1SYNC:
501 /* Read-only registers, do nothing */
502 qemu_log_mask(LOG_GUEST_ERROR,
503 "gt64120: Read-only register write "
504 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
505 saddr << 2, size, size << 1, val);
506 break;
507
508 /* SDRAM and Device Address Decode */
509 case GT_SCS0LD:
510 case GT_SCS0HD:
511 case GT_SCS1LD:
512 case GT_SCS1HD:
513 case GT_SCS2LD:
514 case GT_SCS2HD:
515 case GT_SCS3LD:
516 case GT_SCS3HD:
517 case GT_CS0LD:
518 case GT_CS0HD:
519 case GT_CS1LD:
520 case GT_CS1HD:
521 case GT_CS2LD:
522 case GT_CS2HD:
523 case GT_CS3LD:
524 case GT_CS3HD:
525 case GT_BOOTLD:
526 case GT_BOOTHD:
527 case GT_ADERR:
528 /* SDRAM Configuration */
529 case GT_SDRAM_CFG:
530 case GT_SDRAM_OPMODE:
531 case GT_SDRAM_BM:
532 case GT_SDRAM_ADDRDECODE:
533 /* Accept and ignore SDRAM interleave configuration */
534 s->regs[saddr] = val;
535 break;
536
537 /* Device Parameters */
538 case GT_DEV_B0:
539 case GT_DEV_B1:
540 case GT_DEV_B2:
541 case GT_DEV_B3:
542 case GT_DEV_BOOT:
543 /* Not implemented */
544 qemu_log_mask(LOG_UNIMP,
545 "gt64120: Unimplemented device register write "
546 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
547 saddr << 2, size, size << 1, val);
548 break;
549
550 /* ECC */
551 case GT_ECC_ERRDATALO:
552 case GT_ECC_ERRDATAHI:
553 case GT_ECC_MEM:
554 case GT_ECC_CALC:
555 case GT_ECC_ERRADDR:
556 /* Read-only registers, do nothing */
557 qemu_log_mask(LOG_GUEST_ERROR,
558 "gt64120: Read-only register write "
559 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
560 saddr << 2, size, size << 1, val);
561 break;
562
563 /* DMA Record */
564 case GT_DMA0_CNT:
565 case GT_DMA1_CNT:
566 case GT_DMA2_CNT:
567 case GT_DMA3_CNT:
568 case GT_DMA0_SA:
569 case GT_DMA1_SA:
570 case GT_DMA2_SA:
571 case GT_DMA3_SA:
572 case GT_DMA0_DA:
573 case GT_DMA1_DA:
574 case GT_DMA2_DA:
575 case GT_DMA3_DA:
576 case GT_DMA0_NEXT:
577 case GT_DMA1_NEXT:
578 case GT_DMA2_NEXT:
579 case GT_DMA3_NEXT:
580 case GT_DMA0_CUR:
581 case GT_DMA1_CUR:
582 case GT_DMA2_CUR:
583 case GT_DMA3_CUR:
584
585 /* DMA Channel Control */
586 case GT_DMA0_CTRL:
587 case GT_DMA1_CTRL:
588 case GT_DMA2_CTRL:
589 case GT_DMA3_CTRL:
590
591 /* DMA Arbiter */
592 case GT_DMA_ARB:
593 /* Not implemented */
594 qemu_log_mask(LOG_UNIMP,
595 "gt64120: Unimplemented DMA register write "
596 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
597 saddr << 2, size, size << 1, val);
598 break;
599
600 /* Timer/Counter */
601 case GT_TC0:
602 case GT_TC1:
603 case GT_TC2:
604 case GT_TC3:
605 case GT_TC_CONTROL:
606 /* Not implemented */
607 qemu_log_mask(LOG_UNIMP,
608 "gt64120: Unimplemented timer register write "
609 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
610 saddr << 2, size, size << 1, val);
611 break;
612
613 /* PCI Internal */
614 case GT_PCI0_CMD:
615 case GT_PCI1_CMD:
616 s->regs[saddr] = val & 0x0401fc0f;
617 break;
618 case GT_PCI0_TOR:
619 case GT_PCI0_BS_SCS10:
620 case GT_PCI0_BS_SCS32:
621 case GT_PCI0_BS_CS20:
622 case GT_PCI0_BS_CS3BT:
623 case GT_PCI1_IACK:
624 case GT_PCI0_IACK:
625 case GT_PCI0_BARE:
626 case GT_PCI0_PREFMBR:
627 case GT_PCI0_SCS10_BAR:
628 case GT_PCI0_SCS32_BAR:
629 case GT_PCI0_CS20_BAR:
630 case GT_PCI0_CS3BT_BAR:
631 case GT_PCI0_SSCS10_BAR:
632 case GT_PCI0_SSCS32_BAR:
633 case GT_PCI0_SCS3BT_BAR:
634 case GT_PCI1_TOR:
635 case GT_PCI1_BS_SCS10:
636 case GT_PCI1_BS_SCS32:
637 case GT_PCI1_BS_CS20:
638 case GT_PCI1_BS_CS3BT:
639 case GT_PCI1_BARE:
640 case GT_PCI1_PREFMBR:
641 case GT_PCI1_SCS10_BAR:
642 case GT_PCI1_SCS32_BAR:
643 case GT_PCI1_CS20_BAR:
644 case GT_PCI1_CS3BT_BAR:
645 case GT_PCI1_SSCS10_BAR:
646 case GT_PCI1_SSCS32_BAR:
647 case GT_PCI1_SCS3BT_BAR:
648 case GT_PCI1_CFGADDR:
649 case GT_PCI1_CFGDATA:
650 /* not implemented */
651 qemu_log_mask(LOG_UNIMP,
652 "gt64120: Unimplemented PCI register write "
653 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
654 saddr << 2, size, size << 1, val);
655 break;
656 case GT_PCI0_CFGADDR:
657 case GT_PCI0_CFGDATA:
658 /* Mapped via in gt64120_pci_mapping() */
659 g_assert_not_reached();
660
661 /* Interrupts */
662 case GT_INTRCAUSE:
663 /* not really implemented */
664 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
665 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
666 trace_gt64120_write_intreg("INTRCAUSE", size, val);
667 break;
668 case GT_INTRMASK:
669 s->regs[saddr] = val & 0x3c3ffffe;
670 trace_gt64120_write_intreg("INTRMASK", size, val);
671 break;
672 case GT_PCI0_ICMASK:
673 s->regs[saddr] = val & 0x03fffffe;
674 trace_gt64120_write_intreg("ICMASK", size, val);
675 break;
676 case GT_PCI0_SERR0MASK:
677 s->regs[saddr] = val & 0x0000003f;
678 trace_gt64120_write_intreg("SERR0MASK", size, val);
679 break;
680
681 /* Reserved when only PCI_0 is configured. */
682 case GT_HINTRCAUSE:
683 case GT_CPU_INTSEL:
684 case GT_PCI0_INTSEL:
685 case GT_HINTRMASK:
686 case GT_PCI0_HICMASK:
687 case GT_PCI1_SERR1MASK:
688 /* not implemented */
689 break;
690
691 /* SDRAM Parameters */
692 case GT_SDRAM_B0:
693 case GT_SDRAM_B1:
694 case GT_SDRAM_B2:
695 case GT_SDRAM_B3:
696 /*
697 * We don't simulate electrical parameters of the SDRAM.
698 * Accept, but ignore the values.
699 */
700 s->regs[saddr] = val;
701 break;
702
703 default:
704 qemu_log_mask(LOG_GUEST_ERROR,
705 "gt64120: Illegal register write "
706 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
707 saddr << 2, size, size << 1, val);
708 break;
709 }
710 }
711
712 static uint64_t gt64120_readl(void *opaque,
713 hwaddr addr, unsigned size)
714 {
715 GT64120State *s = opaque;
716 uint32_t val;
717 uint32_t saddr = addr >> 2;
718
719 switch (saddr) {
720
721 /* CPU Configuration */
722 case GT_MULTI:
723 /*
724 * Only one GT64xxx is present on the CPU bus, return
725 * the initial value.
726 */
727 val = s->regs[saddr];
728 break;
729
730 /* CPU Error Report */
731 case GT_CPUERR_ADDRLO:
732 case GT_CPUERR_ADDRHI:
733 case GT_CPUERR_DATALO:
734 case GT_CPUERR_DATAHI:
735 case GT_CPUERR_PARITY:
736 /* Emulated memory has no error, always return the initial values. */
737 val = s->regs[saddr];
738 break;
739
740 /* CPU Sync Barrier */
741 case GT_PCI0SYNC:
742 case GT_PCI1SYNC:
743 /*
744 * Reading those register should empty all FIFO on the PCI
745 * bus, which are not emulated. The return value should be
746 * a random value that should be ignored.
747 */
748 val = 0xc000ffee;
749 break;
750
751 /* ECC */
752 case GT_ECC_ERRDATALO:
753 case GT_ECC_ERRDATAHI:
754 case GT_ECC_MEM:
755 case GT_ECC_CALC:
756 case GT_ECC_ERRADDR:
757 /* Emulated memory has no error, always return the initial values. */
758 val = s->regs[saddr];
759 break;
760
761 case GT_CPU:
762 case GT_SCS10LD:
763 case GT_SCS10HD:
764 case GT_SCS32LD:
765 case GT_SCS32HD:
766 case GT_CS20LD:
767 case GT_CS20HD:
768 case GT_CS3BOOTLD:
769 case GT_CS3BOOTHD:
770 case GT_SCS10AR:
771 case GT_SCS32AR:
772 case GT_CS20R:
773 case GT_CS3BOOTR:
774 case GT_PCI0IOLD:
775 case GT_PCI0M0LD:
776 case GT_PCI0M1LD:
777 case GT_PCI1IOLD:
778 case GT_PCI1M0LD:
779 case GT_PCI1M1LD:
780 case GT_PCI0IOHD:
781 case GT_PCI0M0HD:
782 case GT_PCI0M1HD:
783 case GT_PCI1IOHD:
784 case GT_PCI1M0HD:
785 case GT_PCI1M1HD:
786 case GT_PCI0IOREMAP:
787 case GT_PCI0M0REMAP:
788 case GT_PCI0M1REMAP:
789 case GT_PCI1IOREMAP:
790 case GT_PCI1M0REMAP:
791 case GT_PCI1M1REMAP:
792 case GT_ISD:
793 val = s->regs[saddr];
794 break;
795 case GT_PCI0_IACK:
796 /* Read the IRQ number */
797 val = pic_read_irq(isa_pic);
798 break;
799
800 /* SDRAM and Device Address Decode */
801 case GT_SCS0LD:
802 case GT_SCS0HD:
803 case GT_SCS1LD:
804 case GT_SCS1HD:
805 case GT_SCS2LD:
806 case GT_SCS2HD:
807 case GT_SCS3LD:
808 case GT_SCS3HD:
809 case GT_CS0LD:
810 case GT_CS0HD:
811 case GT_CS1LD:
812 case GT_CS1HD:
813 case GT_CS2LD:
814 case GT_CS2HD:
815 case GT_CS3LD:
816 case GT_CS3HD:
817 case GT_BOOTLD:
818 case GT_BOOTHD:
819 case GT_ADERR:
820 val = s->regs[saddr];
821 break;
822
823 /* SDRAM Configuration */
824 case GT_SDRAM_CFG:
825 case GT_SDRAM_OPMODE:
826 case GT_SDRAM_BM:
827 case GT_SDRAM_ADDRDECODE:
828 val = s->regs[saddr];
829 break;
830
831 /* SDRAM Parameters */
832 case GT_SDRAM_B0:
833 case GT_SDRAM_B1:
834 case GT_SDRAM_B2:
835 case GT_SDRAM_B3:
836 /*
837 * We don't simulate electrical parameters of the SDRAM.
838 * Just return the last written value.
839 */
840 val = s->regs[saddr];
841 break;
842
843 /* Device Parameters */
844 case GT_DEV_B0:
845 case GT_DEV_B1:
846 case GT_DEV_B2:
847 case GT_DEV_B3:
848 case GT_DEV_BOOT:
849 val = s->regs[saddr];
850 break;
851
852 /* DMA Record */
853 case GT_DMA0_CNT:
854 case GT_DMA1_CNT:
855 case GT_DMA2_CNT:
856 case GT_DMA3_CNT:
857 case GT_DMA0_SA:
858 case GT_DMA1_SA:
859 case GT_DMA2_SA:
860 case GT_DMA3_SA:
861 case GT_DMA0_DA:
862 case GT_DMA1_DA:
863 case GT_DMA2_DA:
864 case GT_DMA3_DA:
865 case GT_DMA0_NEXT:
866 case GT_DMA1_NEXT:
867 case GT_DMA2_NEXT:
868 case GT_DMA3_NEXT:
869 case GT_DMA0_CUR:
870 case GT_DMA1_CUR:
871 case GT_DMA2_CUR:
872 case GT_DMA3_CUR:
873 val = s->regs[saddr];
874 break;
875
876 /* DMA Channel Control */
877 case GT_DMA0_CTRL:
878 case GT_DMA1_CTRL:
879 case GT_DMA2_CTRL:
880 case GT_DMA3_CTRL:
881 val = s->regs[saddr];
882 break;
883
884 /* DMA Arbiter */
885 case GT_DMA_ARB:
886 val = s->regs[saddr];
887 break;
888
889 /* Timer/Counter */
890 case GT_TC0:
891 case GT_TC1:
892 case GT_TC2:
893 case GT_TC3:
894 case GT_TC_CONTROL:
895 val = s->regs[saddr];
896 break;
897
898 /* PCI Internal */
899 case GT_PCI0_CFGADDR:
900 case GT_PCI0_CFGDATA:
901 /* Mapped via in gt64120_pci_mapping() */
902 g_assert_not_reached();
903
904 case GT_PCI0_CMD:
905 case GT_PCI0_TOR:
906 case GT_PCI0_BS_SCS10:
907 case GT_PCI0_BS_SCS32:
908 case GT_PCI0_BS_CS20:
909 case GT_PCI0_BS_CS3BT:
910 case GT_PCI1_IACK:
911 case GT_PCI0_BARE:
912 case GT_PCI0_PREFMBR:
913 case GT_PCI0_SCS10_BAR:
914 case GT_PCI0_SCS32_BAR:
915 case GT_PCI0_CS20_BAR:
916 case GT_PCI0_CS3BT_BAR:
917 case GT_PCI0_SSCS10_BAR:
918 case GT_PCI0_SSCS32_BAR:
919 case GT_PCI0_SCS3BT_BAR:
920 case GT_PCI1_CMD:
921 case GT_PCI1_TOR:
922 case GT_PCI1_BS_SCS10:
923 case GT_PCI1_BS_SCS32:
924 case GT_PCI1_BS_CS20:
925 case GT_PCI1_BS_CS3BT:
926 case GT_PCI1_BARE:
927 case GT_PCI1_PREFMBR:
928 case GT_PCI1_SCS10_BAR:
929 case GT_PCI1_SCS32_BAR:
930 case GT_PCI1_CS20_BAR:
931 case GT_PCI1_CS3BT_BAR:
932 case GT_PCI1_SSCS10_BAR:
933 case GT_PCI1_SSCS32_BAR:
934 case GT_PCI1_SCS3BT_BAR:
935 case GT_PCI1_CFGADDR:
936 case GT_PCI1_CFGDATA:
937 val = s->regs[saddr];
938 break;
939
940 /* Interrupts */
941 case GT_INTRCAUSE:
942 val = s->regs[saddr];
943 trace_gt64120_read_intreg("INTRCAUSE", size, val);
944 break;
945 case GT_INTRMASK:
946 val = s->regs[saddr];
947 trace_gt64120_read_intreg("INTRMASK", size, val);
948 break;
949 case GT_PCI0_ICMASK:
950 val = s->regs[saddr];
951 trace_gt64120_read_intreg("ICMASK", size, val);
952 break;
953 case GT_PCI0_SERR0MASK:
954 val = s->regs[saddr];
955 trace_gt64120_read_intreg("SERR0MASK", size, val);
956 break;
957
958 /* Reserved when only PCI_0 is configured. */
959 case GT_HINTRCAUSE:
960 case GT_CPU_INTSEL:
961 case GT_PCI0_INTSEL:
962 case GT_HINTRMASK:
963 case GT_PCI0_HICMASK:
964 case GT_PCI1_SERR1MASK:
965 val = s->regs[saddr];
966 break;
967
968 default:
969 val = s->regs[saddr];
970 qemu_log_mask(LOG_GUEST_ERROR,
971 "gt64120: Illegal register read "
972 "reg:0x%03x size:%u value:0x%0*x\n",
973 saddr << 2, size, size << 1, val);
974 break;
975 }
976
977 if (!(s->regs[GT_CPU] & 0x00001000)) {
978 val = bswap32(val);
979 }
980 trace_gt64120_read(addr, val);
981
982 return val;
983 }
984
985 static const MemoryRegionOps isd_mem_ops = {
986 .read = gt64120_readl,
987 .write = gt64120_writel,
988 .endianness = DEVICE_NATIVE_ENDIAN,
989 .impl = {
990 .min_access_size = 4,
991 .max_access_size = 4,
992 },
993 };
994
995 static bool bswap(const GT64120State *s)
996 {
997 PCIHostState *phb = PCI_HOST_BRIDGE(s);
998 /*check for bus == 0 && device == 0, Bits 11:15 = Device , Bits 16:23 = Bus*/
999 bool is_phb_dev0 = extract32(phb->config_reg, 11, 13) == 0;
1000 bool le_mode = FIELD_EX32(s->regs[GT_PCI0_CMD], GT_PCI0_CMD, MByteSwap);
1001 /* Only swap for non-bridge devices in big-endian mode */
1002 return !le_mode && !is_phb_dev0;
1003 }
1004
1005 static uint64_t gt64120_pci_data_read(void *opaque, hwaddr addr, unsigned size)
1006 {
1007 GT64120State *s = opaque;
1008 uint32_t val = pci_host_data_le_ops.read(opaque, addr, size);
1009
1010 if (bswap(s)) {
1011 val = bswap32(val);
1012 }
1013 return val;
1014 }
1015
1016 static void gt64120_pci_data_write(void *opaque, hwaddr addr,
1017 uint64_t val, unsigned size)
1018 {
1019 GT64120State *s = opaque;
1020
1021 if (bswap(s)) {
1022 val = bswap32(val);
1023 }
1024 pci_host_data_le_ops.write(opaque, addr, val, size);
1025 }
1026
1027 static const MemoryRegionOps gt64120_pci_data_ops = {
1028 .read = gt64120_pci_data_read,
1029 .write = gt64120_pci_data_write,
1030 .endianness = DEVICE_LITTLE_ENDIAN,
1031 .valid = {
1032 .min_access_size = 4,
1033 .max_access_size = 4,
1034 },
1035 };
1036
1037 static void gt64120_reset(DeviceState *dev)
1038 {
1039 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1040
1041 /* FIXME: Malta specific hw assumptions ahead */
1042
1043 /* CPU Configuration */
1044 s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
1045 s->regs[GT_MULTI] = 0x00000003;
1046
1047 /* CPU Address decode */
1048 s->regs[GT_SCS10LD] = 0x00000000;
1049 s->regs[GT_SCS10HD] = 0x00000007;
1050 s->regs[GT_SCS32LD] = 0x00000008;
1051 s->regs[GT_SCS32HD] = 0x0000000f;
1052 s->regs[GT_CS20LD] = 0x000000e0;
1053 s->regs[GT_CS20HD] = 0x00000070;
1054 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1055 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1056
1057 s->regs[GT_PCI0IOLD] = 0x00000080;
1058 s->regs[GT_PCI0IOHD] = 0x0000000f;
1059 s->regs[GT_PCI0M0LD] = 0x00000090;
1060 s->regs[GT_PCI0M0HD] = 0x0000001f;
1061 s->regs[GT_ISD] = 0x000000a0;
1062 s->regs[GT_PCI0M1LD] = 0x00000790;
1063 s->regs[GT_PCI0M1HD] = 0x0000001f;
1064 s->regs[GT_PCI1IOLD] = 0x00000100;
1065 s->regs[GT_PCI1IOHD] = 0x0000000f;
1066 s->regs[GT_PCI1M0LD] = 0x00000110;
1067 s->regs[GT_PCI1M0HD] = 0x0000001f;
1068 s->regs[GT_PCI1M1LD] = 0x00000120;
1069 s->regs[GT_PCI1M1HD] = 0x0000002f;
1070
1071 s->regs[GT_SCS10AR] = 0x00000000;
1072 s->regs[GT_SCS32AR] = 0x00000008;
1073 s->regs[GT_CS20R] = 0x000000e0;
1074 s->regs[GT_CS3BOOTR] = 0x000000f8;
1075
1076 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1077 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1078 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1079 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1080 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1081 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1082
1083 /* CPU Error Report */
1084 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1085 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1086 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1087 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1088 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1089
1090 /* CPU Sync Barrier */
1091 s->regs[GT_PCI0SYNC] = 0x00000000;
1092 s->regs[GT_PCI1SYNC] = 0x00000000;
1093
1094 /* SDRAM and Device Address Decode */
1095 s->regs[GT_SCS0LD] = 0x00000000;
1096 s->regs[GT_SCS0HD] = 0x00000007;
1097 s->regs[GT_SCS1LD] = 0x00000008;
1098 s->regs[GT_SCS1HD] = 0x0000000f;
1099 s->regs[GT_SCS2LD] = 0x00000010;
1100 s->regs[GT_SCS2HD] = 0x00000017;
1101 s->regs[GT_SCS3LD] = 0x00000018;
1102 s->regs[GT_SCS3HD] = 0x0000001f;
1103 s->regs[GT_CS0LD] = 0x000000c0;
1104 s->regs[GT_CS0HD] = 0x000000c7;
1105 s->regs[GT_CS1LD] = 0x000000c8;
1106 s->regs[GT_CS1HD] = 0x000000cf;
1107 s->regs[GT_CS2LD] = 0x000000d0;
1108 s->regs[GT_CS2HD] = 0x000000df;
1109 s->regs[GT_CS3LD] = 0x000000f0;
1110 s->regs[GT_CS3HD] = 0x000000fb;
1111 s->regs[GT_BOOTLD] = 0x000000fc;
1112 s->regs[GT_BOOTHD] = 0x000000ff;
1113 s->regs[GT_ADERR] = 0xffffffff;
1114
1115 /* SDRAM Configuration */
1116 s->regs[GT_SDRAM_CFG] = 0x00000200;
1117 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1118 s->regs[GT_SDRAM_BM] = 0x00000007;
1119 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1120
1121 /* SDRAM Parameters */
1122 s->regs[GT_SDRAM_B0] = 0x00000005;
1123 s->regs[GT_SDRAM_B1] = 0x00000005;
1124 s->regs[GT_SDRAM_B2] = 0x00000005;
1125 s->regs[GT_SDRAM_B3] = 0x00000005;
1126
1127 /* ECC */
1128 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1129 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1130 s->regs[GT_ECC_MEM] = 0x00000000;
1131 s->regs[GT_ECC_CALC] = 0x00000000;
1132 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1133
1134 /* Device Parameters */
1135 s->regs[GT_DEV_B0] = 0x386fffff;
1136 s->regs[GT_DEV_B1] = 0x386fffff;
1137 s->regs[GT_DEV_B2] = 0x386fffff;
1138 s->regs[GT_DEV_B3] = 0x386fffff;
1139 s->regs[GT_DEV_BOOT] = 0x146fffff;
1140
1141 /* DMA registers are all zeroed at reset */
1142
1143 /* Timer/Counter */
1144 s->regs[GT_TC0] = 0xffffffff;
1145 s->regs[GT_TC1] = 0x00ffffff;
1146 s->regs[GT_TC2] = 0x00ffffff;
1147 s->regs[GT_TC3] = 0x00ffffff;
1148 s->regs[GT_TC_CONTROL] = 0x00000000;
1149
1150 /* PCI Internal */
1151 s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
1152 s->regs[GT_PCI0_TOR] = 0x0000070f;
1153 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1154 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1155 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1156 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1157 s->regs[GT_PCI1_IACK] = 0x00000000;
1158 s->regs[GT_PCI0_IACK] = 0x00000000;
1159 s->regs[GT_PCI0_BARE] = 0x0000000f;
1160 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1161 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1162 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1163 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1164 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1165 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1166 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1167 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1168 s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
1169 s->regs[GT_PCI1_TOR] = 0x0000070f;
1170 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1171 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1172 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1173 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1174 s->regs[GT_PCI1_BARE] = 0x0000000f;
1175 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1176 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1177 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1178 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1179 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1180 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1181 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1182 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1183 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1184 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1185 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1186
1187 /* Interrupt registers are all zeroed at reset */
1188
1189 gt64120_isd_mapping(s);
1190 gt64120_pci_mapping(s);
1191 }
1192
1193 static void gt64120_realize(DeviceState *dev, Error **errp)
1194 {
1195 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1196 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
1197
1198 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1199 "gt64120-isd", 0x1000);
1200 memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1201 address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
1202 phb->bus = pci_root_bus_new(dev, "pci",
1203 &s->pci0_mem,
1204 get_system_io(),
1205 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
1206
1207 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1208 memory_region_init_io(&phb->conf_mem, OBJECT(phb),
1209 &pci_host_conf_le_ops,
1210 s, "pci-conf-idx", 4);
1211 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
1212 &phb->conf_mem, 1);
1213
1214 memory_region_init_io(&phb->data_mem, OBJECT(phb),
1215 &gt64120_pci_data_ops,
1216 s, "pci-conf-data", 4);
1217 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
1218 &phb->data_mem, 1);
1219
1220
1221 /*
1222 * The whole address space decoded by the GT-64120A doesn't generate
1223 * exception when accessing invalid memory. Create an empty slot to
1224 * emulate this feature.
1225 */
1226 empty_slot_init("GT64120", 0, 0x20000000);
1227 }
1228
1229 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1230 {
1231 /* Values from chapter 17.16 "PCI Configuration" */
1232
1233 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */
1234 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */
1235 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */
1236 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */
1237 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */
1238 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */
1239 }
1240
1241 static void gt64120_pci_reset_hold(Object *obj, ResetType type)
1242 {
1243 PCIDevice *d = PCI_DEVICE(obj);
1244
1245 /* Values from chapter 17.16 "PCI Configuration" */
1246
1247 pci_set_word(d->config + PCI_COMMAND, 0);
1248 pci_set_word(d->config + PCI_STATUS,
1249 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1250 pci_config_set_prog_interface(d->config, 0);
1251
1252 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1253 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1254 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1255 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1256 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1257 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1258
1259 pci_set_byte(d->config + 0x3d, 0x01);
1260 }
1261
1262 static void gt64120_pci_class_init(ObjectClass *klass, const void *data)
1263 {
1264 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1265 DeviceClass *dc = DEVICE_CLASS(klass);
1266 ResettableClass *rc = RESETTABLE_CLASS(klass);
1267
1268 rc->phases.hold = gt64120_pci_reset_hold;
1269 k->realize = gt64120_pci_realize;
1270 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1271 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1272 k->revision = 0x10;
1273 k->class_id = PCI_CLASS_BRIDGE_HOST;
1274 /*
1275 * PCI-facing part of the host bridge, not usable without the
1276 * host-facing part, which can't be device_add'ed, yet.
1277 */
1278 dc->user_creatable = false;
1279 }
1280
1281 static const TypeInfo gt64120_pci_info = {
1282 .name = "gt64120_pci",
1283 .parent = TYPE_PCI_DEVICE,
1284 .instance_size = sizeof(PCIDevice),
1285 .class_init = gt64120_pci_class_init,
1286 .interfaces = (const InterfaceInfo[]) {
1287 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1288 { },
1289 },
1290 };
1291
1292 static const Property gt64120_properties[] = {
1293 DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
1294 cpu_little_endian, false),
1295 };
1296
1297 static void gt64120_class_init(ObjectClass *klass, const void *data)
1298 {
1299 DeviceClass *dc = DEVICE_CLASS(klass);
1300
1301 device_class_set_props(dc, gt64120_properties);
1302 dc->realize = gt64120_realize;
1303 device_class_set_legacy_reset(dc, gt64120_reset);
1304 dc->vmsd = &vmstate_gt64120;
1305 }
1306
1307 static const TypeInfo gt64120_info = {
1308 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1309 .parent = TYPE_PCI_HOST_BRIDGE,
1310 .instance_size = sizeof(GT64120State),
1311 .class_init = gt64120_class_init,
1312 };
1313
1314 static void gt64120_pci_register_types(void)
1315 {
1316 type_register_static(&gt64120_info);
1317 type_register_static(&gt64120_pci_info);
1318 }
1319
1320 type_init(gt64120_pci_register_types)