| 1 | /* |
| 2 | * QEMU i440FX PCI Bridge Emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "qemu/range.h" |
| 28 | #include "hw/i386/pc.h" |
| 29 | #include "hw/pci/pci.h" |
| 30 | #include "hw/pci/pci_host.h" |
| 31 | #include "hw/pci-host/i440fx.h" |
| 32 | #include "hw/core/qdev-properties.h" |
| 33 | #include "hw/core/sysbus.h" |
| 34 | #include "qapi/error.h" |
| 35 | #include "migration/vmstate.h" |
| 36 | #include "qapi/visitor.h" |
| 37 | #include "qemu/error-report.h" |
| 38 | #include "qom/object.h" |
| 39 | |
| 40 | /* |
| 41 | * I440FX chipset data sheet. |
| 42 | * https://wiki.qemu.org/File:29054901.pdf |
| 43 | */ |
| 44 | |
| 45 | OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE) |
| 46 | |
| 47 | struct I440FXState { |
| 48 | PCIHostState parent_obj; |
| 49 | |
| 50 | MemoryRegion *system_memory; |
| 51 | MemoryRegion *io_memory; |
| 52 | MemoryRegion *pci_address_space; |
| 53 | MemoryRegion *ram_memory; |
| 54 | Range pci_hole; |
| 55 | uint64_t below_4g_mem_size; |
| 56 | uint64_t above_4g_mem_size; |
| 57 | uint64_t pci_hole64_size; |
| 58 | bool pci_hole64_fix; |
| 59 | |
| 60 | char *pci_type; |
| 61 | }; |
| 62 | |
| 63 | #define I440FX_PAM 0x59 |
| 64 | #define I440FX_PAM_SIZE 7 |
| 65 | #define I440FX_SMRAM 0x72 |
| 66 | |
| 67 | /* Keep it 2G to comply with older win32 guests */ |
| 68 | #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) |
| 69 | |
| 70 | /* Older coreboot versions (4.0 and older) read a config register that doesn't |
| 71 | * exist in real hardware, to get the RAM size from QEMU. |
| 72 | */ |
| 73 | #define I440FX_COREBOOT_RAM_SIZE 0x57 |
| 74 | |
| 75 | static void i440fx_realize(PCIDevice *dev, Error **errp) |
| 76 | { |
| 77 | dev->config[I440FX_SMRAM] = 0x02; |
| 78 | |
| 79 | if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { |
| 80 | warn_report("i440fx doesn't support emulated iommu"); |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
| 85 | { |
| 86 | int i; |
| 87 | PCIDevice *pd = PCI_DEVICE(d); |
| 88 | |
| 89 | memory_region_transaction_begin(); |
| 90 | for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { |
| 91 | pam_update(&d->pam_regions[i], i, |
| 92 | pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); |
| 93 | } |
| 94 | memory_region_set_enabled(&d->smram_region, |
| 95 | !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); |
| 96 | memory_region_set_enabled(&d->smram, |
| 97 | pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); |
| 98 | memory_region_transaction_commit(); |
| 99 | } |
| 100 | |
| 101 | |
| 102 | static void i440fx_write_config(PCIDevice *dev, |
| 103 | uint32_t address, uint32_t val, int len) |
| 104 | { |
| 105 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
| 106 | |
| 107 | /* XXX: implement SMRAM.D_LOCK */ |
| 108 | pci_default_write_config(dev, address, val, len); |
| 109 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
| 110 | range_covers_byte(address, len, I440FX_SMRAM)) { |
| 111 | i440fx_update_memory_mappings(d); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | static int i440fx_post_load(void *opaque, int version_id) |
| 116 | { |
| 117 | PCII440FXState *d = opaque; |
| 118 | |
| 119 | i440fx_update_memory_mappings(d); |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static const VMStateDescription vmstate_i440fx = { |
| 124 | .name = "I440FX", |
| 125 | .version_id = 3, |
| 126 | .minimum_version_id = 3, |
| 127 | .post_load = i440fx_post_load, |
| 128 | .fields = (const VMStateField[]) { |
| 129 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
| 130 | /* Used to be smm_enabled, which was basically always zero because |
| 131 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. |
| 132 | */ |
| 133 | VMSTATE_UNUSED(1), |
| 134 | VMSTATE_END_OF_LIST() |
| 135 | } |
| 136 | }; |
| 137 | |
| 138 | static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, |
| 139 | const char *name, void *opaque, |
| 140 | Error **errp) |
| 141 | { |
| 142 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
| 143 | uint64_t val64; |
| 144 | uint32_t value; |
| 145 | |
| 146 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); |
| 147 | value = val64; |
| 148 | assert(value == val64); |
| 149 | visit_type_uint32(v, name, &value, errp); |
| 150 | } |
| 151 | |
| 152 | static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, |
| 153 | const char *name, void *opaque, |
| 154 | Error **errp) |
| 155 | { |
| 156 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
| 157 | uint64_t val64; |
| 158 | uint32_t value; |
| 159 | |
| 160 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; |
| 161 | value = val64; |
| 162 | assert(value == val64); |
| 163 | visit_type_uint32(v, name, &value, errp); |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * The 64bit PCI hole start is set by the Guest firmware |
| 168 | * as the address of the first 64bit PCI MEM resource. |
| 169 | * If no PCI device has resources on the 64bit area, |
| 170 | * the 64bit PCI hole will start after "over 4G RAM" and the |
| 171 | * reserved space for memory hotplug if any. |
| 172 | */ |
| 173 | static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) |
| 174 | { |
| 175 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 176 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
| 177 | Range w64; |
| 178 | uint64_t value; |
| 179 | |
| 180 | pci_bus_get_w64_range(h->bus, &w64); |
| 181 | value = range_is_empty(&w64) ? 0 : range_lob(&w64); |
| 182 | if (!value && s->pci_hole64_fix) { |
| 183 | value = pc_pci_hole64_start(); |
| 184 | } |
| 185 | return value; |
| 186 | } |
| 187 | |
| 188 | static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, |
| 189 | const char *name, |
| 190 | void *opaque, Error **errp) |
| 191 | { |
| 192 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 193 | uint64_t hole64_start; |
| 194 | |
| 195 | if (!h->bus) { |
| 196 | error_setg(errp, "PCI host bridge not realized"); |
| 197 | return; |
| 198 | } |
| 199 | hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); |
| 200 | visit_type_uint64(v, name, &hole64_start, errp); |
| 201 | } |
| 202 | |
| 203 | /* |
| 204 | * The 64bit PCI hole end is set by the Guest firmware |
| 205 | * as the address of the last 64bit PCI MEM resource. |
| 206 | * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE |
| 207 | * that can be configured by the user. |
| 208 | */ |
| 209 | static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, |
| 210 | const char *name, void *opaque, |
| 211 | Error **errp) |
| 212 | { |
| 213 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 214 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
| 215 | uint64_t hole64_start; |
| 216 | Range w64; |
| 217 | uint64_t value, hole64_end; |
| 218 | |
| 219 | if (!h->bus) { |
| 220 | error_setg(errp, "PCI host bridge not realized"); |
| 221 | return; |
| 222 | } |
| 223 | hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); |
| 224 | pci_bus_get_w64_range(h->bus, &w64); |
| 225 | value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; |
| 226 | hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); |
| 227 | if (s->pci_hole64_fix && value < hole64_end) { |
| 228 | value = hole64_end; |
| 229 | } |
| 230 | visit_type_uint64(v, name, &value, errp); |
| 231 | } |
| 232 | |
| 233 | static void i440fx_pcihost_initfn(Object *obj) |
| 234 | { |
| 235 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
| 236 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); |
| 237 | |
| 238 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, |
| 239 | "pci-conf-idx", 4); |
| 240 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, |
| 241 | "pci-conf-data", 4); |
| 242 | |
| 243 | object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, |
| 244 | (Object **) &s->ram_memory, |
| 245 | qdev_prop_allow_set_link_before_realize, 0); |
| 246 | |
| 247 | object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, |
| 248 | (Object **) &s->pci_address_space, |
| 249 | qdev_prop_allow_set_link_before_realize, 0); |
| 250 | |
| 251 | object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, |
| 252 | (Object **) &s->system_memory, |
| 253 | qdev_prop_allow_set_link_before_realize, 0); |
| 254 | |
| 255 | object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, |
| 256 | (Object **) &s->io_memory, |
| 257 | qdev_prop_allow_set_link_before_realize, 0); |
| 258 | } |
| 259 | |
| 260 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
| 261 | { |
| 262 | ERRP_GUARD(); |
| 263 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); |
| 264 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
| 265 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 266 | PCIBus *b; |
| 267 | PCIDevice *d; |
| 268 | PCII440FXState *f; |
| 269 | unsigned i; |
| 270 | |
| 271 | memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem); |
| 272 | sysbus_init_ioports(sbd, 0xcf8, 4); |
| 273 | |
| 274 | memory_region_add_subregion(s->io_memory, 0xcfc, &phb->data_mem); |
| 275 | sysbus_init_ioports(sbd, 0xcfc, 4); |
| 276 | |
| 277 | /* register i440fx 0xcf8 port as coalesced pio */ |
| 278 | memory_region_set_flush_coalesced(&phb->data_mem); |
| 279 | memory_region_add_coalescing(&phb->conf_mem, 0, 4); |
| 280 | |
| 281 | b = pci_root_bus_new(dev, NULL, s->pci_address_space, |
| 282 | s->io_memory, 0, TYPE_PCI_BUS); |
| 283 | phb->bus = b; |
| 284 | |
| 285 | d = pci_create_simple(b, 0, s->pci_type); |
| 286 | f = I440FX_PCI_DEVICE(d); |
| 287 | |
| 288 | range_set_bounds(&s->pci_hole, s->below_4g_mem_size, |
| 289 | IO_APIC_DEFAULT_ADDRESS - 1); |
| 290 | |
| 291 | /* setup pci memory mapping */ |
| 292 | pc_pci_as_mapping_init(s->system_memory, s->pci_address_space); |
| 293 | |
| 294 | /* if *disabled* show SMRAM to all CPUs */ |
| 295 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
| 296 | s->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE); |
| 297 | memory_region_add_subregion_overlap(s->system_memory, SMRAM_C_BASE, |
| 298 | &f->smram_region, 1); |
| 299 | memory_region_set_enabled(&f->smram_region, true); |
| 300 | |
| 301 | /* smram, as seen by SMM CPUs */ |
| 302 | memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); |
| 303 | memory_region_set_enabled(&f->smram, true); |
| 304 | memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", |
| 305 | s->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE); |
| 306 | memory_region_set_enabled(&f->low_smram, true); |
| 307 | memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram); |
| 308 | object_property_add_const_link(qdev_get_machine(), "smram", |
| 309 | OBJECT(&f->smram)); |
| 310 | |
| 311 | init_pam(&f->pam_regions[0], OBJECT(d), s->ram_memory, s->system_memory, |
| 312 | s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); |
| 313 | for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { |
| 314 | init_pam(&f->pam_regions[i + 1], OBJECT(d), s->ram_memory, |
| 315 | s->system_memory, s->pci_address_space, |
| 316 | PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); |
| 317 | } |
| 318 | |
| 319 | ram_addr_t ram_size = s->below_4g_mem_size + s->above_4g_mem_size; |
| 320 | ram_size = ram_size / 8 / 1024 / 1024; |
| 321 | if (ram_size > 255) { |
| 322 | ram_size = 255; |
| 323 | } |
| 324 | d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; |
| 325 | |
| 326 | i440fx_update_memory_mappings(f); |
| 327 | } |
| 328 | |
| 329 | static void i440fx_class_init(ObjectClass *klass, const void *data) |
| 330 | { |
| 331 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 332 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 333 | |
| 334 | k->realize = i440fx_realize; |
| 335 | k->config_write = i440fx_write_config; |
| 336 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 337 | k->device_id = PCI_DEVICE_ID_INTEL_82441; |
| 338 | k->revision = 0x02; |
| 339 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 340 | dc->desc = "Host bridge"; |
| 341 | dc->vmsd = &vmstate_i440fx; |
| 342 | /* |
| 343 | * PCI-facing part of the host bridge, not usable without the |
| 344 | * host-facing part, which can't be device_add'ed, yet. |
| 345 | */ |
| 346 | dc->user_creatable = false; |
| 347 | dc->hotpluggable = false; |
| 348 | } |
| 349 | |
| 350 | static const TypeInfo i440fx_info = { |
| 351 | .name = TYPE_I440FX_PCI_DEVICE, |
| 352 | .parent = TYPE_PCI_DEVICE, |
| 353 | .instance_size = sizeof(PCII440FXState), |
| 354 | .class_init = i440fx_class_init, |
| 355 | .interfaces = (const InterfaceInfo[]) { |
| 356 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 357 | { }, |
| 358 | }, |
| 359 | }; |
| 360 | |
| 361 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
| 362 | PCIBus *rootbus) |
| 363 | { |
| 364 | return "0000:00"; |
| 365 | } |
| 366 | |
| 367 | static const Property i440fx_props[] = { |
| 368 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, |
| 369 | pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), |
| 370 | DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState, |
| 371 | below_4g_mem_size, 0), |
| 372 | DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, I440FXState, |
| 373 | above_4g_mem_size, 0), |
| 374 | DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), |
| 375 | DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type), |
| 376 | }; |
| 377 | |
| 378 | static void i440fx_pcihost_class_init(ObjectClass *klass, const void *data) |
| 379 | { |
| 380 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 381 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
| 382 | |
| 383 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
| 384 | dc->realize = i440fx_pcihost_realize; |
| 385 | dc->fw_name = "pci"; |
| 386 | device_class_set_props(dc, i440fx_props); |
| 387 | /* Reason: needs to be wired up by pc_init1 */ |
| 388 | dc->user_creatable = false; |
| 389 | |
| 390 | object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32", |
| 391 | i440fx_pcihost_get_pci_hole_start, |
| 392 | NULL, NULL, NULL); |
| 393 | |
| 394 | object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32", |
| 395 | i440fx_pcihost_get_pci_hole_end, |
| 396 | NULL, NULL, NULL); |
| 397 | |
| 398 | object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", |
| 399 | i440fx_pcihost_get_pci_hole64_start, |
| 400 | NULL, NULL, NULL); |
| 401 | |
| 402 | object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", |
| 403 | i440fx_pcihost_get_pci_hole64_end, |
| 404 | NULL, NULL, NULL); |
| 405 | } |
| 406 | |
| 407 | static const TypeInfo i440fx_pcihost_info = { |
| 408 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
| 409 | .parent = TYPE_PCI_HOST_BRIDGE, |
| 410 | .instance_size = sizeof(I440FXState), |
| 411 | .instance_init = i440fx_pcihost_initfn, |
| 412 | .class_init = i440fx_pcihost_class_init, |
| 413 | }; |
| 414 | |
| 415 | static void i440fx_register_types(void) |
| 416 | { |
| 417 | type_register_static(&i440fx_info); |
| 418 | type_register_static(&i440fx_pcihost_info); |
| 419 | } |
| 420 | |
| 421 | type_init(i440fx_register_types) |