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1 /*
2 * Marvell Discovery II MV64361 System Controller for
3 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
4 *
5 * Copyright (c) 2018-2020 BALATON Zoltan
6 *
7 * This work is licensed under the GNU GPL license version 2 or later.
8 *
9 */
10
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
14 #include "hw/core/sysbus.h"
15 #include "hw/pci/pci_device.h"
16 #include "hw/pci/pci_host.h"
17 #include "hw/core/irq.h"
18 #include "hw/intc/i8259.h"
19 #include "hw/core/qdev-properties.h"
20 #include "system/address-spaces.h"
21 #include "qemu/log.h"
22 #include "qemu/error-report.h"
23 #include "trace.h"
24 #include "hw/pci-host/mv64361.h"
25 #include "mv643xx.h"
26
27 #define TYPE_MV64361_PCI_BRIDGE "mv64361-pcibridge"
28
29 static void mv64361_pcibridge_class_init(ObjectClass *klass, const void *data)
30 {
31 DeviceClass *dc = DEVICE_CLASS(klass);
32 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
33
34 k->vendor_id = PCI_VENDOR_ID_MARVELL;
35 k->device_id = PCI_DEVICE_ID_MARVELL_MV6436X;
36 k->class_id = PCI_CLASS_BRIDGE_HOST;
37 /*
38 * PCI-facing part of the host bridge,
39 * not usable without the host-facing part
40 */
41 dc->user_creatable = false;
42 }
43
44 static const TypeInfo mv64361_pcibridge_info = {
45 .name = TYPE_MV64361_PCI_BRIDGE,
46 .parent = TYPE_PCI_DEVICE,
47 .instance_size = sizeof(PCIDevice),
48 .class_init = mv64361_pcibridge_class_init,
49 .interfaces = (const InterfaceInfo[]) {
50 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
51 { },
52 },
53 };
54
55
56 #define TYPE_MV64361_PCI "mv64361-pcihost"
57 OBJECT_DECLARE_SIMPLE_TYPE(MV64361PCIState, MV64361_PCI)
58
59 struct MV64361PCIState {
60 PCIHostState parent_obj;
61
62 uint8_t index;
63 MemoryRegion io;
64 MemoryRegion mem;
65 qemu_irq irq[PCI_NUM_PINS];
66
67 uint32_t io_base;
68 uint32_t io_size;
69 uint32_t mem_base[4];
70 uint32_t mem_size[4];
71 uint64_t remap[5];
72 };
73
74 static void mv64361_pcihost_set_irq(void *opaque, int n, int level)
75 {
76 MV64361PCIState *s = opaque;
77 qemu_set_irq(s->irq[n], level);
78 }
79
80 static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
81 {
82 MV64361PCIState *s = MV64361_PCI(dev);
83 PCIHostState *h = PCI_HOST_BRIDGE(dev);
84 char *name;
85
86 name = g_strdup_printf("pci%d-io", s->index);
87 memory_region_init(&s->io, OBJECT(dev), name, 0x10000);
88 g_free(name);
89 name = g_strdup_printf("pci%d-mem", s->index);
90 memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32);
91 g_free(name);
92 name = g_strdup_printf("pci.%d", s->index);
93 h->bus = pci_register_root_bus(dev, name, mv64361_pcihost_set_irq,
94 pci_swizzle_map_irq_fn, dev,
95 &s->mem, &s->io, 0, 4, TYPE_PCI_BUS);
96 g_free(name);
97 pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE);
98 qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
99 }
100
101 static const Property mv64361_pcihost_props[] = {
102 DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
103 };
104
105 static void mv64361_pcihost_class_init(ObjectClass *klass, const void *data)
106 {
107 DeviceClass *dc = DEVICE_CLASS(klass);
108
109 dc->realize = mv64361_pcihost_realize;
110 device_class_set_props(dc, mv64361_pcihost_props);
111 }
112
113 static const TypeInfo mv64361_pcihost_info = {
114 .name = TYPE_MV64361_PCI,
115 .parent = TYPE_PCI_HOST_BRIDGE,
116 .instance_size = sizeof(MV64361PCIState),
117 .class_init = mv64361_pcihost_class_init,
118 };
119
120 static void mv64361_pci_register_types(void)
121 {
122 type_register_static(&mv64361_pcihost_info);
123 type_register_static(&mv64361_pcibridge_info);
124 }
125
126 type_init(mv64361_pci_register_types)
127
128
129 OBJECT_DECLARE_SIMPLE_TYPE(MV64361State, MV64361)
130
131 struct MV64361State {
132 SysBusDevice parent_obj;
133
134 MemoryRegion regs;
135 MV64361PCIState pci[2];
136 MemoryRegion cpu_win[19];
137 qemu_irq cpu_irq;
138
139 /* registers state */
140 uint32_t cpu_conf;
141 uint32_t regs_base;
142 uint32_t base_addr_enable;
143 uint64_t main_int_cr;
144 uint64_t cpu0_int_mask;
145 uint32_t gpp_io;
146 uint32_t gpp_level;
147 uint32_t gpp_value;
148 uint32_t gpp_int_cr;
149 uint32_t gpp_int_mask;
150 bool gpp_int_level;
151 };
152
153 enum mv64361_irq_cause {
154 MV64361_IRQ_DEVERR = 1,
155 MV64361_IRQ_DMAERR = 2,
156 MV64361_IRQ_CPUERR = 3,
157 MV64361_IRQ_IDMA0 = 4,
158 MV64361_IRQ_IDMA1 = 5,
159 MV64361_IRQ_IDMA2 = 6,
160 MV64361_IRQ_IDMA3 = 7,
161 MV64361_IRQ_TIMER0 = 8,
162 MV64361_IRQ_TIMER1 = 9,
163 MV64361_IRQ_TIMER2 = 10,
164 MV64361_IRQ_TIMER3 = 11,
165 MV64361_IRQ_PCI0 = 12,
166 MV64361_IRQ_SRAMERR = 13,
167 MV64361_IRQ_GBEERR = 14,
168 MV64361_IRQ_CERR = 15,
169 MV64361_IRQ_PCI1 = 16,
170 MV64361_IRQ_DRAMERR = 17,
171 MV64361_IRQ_WDNMI = 18,
172 MV64361_IRQ_WDE = 19,
173 MV64361_IRQ_PCI0IN = 20,
174 MV64361_IRQ_PCI0OUT = 21,
175 MV64361_IRQ_PCI1IN = 22,
176 MV64361_IRQ_PCI1OUT = 23,
177 MV64361_IRQ_P1_GPP0_7 = 24,
178 MV64361_IRQ_P1_GPP8_15 = 25,
179 MV64361_IRQ_P1_GPP16_23 = 26,
180 MV64361_IRQ_P1_GPP24_31 = 27,
181 MV64361_IRQ_P1_CPU_DB = 28,
182 /* 29-31: reserved */
183 MV64361_IRQ_GBE0 = 32,
184 MV64361_IRQ_GBE1 = 33,
185 MV64361_IRQ_GBE2 = 34,
186 /* 35: reserved */
187 MV64361_IRQ_SDMA0 = 36,
188 MV64361_IRQ_TWSI = 37,
189 MV64361_IRQ_SDMA1 = 38,
190 MV64361_IRQ_BRG = 39,
191 MV64361_IRQ_MPSC0 = 40,
192 MV64361_IRQ_MPSC1 = 41,
193 MV64361_IRQ_G0RX = 42,
194 MV64361_IRQ_G0TX = 43,
195 MV64361_IRQ_G0MISC = 44,
196 MV64361_IRQ_G1RX = 45,
197 MV64361_IRQ_G1TX = 46,
198 MV64361_IRQ_G1MISC = 47,
199 MV64361_IRQ_G2RX = 48,
200 MV64361_IRQ_G2TX = 49,
201 MV64361_IRQ_G2MISC = 50,
202 /* 51-55: reserved */
203 MV64361_IRQ_P0_GPP0_7 = 56,
204 MV64361_IRQ_P0_GPP8_15 = 57,
205 MV64361_IRQ_P0_GPP16_23 = 58,
206 MV64361_IRQ_P0_GPP24_31 = 59,
207 MV64361_IRQ_P0_CPU_DB = 60,
208 /* 61-63: reserved */
209 };
210
211 PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n)
212 {
213 MV64361State *mv = MV64361(dev);
214 return PCI_HOST_BRIDGE(&mv->pci[n])->bus;
215 }
216
217 static void unmap_region(MemoryRegion *mr)
218 {
219 if (memory_region_is_mapped(mr)) {
220 memory_region_del_subregion(get_system_memory(), mr);
221 object_unparent(OBJECT(mr));
222 }
223 }
224
225 static void map_pci_region(MemoryRegion *mr, MemoryRegion *parent,
226 struct Object *owner, const char *name,
227 hwaddr poffs, uint64_t size, hwaddr moffs)
228 {
229 memory_region_init_alias(mr, owner, name, parent, poffs, size);
230 memory_region_add_subregion(get_system_memory(), moffs, mr);
231 trace_mv64361_region_map(name, poffs, size, moffs);
232 }
233
234 static void set_mem_windows(MV64361State *s, uint32_t val)
235 {
236 MV64361PCIState *p;
237 MemoryRegion *mr;
238 uint32_t mask;
239 int i;
240
241 val &= 0x1fffff;
242 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) {
243 if ((val & mask) != (s->base_addr_enable & mask)) {
244 trace_mv64361_region_enable(!(val & mask) ? "enable" : "disable", i);
245 /*
246 * 0-3 are SDRAM chip selects but we map all RAM directly
247 * 4-7 are device chip selects (not sure what those are)
248 * 8 is Boot device (ROM) chip select but we map that directly too
249 */
250 if (i == 9) {
251 p = &s->pci[0];
252 mr = &s->cpu_win[i];
253 unmap_region(mr);
254 if (!(val & mask)) {
255 map_pci_region(mr, &p->io, OBJECT(s), "pci0-io-win",
256 p->remap[4], (p->io_size + 1) << 16,
257 (p->io_base & 0xfffff) << 16);
258 }
259 } else if (i == 10) {
260 p = &s->pci[0];
261 mr = &s->cpu_win[i];
262 unmap_region(mr);
263 if (!(val & mask)) {
264 map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem0-win",
265 p->remap[0], (p->mem_size[0] + 1) << 16,
266 (p->mem_base[0] & 0xfffff) << 16);
267 }
268 } else if (i == 11) {
269 p = &s->pci[0];
270 mr = &s->cpu_win[i];
271 unmap_region(mr);
272 if (!(val & mask)) {
273 map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem1-win",
274 p->remap[1], (p->mem_size[1] + 1) << 16,
275 (p->mem_base[1] & 0xfffff) << 16);
276 }
277 } else if (i == 12) {
278 p = &s->pci[0];
279 mr = &s->cpu_win[i];
280 unmap_region(mr);
281 if (!(val & mask)) {
282 map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem2-win",
283 p->remap[2], (p->mem_size[2] + 1) << 16,
284 (p->mem_base[2] & 0xfffff) << 16);
285 }
286 } else if (i == 13) {
287 p = &s->pci[0];
288 mr = &s->cpu_win[i];
289 unmap_region(mr);
290 if (!(val & mask)) {
291 map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem3-win",
292 p->remap[3], (p->mem_size[3] + 1) << 16,
293 (p->mem_base[3] & 0xfffff) << 16);
294 }
295 } else if (i == 14) {
296 p = &s->pci[1];
297 mr = &s->cpu_win[i];
298 unmap_region(mr);
299 if (!(val & mask)) {
300 map_pci_region(mr, &p->io, OBJECT(s), "pci1-io-win",
301 p->remap[4], (p->io_size + 1) << 16,
302 (p->io_base & 0xfffff) << 16);
303 }
304 } else if (i == 15) {
305 p = &s->pci[1];
306 mr = &s->cpu_win[i];
307 unmap_region(mr);
308 if (!(val & mask)) {
309 map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem0-win",
310 p->remap[0], (p->mem_size[0] + 1) << 16,
311 (p->mem_base[0] & 0xfffff) << 16);
312 }
313 } else if (i == 16) {
314 p = &s->pci[1];
315 mr = &s->cpu_win[i];
316 unmap_region(mr);
317 if (!(val & mask)) {
318 map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem1-win",
319 p->remap[1], (p->mem_size[1] + 1) << 16,
320 (p->mem_base[1] & 0xfffff) << 16);
321 }
322 } else if (i == 17) {
323 p = &s->pci[1];
324 mr = &s->cpu_win[i];
325 unmap_region(mr);
326 if (!(val & mask)) {
327 map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem2-win",
328 p->remap[2], (p->mem_size[2] + 1) << 16,
329 (p->mem_base[2] & 0xfffff) << 16);
330 }
331 } else if (i == 18) {
332 p = &s->pci[1];
333 mr = &s->cpu_win[i];
334 unmap_region(mr);
335 if (!(val & mask)) {
336 map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem3-win",
337 p->remap[3], (p->mem_size[3] + 1) << 16,
338 (p->mem_base[3] & 0xfffff) << 16);
339 }
340 /* 19 is integrated SRAM */
341 } else if (i == 20) {
342 mr = &s->regs;
343 unmap_region(mr);
344 if (!(val & mask)) {
345 memory_region_add_subregion(get_system_memory(),
346 (s->regs_base & 0xfffff) << 16, mr);
347 }
348 }
349 }
350 }
351 s->base_addr_enable = val;
352 }
353
354 static void mv64361_update_irq(void *opaque, int n, int level)
355 {
356 MV64361State *s = opaque;
357 uint64_t val = s->main_int_cr;
358
359 if (level) {
360 val |= BIT_ULL(n);
361 } else {
362 val &= ~BIT_ULL(n);
363 }
364 if ((s->main_int_cr & s->cpu0_int_mask) != (val & s->cpu0_int_mask)) {
365 qemu_set_irq(s->cpu_irq, level);
366 }
367 s->main_int_cr = val;
368 }
369
370 static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
371 {
372 MV64361State *s = MV64361(opaque);
373 uint32_t ret = 0;
374
375 switch (addr) {
376 case MV64340_CPU_CONFIG:
377 ret = s->cpu_conf;
378 break;
379 case MV64340_PCI_0_IO_BASE_ADDR:
380 ret = s->pci[0].io_base;
381 break;
382 case MV64340_PCI_0_IO_SIZE:
383 ret = s->pci[0].io_size;
384 break;
385 case MV64340_PCI_0_IO_ADDR_REMAP:
386 ret = s->pci[0].remap[4] >> 16;
387 break;
388 case MV64340_PCI_0_MEMORY0_BASE_ADDR:
389 ret = s->pci[0].mem_base[0];
390 break;
391 case MV64340_PCI_0_MEMORY0_SIZE:
392 ret = s->pci[0].mem_size[0];
393 break;
394 case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP:
395 ret = (s->pci[0].remap[0] & 0xffff0000) >> 16;
396 break;
397 case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP:
398 ret = s->pci[0].remap[0] >> 32;
399 break;
400 case MV64340_PCI_0_MEMORY1_BASE_ADDR:
401 ret = s->pci[0].mem_base[1];
402 break;
403 case MV64340_PCI_0_MEMORY1_SIZE:
404 ret = s->pci[0].mem_size[1];
405 break;
406 case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP:
407 ret = (s->pci[0].remap[1] & 0xffff0000) >> 16;
408 break;
409 case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP:
410 ret = s->pci[0].remap[1] >> 32;
411 break;
412 case MV64340_PCI_0_MEMORY2_BASE_ADDR:
413 ret = s->pci[0].mem_base[2];
414 break;
415 case MV64340_PCI_0_MEMORY2_SIZE:
416 ret = s->pci[0].mem_size[2];
417 break;
418 case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP:
419 ret = (s->pci[0].remap[2] & 0xffff0000) >> 16;
420 break;
421 case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP:
422 ret = s->pci[0].remap[2] >> 32;
423 break;
424 case MV64340_PCI_0_MEMORY3_BASE_ADDR:
425 ret = s->pci[0].mem_base[3];
426 break;
427 case MV64340_PCI_0_MEMORY3_SIZE:
428 ret = s->pci[0].mem_size[3];
429 break;
430 case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP:
431 ret = (s->pci[0].remap[3] & 0xffff0000) >> 16;
432 break;
433 case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP:
434 ret = s->pci[0].remap[3] >> 32;
435 break;
436 case MV64340_PCI_1_IO_BASE_ADDR:
437 ret = s->pci[1].io_base;
438 break;
439 case MV64340_PCI_1_IO_SIZE:
440 ret = s->pci[1].io_size;
441 break;
442 case MV64340_PCI_1_IO_ADDR_REMAP:
443 ret = s->pci[1].remap[4] >> 16;
444 break;
445 case MV64340_PCI_1_MEMORY0_BASE_ADDR:
446 ret = s->pci[1].mem_base[0];
447 break;
448 case MV64340_PCI_1_MEMORY0_SIZE:
449 ret = s->pci[1].mem_size[0];
450 break;
451 case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP:
452 ret = (s->pci[1].remap[0] & 0xffff0000) >> 16;
453 break;
454 case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP:
455 ret = s->pci[1].remap[0] >> 32;
456 break;
457 case MV64340_PCI_1_MEMORY1_BASE_ADDR:
458 ret = s->pci[1].mem_base[1];
459 break;
460 case MV64340_PCI_1_MEMORY1_SIZE:
461 ret = s->pci[1].mem_size[1];
462 break;
463 case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP:
464 ret = (s->pci[1].remap[1] & 0xffff0000) >> 16;
465 break;
466 case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP:
467 ret = s->pci[1].remap[1] >> 32;
468 break;
469 case MV64340_PCI_1_MEMORY2_BASE_ADDR:
470 ret = s->pci[1].mem_base[2];
471 break;
472 case MV64340_PCI_1_MEMORY2_SIZE:
473 ret = s->pci[1].mem_size[2];
474 break;
475 case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP:
476 ret = (s->pci[1].remap[2] & 0xffff0000) >> 16;
477 break;
478 case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP:
479 ret = s->pci[1].remap[2] >> 32;
480 break;
481 case MV64340_PCI_1_MEMORY3_BASE_ADDR:
482 ret = s->pci[1].mem_base[3];
483 break;
484 case MV64340_PCI_1_MEMORY3_SIZE:
485 ret = s->pci[1].mem_size[3];
486 break;
487 case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP:
488 ret = (s->pci[1].remap[3] & 0xffff0000) >> 16;
489 break;
490 case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP:
491 ret = s->pci[1].remap[3] >> 32;
492 break;
493 case MV64340_INTERNAL_SPACE_BASE_ADDR:
494 ret = s->regs_base;
495 break;
496 case MV64340_BASE_ADDR_ENABLE:
497 ret = s->base_addr_enable;
498 break;
499 case MV64340_PCI_0_CONFIG_ADDR:
500 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), 0, size);
501 break;
502 case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ...
503 MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3:
504 ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]),
505 addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, size);
506 break;
507 case MV64340_PCI_1_CONFIG_ADDR:
508 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size);
509 break;
510 case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ...
511 MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3:
512 ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]),
513 addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, size);
514 break;
515 case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG:
516 /* FIXME: Should this be sent via the PCI bus somehow? */
517 if (s->gpp_int_level && (s->gpp_value & BIT(31))) {
518 ret = pic_read_irq(isa_pic);
519 }
520 break;
521 case MV64340_MAIN_INTERRUPT_CAUSE_LOW:
522 ret = s->main_int_cr;
523 break;
524 case MV64340_MAIN_INTERRUPT_CAUSE_HIGH:
525 ret = s->main_int_cr >> 32;
526 break;
527 case MV64340_CPU_INTERRUPT0_MASK_LOW:
528 ret = s->cpu0_int_mask;
529 break;
530 case MV64340_CPU_INTERRUPT0_MASK_HIGH:
531 ret = s->cpu0_int_mask >> 32;
532 break;
533 case MV64340_CPU_INTERRUPT0_SELECT_CAUSE:
534 ret = s->main_int_cr;
535 if (s->main_int_cr & s->cpu0_int_mask) {
536 if (!(s->main_int_cr & s->cpu0_int_mask & 0xffffffff)) {
537 ret = s->main_int_cr >> 32 | BIT(30);
538 } else if ((s->main_int_cr & s->cpu0_int_mask) >> 32) {
539 ret |= BIT(31);
540 }
541 }
542 break;
543 case MV64340_ETH_PHY_ADDR:
544 ret = 0x98;
545 break;
546 case MV64340_ETH_SMI:
547 ret = BIT(27);
548 break;
549 case MV64340_CUNIT_ARBITER_CONTROL_REG:
550 ret = 0x11ff0000 | (s->gpp_int_level << 10);
551 break;
552 case MV64340_GPP_IO_CONTROL:
553 ret = s->gpp_io;
554 break;
555 case MV64340_GPP_LEVEL_CONTROL:
556 ret = s->gpp_level;
557 break;
558 case MV64340_GPP_VALUE:
559 ret = s->gpp_value;
560 break;
561 case MV64340_GPP_VALUE_SET:
562 case MV64340_GPP_VALUE_CLEAR:
563 ret = 0;
564 break;
565 case MV64340_GPP_INTERRUPT_CAUSE:
566 ret = s->gpp_int_cr;
567 break;
568 case MV64340_GPP_INTERRUPT_MASK0:
569 case MV64340_GPP_INTERRUPT_MASK1:
570 ret = s->gpp_int_mask;
571 break;
572 default:
573 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%"
574 HWADDR_PRIx "\n", __func__, addr);
575 break;
576 }
577 if (addr != MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG) {
578 trace_mv64361_reg_read(addr, ret);
579 }
580 return ret;
581 }
582
583 static void warn_swap_bit(uint64_t val)
584 {
585 if ((val & 0x3000000ULL) >> 24 != 1) {
586 qemu_log_mask(LOG_UNIMP, "%s: Data swap not implemented", __func__);
587 }
588 }
589
590 static void mv64361_set_pci_mem_remap(MV64361State *s, int bus, int idx,
591 uint64_t val, bool high)
592 {
593 if (high) {
594 s->pci[bus].remap[idx] = val;
595 } else {
596 s->pci[bus].remap[idx] &= 0xffffffff00000000ULL;
597 s->pci[bus].remap[idx] |= (val & 0xffffULL) << 16;
598 }
599 }
600
601 static void mv64361_write(void *opaque, hwaddr addr, uint64_t val,
602 unsigned int size)
603 {
604 MV64361State *s = MV64361(opaque);
605
606 trace_mv64361_reg_write(addr, val);
607 switch (addr) {
608 case MV64340_CPU_CONFIG:
609 s->cpu_conf = val & 0xe4e3bffULL;
610 s->cpu_conf |= BIT(23);
611 break;
612 case MV64340_PCI_0_IO_BASE_ADDR:
613 s->pci[0].io_base = val & 0x30fffffULL;
614 warn_swap_bit(val);
615 if (!(s->cpu_conf & BIT(27))) {
616 s->pci[0].remap[4] = (val & 0xffffULL) << 16;
617 }
618 break;
619 case MV64340_PCI_0_IO_SIZE:
620 s->pci[0].io_size = val & 0xffffULL;
621 break;
622 case MV64340_PCI_0_IO_ADDR_REMAP:
623 s->pci[0].remap[4] = (val & 0xffffULL) << 16;
624 break;
625 case MV64340_PCI_0_MEMORY0_BASE_ADDR:
626 s->pci[0].mem_base[0] = val & 0x70fffffULL;
627 warn_swap_bit(val);
628 if (!(s->cpu_conf & BIT(27))) {
629 mv64361_set_pci_mem_remap(s, 0, 0, val, false);
630 }
631 break;
632 case MV64340_PCI_0_MEMORY0_SIZE:
633 s->pci[0].mem_size[0] = val & 0xffffULL;
634 break;
635 case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP:
636 case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP:
637 mv64361_set_pci_mem_remap(s, 0, 0, val,
638 (addr == MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP));
639 break;
640 case MV64340_PCI_0_MEMORY1_BASE_ADDR:
641 s->pci[0].mem_base[1] = val & 0x70fffffULL;
642 warn_swap_bit(val);
643 if (!(s->cpu_conf & BIT(27))) {
644 mv64361_set_pci_mem_remap(s, 0, 1, val, false);
645 }
646 break;
647 case MV64340_PCI_0_MEMORY1_SIZE:
648 s->pci[0].mem_size[1] = val & 0xffffULL;
649 break;
650 case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP:
651 case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP:
652 mv64361_set_pci_mem_remap(s, 0, 1, val,
653 (addr == MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP));
654 break;
655 case MV64340_PCI_0_MEMORY2_BASE_ADDR:
656 s->pci[0].mem_base[2] = val & 0x70fffffULL;
657 warn_swap_bit(val);
658 if (!(s->cpu_conf & BIT(27))) {
659 mv64361_set_pci_mem_remap(s, 0, 2, val, false);
660 }
661 break;
662 case MV64340_PCI_0_MEMORY2_SIZE:
663 s->pci[0].mem_size[2] = val & 0xffffULL;
664 break;
665 case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP:
666 case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP:
667 mv64361_set_pci_mem_remap(s, 0, 2, val,
668 (addr == MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP));
669 break;
670 case MV64340_PCI_0_MEMORY3_BASE_ADDR:
671 s->pci[0].mem_base[3] = val & 0x70fffffULL;
672 warn_swap_bit(val);
673 if (!(s->cpu_conf & BIT(27))) {
674 mv64361_set_pci_mem_remap(s, 0, 3, val, false);
675 }
676 break;
677 case MV64340_PCI_0_MEMORY3_SIZE:
678 s->pci[0].mem_size[3] = val & 0xffffULL;
679 break;
680 case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP:
681 case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP:
682 mv64361_set_pci_mem_remap(s, 0, 3, val,
683 (addr == MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP));
684 break;
685 case MV64340_PCI_1_IO_BASE_ADDR:
686 s->pci[1].io_base = val & 0x30fffffULL;
687 warn_swap_bit(val);
688 if (!(s->cpu_conf & BIT(27))) {
689 s->pci[1].remap[4] = (val & 0xffffULL) << 16;
690 }
691 break;
692 case MV64340_PCI_1_IO_SIZE:
693 s->pci[1].io_size = val & 0xffffULL;
694 break;
695 case MV64340_PCI_1_MEMORY0_BASE_ADDR:
696 s->pci[1].mem_base[0] = val & 0x70fffffULL;
697 warn_swap_bit(val);
698 if (!(s->cpu_conf & BIT(27))) {
699 mv64361_set_pci_mem_remap(s, 1, 0, val, false);
700 }
701 break;
702 case MV64340_PCI_1_MEMORY0_SIZE:
703 s->pci[1].mem_size[0] = val & 0xffffULL;
704 break;
705 case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP:
706 case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP:
707 mv64361_set_pci_mem_remap(s, 1, 0, val,
708 (addr == MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP));
709 break;
710 case MV64340_PCI_1_MEMORY1_BASE_ADDR:
711 s->pci[1].mem_base[1] = val & 0x70fffffULL;
712 warn_swap_bit(val);
713 if (!(s->cpu_conf & BIT(27))) {
714 mv64361_set_pci_mem_remap(s, 1, 1, val, false);
715 }
716 break;
717 case MV64340_PCI_1_MEMORY1_SIZE:
718 s->pci[1].mem_size[1] = val & 0xffffULL;
719 break;
720 case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP:
721 case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP:
722 mv64361_set_pci_mem_remap(s, 1, 1, val,
723 (addr == MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP));
724 break;
725 case MV64340_PCI_1_MEMORY2_BASE_ADDR:
726 s->pci[1].mem_base[2] = val & 0x70fffffULL;
727 warn_swap_bit(val);
728 if (!(s->cpu_conf & BIT(27))) {
729 mv64361_set_pci_mem_remap(s, 1, 2, val, false);
730 }
731 break;
732 case MV64340_PCI_1_MEMORY2_SIZE:
733 s->pci[1].mem_size[2] = val & 0xffffULL;
734 break;
735 case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP:
736 case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP:
737 mv64361_set_pci_mem_remap(s, 1, 2, val,
738 (addr == MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP));
739 break;
740 case MV64340_PCI_1_MEMORY3_BASE_ADDR:
741 s->pci[1].mem_base[3] = val & 0x70fffffULL;
742 warn_swap_bit(val);
743 if (!(s->cpu_conf & BIT(27))) {
744 mv64361_set_pci_mem_remap(s, 1, 3, val, false);
745 }
746 break;
747 case MV64340_PCI_1_MEMORY3_SIZE:
748 s->pci[1].mem_size[3] = val & 0xffffULL;
749 break;
750 case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP:
751 case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP:
752 mv64361_set_pci_mem_remap(s, 1, 3, val,
753 (addr == MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP));
754 break;
755 case MV64340_INTERNAL_SPACE_BASE_ADDR:
756 s->regs_base = val & 0xfffffULL;
757 break;
758 case MV64340_BASE_ADDR_ENABLE:
759 set_mem_windows(s, val);
760 break;
761 case MV64340_PCI_0_CONFIG_ADDR:
762 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), 0, val, size);
763 break;
764 case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ...
765 MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3:
766 pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]),
767 addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, val, size);
768 break;
769 case MV64340_PCI_1_CONFIG_ADDR:
770 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size);
771 break;
772 case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ...
773 MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3:
774 pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]),
775 addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, val, size);
776 break;
777 case MV64340_CPU_INTERRUPT0_MASK_LOW:
778 s->cpu0_int_mask &= 0xffffffff00000000ULL;
779 s->cpu0_int_mask |= val & 0xffffffffULL;
780 break;
781 case MV64340_CPU_INTERRUPT0_MASK_HIGH:
782 s->cpu0_int_mask &= 0xffffffffULL;
783 s->cpu0_int_mask |= val << 32;
784 break;
785 case MV64340_CUNIT_ARBITER_CONTROL_REG:
786 s->gpp_int_level = !!(val & BIT(10));
787 break;
788 case MV64340_GPP_IO_CONTROL:
789 s->gpp_io = val;
790 break;
791 case MV64340_GPP_LEVEL_CONTROL:
792 s->gpp_level = val;
793 break;
794 case MV64340_GPP_VALUE:
795 s->gpp_value &= ~s->gpp_io;
796 s->gpp_value |= val & s->gpp_io;
797 break;
798 case MV64340_GPP_VALUE_SET:
799 s->gpp_value |= val & s->gpp_io;
800 break;
801 case MV64340_GPP_VALUE_CLEAR:
802 s->gpp_value &= ~(val & s->gpp_io);
803 break;
804 case MV64340_GPP_INTERRUPT_CAUSE:
805 if (!s->gpp_int_level && val != s->gpp_int_cr) {
806 int i;
807 uint32_t ch = s->gpp_int_cr ^ val;
808 s->gpp_int_cr = val;
809 for (i = 0; i < 4; i++) {
810 if ((ch & 0xff << i) && !(val & 0xff << i)) {
811 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + i, 0);
812 }
813 }
814 } else {
815 s->gpp_int_cr = val;
816 }
817 break;
818 case MV64340_GPP_INTERRUPT_MASK0:
819 case MV64340_GPP_INTERRUPT_MASK1:
820 s->gpp_int_mask = val;
821 break;
822 default:
823 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%"
824 HWADDR_PRIx " = %"PRIx64"\n", __func__, addr, val);
825 break;
826 }
827 }
828
829 static const MemoryRegionOps mv64361_ops = {
830 .read = mv64361_read,
831 .write = mv64361_write,
832 .valid.min_access_size = 1,
833 .valid.max_access_size = 4,
834 .endianness = DEVICE_LITTLE_ENDIAN,
835 };
836
837 static void mv64361_gpp_irq(void *opaque, int n, int level)
838 {
839 MV64361State *s = opaque;
840 uint32_t mask = BIT(n);
841 uint32_t val = s->gpp_value & ~mask;
842
843 if (s->gpp_level & mask) {
844 level = !level;
845 }
846 val |= level << n;
847 if (val > s->gpp_value) {
848 s->gpp_value = val;
849 s->gpp_int_cr |= mask;
850 if (s->gpp_int_mask & mask) {
851 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + n / 8, 1);
852 }
853 } else if (val < s->gpp_value) {
854 int b = n / 8;
855 s->gpp_value = val;
856 if (s->gpp_int_level && !(val & 0xff << b)) {
857 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + b, 0);
858 }
859 }
860 }
861
862 static void mv64361_realize(DeviceState *dev, Error **errp)
863 {
864 MV64361State *s = MV64361(dev);
865 int i;
866
867 s->base_addr_enable = 0x1fffff;
868 memory_region_init_io(&s->regs, OBJECT(s), &mv64361_ops, s,
869 TYPE_MV64361, 0x10000);
870 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs);
871 for (i = 0; i < 2; i++) {
872 g_autofree char *name = g_strdup_printf("pcihost%d", i);
873 object_initialize_child(OBJECT(dev), name, &s->pci[i],
874 TYPE_MV64361_PCI);
875 DeviceState *pci = DEVICE(&s->pci[i]);
876 qdev_prop_set_uint8(pci, "index", i);
877 sysbus_realize_and_unref(SYS_BUS_DEVICE(pci), &error_fatal);
878 }
879 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq);
880 qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32);
881 }
882
883 static void mv64361_reset(DeviceState *dev)
884 {
885 MV64361State *s = MV64361(dev);
886 int i, j;
887
888 /*
889 * These values may be board specific
890 * Real chip supports init from an eprom but that's not modelled
891 */
892 set_mem_windows(s, 0x1fffff);
893 s->cpu_conf = 0x28000ff;
894 s->regs_base = 0x100f100;
895 s->pci[0].io_base = 0x100f800;
896 s->pci[0].io_size = 0xff;
897 s->pci[0].mem_base[0] = 0x100c000;
898 s->pci[0].mem_size[0] = 0x1fff;
899 s->pci[0].mem_base[1] = 0x100f900;
900 s->pci[0].mem_size[1] = 0xff;
901 s->pci[0].mem_base[2] = 0x100f400;
902 s->pci[0].mem_size[2] = 0x1ff;
903 s->pci[0].mem_base[3] = 0x100f600;
904 s->pci[0].mem_size[3] = 0x1ff;
905 s->pci[1].io_base = 0x100fe00;
906 s->pci[1].io_size = 0xff;
907 s->pci[1].mem_base[0] = 0x1008000;
908 s->pci[1].mem_size[0] = 0x3fff;
909 s->pci[1].mem_base[1] = 0x100fd00;
910 s->pci[1].mem_size[1] = 0xff;
911 s->pci[1].mem_base[2] = 0x1002600;
912 s->pci[1].mem_size[2] = 0x1ff;
913 s->pci[1].mem_base[3] = 0x100ff80;
914 s->pci[1].mem_size[3] = 0x7f;
915 for (i = 0; i < 2; i++) {
916 for (j = 0; j < 4; j++) {
917 s->pci[i].remap[j] = s->pci[i].mem_base[j] << 16;
918 }
919 }
920 s->pci[0].remap[1] = 0;
921 s->pci[1].remap[1] = 0;
922 set_mem_windows(s, 0xfbfff);
923 }
924
925 static void mv64361_class_init(ObjectClass *klass, const void *data)
926 {
927 DeviceClass *dc = DEVICE_CLASS(klass);
928
929 dc->realize = mv64361_realize;
930 device_class_set_legacy_reset(dc, mv64361_reset);
931 }
932
933 static const TypeInfo mv64361_type_info = {
934 .name = TYPE_MV64361,
935 .parent = TYPE_SYS_BUS_DEVICE,
936 .instance_size = sizeof(MV64361State),
937 .class_init = mv64361_class_init,
938 };
939
940 static void mv64361_register_types(void)
941 {
942 type_register_static(&mv64361_type_info);
943 }
944
945 type_init(mv64361_register_types)