| 1 | /* |
| 2 | * QEMU PowerPC PowerNV Proxy PHB model |
| 3 | * |
| 4 | * Copyright (c) 2022, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qemu/log.h" |
| 12 | #include "qapi/visitor.h" |
| 13 | #include "qapi/error.h" |
| 14 | #include "hw/pci-host/pnv_phb.h" |
| 15 | #include "hw/pci-host/pnv_phb3.h" |
| 16 | #include "hw/pci-host/pnv_phb4.h" |
| 17 | #include "hw/ppc/pnv.h" |
| 18 | #include "hw/core/qdev-properties.h" |
| 19 | #include "qom/object.h" |
| 20 | #include "system/system.h" |
| 21 | |
| 22 | |
| 23 | /* |
| 24 | * Set the QOM parent and parent bus of an object child. If the device |
| 25 | * state associated with the child has an id, use it as QOM id. |
| 26 | * Otherwise use object_typename[index] as QOM id. |
| 27 | * |
| 28 | * This helper does both operations at the same time because setting |
| 29 | * a new QOM child will erase the bus parent of the device. This happens |
| 30 | * because object_unparent() will call object_property_del_child(), |
| 31 | * which in turn calls the property release callback prop->release if |
| 32 | * it's defined. In our case this callback is set to |
| 33 | * object_finalize_child_property(), which was assigned during the |
| 34 | * first object_property_add_child() call. This callback will end up |
| 35 | * calling device_unparent(), and this function removes the device |
| 36 | * from its parent bus. |
| 37 | * |
| 38 | * The QOM and parent bus to be set aren´t necessarily related, so |
| 39 | * let's receive both as arguments. |
| 40 | */ |
| 41 | static bool pnv_parent_fixup(Object *parent, BusState *parent_bus, |
| 42 | Object *child, int index, |
| 43 | Error **errp) |
| 44 | { |
| 45 | g_autofree char *default_id = |
| 46 | g_strdup_printf("%s[%d]", object_get_typename(child), index); |
| 47 | const char *dev_id = DEVICE(child)->id; |
| 48 | |
| 49 | if (child->parent == parent) { |
| 50 | return true; |
| 51 | } |
| 52 | |
| 53 | object_ref(child); |
| 54 | object_unparent(child); |
| 55 | object_property_add_child(parent, dev_id ? dev_id : default_id, child); |
| 56 | object_unref(child); |
| 57 | |
| 58 | if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) { |
| 59 | return false; |
| 60 | } |
| 61 | |
| 62 | return true; |
| 63 | } |
| 64 | |
| 65 | static Object *pnv_phb_user_get_parent(PnvChip *chip, PnvPHB *phb, Error **errp) |
| 66 | { |
| 67 | if (phb->version == 3) { |
| 68 | return OBJECT(pnv_chip_add_phb(chip, phb)); |
| 69 | } else { |
| 70 | return OBJECT(pnv_pec_add_phb(chip, phb, errp)); |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * User created devices won't have the initial setup that default |
| 76 | * devices have. This setup consists of assigning a parent device |
| 77 | * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent |
| 78 | * of the PHB. |
| 79 | */ |
| 80 | static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp) |
| 81 | { |
| 82 | PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); |
| 83 | PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); |
| 84 | Object *parent = NULL; |
| 85 | |
| 86 | if (!chip) { |
| 87 | error_setg(errp, "invalid chip id: %d", phb->chip_id); |
| 88 | return false; |
| 89 | } |
| 90 | |
| 91 | parent = pnv_phb_user_get_parent(chip, phb, errp); |
| 92 | if (!parent) { |
| 93 | return false; |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * Reparent user created devices to the chip to build |
| 98 | * correctly the device tree. pnv_xscom_dt() needs every |
| 99 | * PHB to be a child of the chip to build the DT correctly. |
| 100 | */ |
| 101 | if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)), |
| 102 | OBJECT(phb), phb->phb_id, errp)) { |
| 103 | return false; |
| 104 | } |
| 105 | |
| 106 | return true; |
| 107 | } |
| 108 | |
| 109 | static void pnv_phb_realize(DeviceState *dev, Error **errp) |
| 110 | { |
| 111 | PnvPHB *phb = PNV_PHB(dev); |
| 112 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
| 113 | g_autofree char *phb_typename = NULL; |
| 114 | |
| 115 | if (!phb->version) { |
| 116 | error_setg(errp, "version not specified"); |
| 117 | return; |
| 118 | } |
| 119 | |
| 120 | switch (phb->version) { |
| 121 | case 3: |
| 122 | phb_typename = g_strdup(TYPE_PNV_PHB3); |
| 123 | break; |
| 124 | case 4: |
| 125 | phb_typename = g_strdup(TYPE_PNV_PHB4); |
| 126 | break; |
| 127 | case 5: |
| 128 | phb_typename = g_strdup(TYPE_PNV_PHB5); |
| 129 | break; |
| 130 | default: |
| 131 | g_assert_not_reached(); |
| 132 | } |
| 133 | |
| 134 | phb->backend = object_new(phb_typename); |
| 135 | object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); |
| 136 | |
| 137 | /* Passthrough child device properties to the proxy device */ |
| 138 | object_property_set_uint(phb->backend, "index", phb->phb_id, errp); |
| 139 | object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); |
| 140 | object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); |
| 141 | |
| 142 | /* |
| 143 | * Handle user created devices. User devices will not have a |
| 144 | * pointer to a chip (PHB3) and a PEC (PHB4/5). |
| 145 | */ |
| 146 | if (!phb->chip && !phb->pec) { |
| 147 | if (!pnv_phb_user_device_init(phb, errp)) { |
| 148 | return; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | if (phb->version == 3) { |
| 153 | object_property_set_link(phb->backend, "chip", |
| 154 | OBJECT(phb->chip), errp); |
| 155 | } else { |
| 156 | object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); |
| 157 | } |
| 158 | |
| 159 | if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { |
| 160 | return; |
| 161 | } |
| 162 | |
| 163 | if (phb->version == 3) { |
| 164 | pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); |
| 165 | } else { |
| 166 | pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); |
| 167 | } |
| 168 | |
| 169 | if (defaults_enabled()) { |
| 170 | PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); |
| 171 | |
| 172 | pci_realize_and_unref(root, pci->bus, errp); |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, |
| 177 | PCIBus *rootbus) |
| 178 | { |
| 179 | PnvPHB *phb = PNV_PHB(host_bridge); |
| 180 | |
| 181 | snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", |
| 182 | phb->chip_id, phb->phb_id); |
| 183 | return phb->bus_path; |
| 184 | } |
| 185 | |
| 186 | static const Property pnv_phb_properties[] = { |
| 187 | DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), |
| 188 | DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), |
| 189 | DEFINE_PROP_UINT32("version", PnvPHB, version, 0), |
| 190 | |
| 191 | DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), |
| 192 | |
| 193 | DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, |
| 194 | PnvPhb4PecState *), |
| 195 | }; |
| 196 | |
| 197 | static void pnv_phb_class_init(ObjectClass *klass, const void *data) |
| 198 | { |
| 199 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
| 200 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 201 | |
| 202 | hc->root_bus_path = pnv_phb_root_bus_path; |
| 203 | dc->realize = pnv_phb_realize; |
| 204 | device_class_set_props(dc, pnv_phb_properties); |
| 205 | dc->user_creatable = true; |
| 206 | } |
| 207 | |
| 208 | static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type) |
| 209 | { |
| 210 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); |
| 211 | PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj); |
| 212 | PCIDevice *d = PCI_DEVICE(obj); |
| 213 | uint8_t *conf = d->config; |
| 214 | |
| 215 | if (rpc->parent_phases.hold) { |
| 216 | rpc->parent_phases.hold(obj, type); |
| 217 | } |
| 218 | |
| 219 | if (phb_rp->version == 3) { |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | /* PHB4 and later requires these extra reset steps */ |
| 224 | pci_byte_test_and_set_mask(conf + PCI_IO_BASE, |
| 225 | PCI_IO_RANGE_MASK & 0xff); |
| 226 | pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, |
| 227 | PCI_IO_RANGE_MASK & 0xff); |
| 228 | pci_set_word(conf + PCI_MEMORY_BASE, 0); |
| 229 | pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); |
| 230 | pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); |
| 231 | pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); |
| 232 | pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ |
| 233 | pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); |
| 234 | pci_config_set_interrupt_pin(conf, 0); |
| 235 | } |
| 236 | |
| 237 | static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) |
| 238 | { |
| 239 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); |
| 240 | PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); |
| 241 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); |
| 242 | PCIDevice *pci = PCI_DEVICE(dev); |
| 243 | uint16_t device_id = 0; |
| 244 | Error *local_err = NULL; |
| 245 | int chip_id, index; |
| 246 | |
| 247 | /* |
| 248 | * 'index' will be used both as a PCIE slot value and to calculate |
| 249 | * QOM id. 'chip_id' is going to be used as PCIE chassis for the |
| 250 | * root port. |
| 251 | */ |
| 252 | chip_id = object_property_get_int(OBJECT(bus), "chip-id", &local_err); |
| 253 | if (local_err) { |
| 254 | error_propagate(errp, local_err); |
| 255 | return; |
| 256 | } |
| 257 | index = object_property_get_int(OBJECT(bus), "phb-id", &local_err); |
| 258 | if (local_err) { |
| 259 | error_propagate(errp, local_err); |
| 260 | return; |
| 261 | } |
| 262 | |
| 263 | /* Set unique chassis/slot values for the root port */ |
| 264 | qdev_prop_set_uint8(dev, "chassis", chip_id); |
| 265 | qdev_prop_set_uint16(dev, "slot", index); |
| 266 | |
| 267 | /* |
| 268 | * User created root ports are QOM parented to one of |
| 269 | * the peripheral containers but it's already at the right |
| 270 | * parent bus. Change the QOM parent to be the same as the |
| 271 | * parent bus it's already assigned to. |
| 272 | */ |
| 273 | if (!pnv_parent_fixup(OBJECT(bus), BUS(bus), OBJECT(dev), |
| 274 | index, errp)) { |
| 275 | return; |
| 276 | } |
| 277 | |
| 278 | rpc->parent_realize(dev, &local_err); |
| 279 | if (local_err) { |
| 280 | error_propagate(errp, local_err); |
| 281 | return; |
| 282 | } |
| 283 | |
| 284 | switch (phb_rp->version) { |
| 285 | case 3: |
| 286 | device_id = PNV_PHB3_DEVICE_ID; |
| 287 | break; |
| 288 | case 4: |
| 289 | device_id = PNV_PHB4_DEVICE_ID; |
| 290 | break; |
| 291 | case 5: |
| 292 | device_id = PNV_PHB5_DEVICE_ID; |
| 293 | break; |
| 294 | default: |
| 295 | g_assert_not_reached(); |
| 296 | } |
| 297 | |
| 298 | pci_config_set_device_id(pci->config, device_id); |
| 299 | pci_config_set_interrupt_pin(pci->config, 0); |
| 300 | } |
| 301 | |
| 302 | static const Property pnv_phb_root_port_properties[] = { |
| 303 | DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), |
| 304 | }; |
| 305 | |
| 306 | static void pnv_phb_root_port_class_init(ObjectClass *klass, const void *data) |
| 307 | { |
| 308 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 309 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 310 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 311 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); |
| 312 | |
| 313 | dc->desc = "IBM PHB PCIE Root Port"; |
| 314 | |
| 315 | device_class_set_props(dc, pnv_phb_root_port_properties); |
| 316 | device_class_set_parent_realize(dc, pnv_phb_root_port_realize, |
| 317 | &rpc->parent_realize); |
| 318 | resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold, |
| 319 | NULL, &rpc->parent_phases); |
| 320 | dc->user_creatable = true; |
| 321 | |
| 322 | k->vendor_id = PCI_VENDOR_ID_IBM; |
| 323 | /* device_id will be written during realize() */ |
| 324 | k->device_id = 0; |
| 325 | k->revision = 0; |
| 326 | |
| 327 | rpc->exp_offset = 0x48; |
| 328 | rpc->aer_offset = 0x100; |
| 329 | } |
| 330 | |
| 331 | static const TypeInfo pnv_phb_type_info = { |
| 332 | .name = TYPE_PNV_PHB, |
| 333 | .parent = TYPE_PCIE_HOST_BRIDGE, |
| 334 | .instance_size = sizeof(PnvPHB), |
| 335 | .class_init = pnv_phb_class_init, |
| 336 | }; |
| 337 | |
| 338 | static const TypeInfo pnv_phb_root_port_info = { |
| 339 | .name = TYPE_PNV_PHB_ROOT_PORT, |
| 340 | .parent = TYPE_PCIE_ROOT_PORT, |
| 341 | .instance_size = sizeof(PnvPHBRootPort), |
| 342 | .class_init = pnv_phb_root_port_class_init, |
| 343 | }; |
| 344 | |
| 345 | static void pnv_phb_register_types(void) |
| 346 | { |
| 347 | type_register_static(&pnv_phb_type_info); |
| 348 | type_register_static(&pnv_phb_root_port_info); |
| 349 | } |
| 350 | |
| 351 | type_init(pnv_phb_register_types) |