| 1 | /* |
| 2 | * QEMU PowerPC PowerNV (POWER8) PHB3 model |
| 3 | * |
| 4 | * Copyright (c) 2014-2020, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "qemu/log.h" |
| 11 | #include "qemu/bswap.h" |
| 12 | #include "qapi/visitor.h" |
| 13 | #include "qapi/error.h" |
| 14 | #include "hw/pci-host/pnv_phb3_regs.h" |
| 15 | #include "hw/pci-host/pnv_phb.h" |
| 16 | #include "hw/pci-host/pnv_phb3.h" |
| 17 | #include "hw/pci/pcie_host.h" |
| 18 | #include "hw/pci/pcie_port.h" |
| 19 | #include "hw/ppc/pnv.h" |
| 20 | #include "hw/ppc/pnv_chip.h" |
| 21 | #include "hw/core/irq.h" |
| 22 | #include "hw/core/qdev-properties.h" |
| 23 | #include "qom/object.h" |
| 24 | #include "system/system.h" |
| 25 | |
| 26 | #define phb3_error(phb, fmt, ...) \ |
| 27 | qemu_log_mask(LOG_GUEST_ERROR, "phb3[%d:%d]: " fmt "\n", \ |
| 28 | (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) |
| 29 | |
| 30 | static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) |
| 31 | { |
| 32 | PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); |
| 33 | uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; |
| 34 | uint8_t bus, devfn; |
| 35 | |
| 36 | if (!(addr >> 63)) { |
| 37 | return NULL; |
| 38 | } |
| 39 | bus = (addr >> 52) & 0xff; |
| 40 | devfn = (addr >> 44) & 0xff; |
| 41 | |
| 42 | return pci_find_device(pci->bus, bus, devfn); |
| 43 | } |
| 44 | |
| 45 | /* |
| 46 | * The CONFIG_DATA register expects little endian accesses, but as the |
| 47 | * region is big endian, we have to swap the value. |
| 48 | */ |
| 49 | static void pnv_phb3_config_write(PnvPHB3 *phb, unsigned off, |
| 50 | unsigned size, uint64_t val) |
| 51 | { |
| 52 | uint32_t cfg_addr, limit; |
| 53 | PCIDevice *pdev; |
| 54 | |
| 55 | pdev = pnv_phb3_find_cfg_dev(phb); |
| 56 | if (!pdev) { |
| 57 | return; |
| 58 | } |
| 59 | cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; |
| 60 | cfg_addr |= off; |
| 61 | limit = pci_config_size(pdev); |
| 62 | if (limit <= cfg_addr) { |
| 63 | /* |
| 64 | * conventional pci device can be behind pcie-to-pci bridge. |
| 65 | * 256 <= addr < 4K has no effects. |
| 66 | */ |
| 67 | return; |
| 68 | } |
| 69 | switch (size) { |
| 70 | case 1: |
| 71 | break; |
| 72 | case 2: |
| 73 | val = bswap16(val); |
| 74 | break; |
| 75 | case 4: |
| 76 | val = bswap32(val); |
| 77 | break; |
| 78 | default: |
| 79 | g_assert_not_reached(); |
| 80 | } |
| 81 | pci_host_config_write_common(pdev, cfg_addr, limit, val, size); |
| 82 | } |
| 83 | |
| 84 | static uint64_t pnv_phb3_config_read(PnvPHB3 *phb, unsigned off, |
| 85 | unsigned size) |
| 86 | { |
| 87 | uint32_t cfg_addr, limit; |
| 88 | PCIDevice *pdev; |
| 89 | uint64_t val; |
| 90 | |
| 91 | pdev = pnv_phb3_find_cfg_dev(phb); |
| 92 | if (!pdev) { |
| 93 | return ~0ull; |
| 94 | } |
| 95 | cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; |
| 96 | cfg_addr |= off; |
| 97 | limit = pci_config_size(pdev); |
| 98 | if (limit <= cfg_addr) { |
| 99 | /* |
| 100 | * conventional pci device can be behind pcie-to-pci bridge. |
| 101 | * 256 <= addr < 4K has no effects. |
| 102 | */ |
| 103 | return ~0ull; |
| 104 | } |
| 105 | val = pci_host_config_read_common(pdev, cfg_addr, limit, size); |
| 106 | switch (size) { |
| 107 | case 1: |
| 108 | return val; |
| 109 | case 2: |
| 110 | return bswap16(val); |
| 111 | case 4: |
| 112 | return bswap32(val); |
| 113 | default: |
| 114 | g_assert_not_reached(); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void pnv_phb3_check_m32(PnvPHB3 *phb) |
| 119 | { |
| 120 | uint64_t base, start, size; |
| 121 | MemoryRegion *parent; |
| 122 | PnvPBCQState *pbcq = &phb->pbcq; |
| 123 | |
| 124 | if (memory_region_is_mapped(&phb->mr_m32)) { |
| 125 | memory_region_del_subregion(phb->mr_m32.container, &phb->mr_m32); |
| 126 | } |
| 127 | |
| 128 | if (!(phb->regs[PHB_PHB3_CONFIG >> 3] & PHB_PHB3C_M32_EN)) { |
| 129 | return; |
| 130 | } |
| 131 | |
| 132 | /* Grab geometry from registers */ |
| 133 | base = phb->regs[PHB_M32_BASE_ADDR >> 3]; |
| 134 | start = phb->regs[PHB_M32_START_ADDR >> 3]; |
| 135 | size = ~(phb->regs[PHB_M32_BASE_MASK >> 3] | 0xfffc000000000000ull) + 1; |
| 136 | |
| 137 | /* Check if it matches an enabled MMIO region in the PBCQ */ |
| 138 | if (memory_region_is_mapped(&pbcq->mmbar0) && |
| 139 | base >= pbcq->mmio0_base && |
| 140 | (base + size) <= (pbcq->mmio0_base + pbcq->mmio0_size)) { |
| 141 | parent = &pbcq->mmbar0; |
| 142 | base -= pbcq->mmio0_base; |
| 143 | } else if (memory_region_is_mapped(&pbcq->mmbar1) && |
| 144 | base >= pbcq->mmio1_base && |
| 145 | (base + size) <= (pbcq->mmio1_base + pbcq->mmio1_size)) { |
| 146 | parent = &pbcq->mmbar1; |
| 147 | base -= pbcq->mmio1_base; |
| 148 | } else { |
| 149 | return; |
| 150 | } |
| 151 | |
| 152 | /* Create alias */ |
| 153 | memory_region_init_alias(&phb->mr_m32, OBJECT(phb), "phb3-m32", |
| 154 | &phb->pci_mmio, start, size); |
| 155 | memory_region_add_subregion(parent, base, &phb->mr_m32); |
| 156 | } |
| 157 | |
| 158 | static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index) |
| 159 | { |
| 160 | uint64_t base, start, size, m64; |
| 161 | MemoryRegion *parent; |
| 162 | PnvPBCQState *pbcq = &phb->pbcq; |
| 163 | |
| 164 | if (memory_region_is_mapped(&phb->mr_m64[index])) { |
| 165 | /* Should we destroy it in RCU friendly way... ? */ |
| 166 | memory_region_del_subregion(phb->mr_m64[index].container, |
| 167 | &phb->mr_m64[index]); |
| 168 | } |
| 169 | |
| 170 | /* Get table entry */ |
| 171 | m64 = phb->ioda_M64BT[index]; |
| 172 | |
| 173 | if (!(m64 & IODA2_M64BT_ENABLE)) { |
| 174 | return; |
| 175 | } |
| 176 | |
| 177 | /* Grab geometry from registers */ |
| 178 | base = GETFIELD(IODA2_M64BT_BASE, m64) << 20; |
| 179 | if (m64 & IODA2_M64BT_SINGLE_PE) { |
| 180 | base &= ~0x1ffffffull; |
| 181 | } |
| 182 | size = GETFIELD(IODA2_M64BT_MASK, m64) << 20; |
| 183 | size |= 0xfffc000000000000ull; |
| 184 | size = ~size + 1; |
| 185 | start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]); |
| 186 | |
| 187 | /* Check if it matches an enabled MMIO region in the PBCQ */ |
| 188 | if (memory_region_is_mapped(&pbcq->mmbar0) && |
| 189 | base >= pbcq->mmio0_base && |
| 190 | (base + size) <= (pbcq->mmio0_base + pbcq->mmio0_size)) { |
| 191 | parent = &pbcq->mmbar0; |
| 192 | base -= pbcq->mmio0_base; |
| 193 | } else if (memory_region_is_mapped(&pbcq->mmbar1) && |
| 194 | base >= pbcq->mmio1_base && |
| 195 | (base + size) <= (pbcq->mmio1_base + pbcq->mmio1_size)) { |
| 196 | parent = &pbcq->mmbar1; |
| 197 | base -= pbcq->mmio1_base; |
| 198 | } else { |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | /* Create alias */ |
| 203 | memory_region_init_alias(&phb->mr_m64[index], OBJECT(phb), "phb3-m64", |
| 204 | &phb->pci_mmio, start, size); |
| 205 | memory_region_add_subregion(parent, base, &phb->mr_m64[index]); |
| 206 | } |
| 207 | |
| 208 | static void pnv_phb3_check_all_m64s(PnvPHB3 *phb) |
| 209 | { |
| 210 | uint64_t i; |
| 211 | |
| 212 | for (i = 0; i < PNV_PHB3_NUM_M64; i++) { |
| 213 | pnv_phb3_check_m64(phb, i); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val) |
| 218 | { |
| 219 | uint8_t server, prio; |
| 220 | |
| 221 | phb->ioda_LXIVT[idx] = val & (IODA2_LXIVT_SERVER | |
| 222 | IODA2_LXIVT_PRIORITY | |
| 223 | IODA2_LXIVT_NODE_ID); |
| 224 | server = GETFIELD(IODA2_LXIVT_SERVER, val); |
| 225 | prio = GETFIELD(IODA2_LXIVT_PRIORITY, val); |
| 226 | |
| 227 | /* |
| 228 | * The low order 2 bits are the link pointer (Type II interrupts). |
| 229 | * Shift back to get a valid IRQ server. |
| 230 | */ |
| 231 | server >>= 2; |
| 232 | |
| 233 | ics_write_xive(&phb->lsis, idx, server, prio, prio); |
| 234 | } |
| 235 | |
| 236 | static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, |
| 237 | unsigned *out_table, unsigned *out_idx) |
| 238 | { |
| 239 | uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; |
| 240 | unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg); |
| 241 | unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg); |
| 242 | unsigned int mask; |
| 243 | uint64_t *tptr = NULL; |
| 244 | |
| 245 | switch (table) { |
| 246 | case IODA2_TBL_LIST: |
| 247 | tptr = phb->ioda_LIST; |
| 248 | mask = 7; |
| 249 | break; |
| 250 | case IODA2_TBL_LXIVT: |
| 251 | tptr = phb->ioda_LXIVT; |
| 252 | mask = 7; |
| 253 | break; |
| 254 | case IODA2_TBL_IVC_CAM: |
| 255 | case IODA2_TBL_RBA: |
| 256 | mask = 31; |
| 257 | break; |
| 258 | case IODA2_TBL_RCAM: |
| 259 | mask = 63; |
| 260 | break; |
| 261 | case IODA2_TBL_MRT: |
| 262 | mask = 7; |
| 263 | break; |
| 264 | case IODA2_TBL_PESTA: |
| 265 | case IODA2_TBL_PESTB: |
| 266 | mask = 255; |
| 267 | break; |
| 268 | case IODA2_TBL_TVT: |
| 269 | tptr = phb->ioda_TVT; |
| 270 | mask = 511; |
| 271 | break; |
| 272 | case IODA2_TBL_TCAM: |
| 273 | case IODA2_TBL_TDR: |
| 274 | mask = 63; |
| 275 | break; |
| 276 | case IODA2_TBL_M64BT: |
| 277 | tptr = phb->ioda_M64BT; |
| 278 | mask = 15; |
| 279 | break; |
| 280 | case IODA2_TBL_M32DT: |
| 281 | tptr = phb->ioda_MDT; |
| 282 | mask = 255; |
| 283 | break; |
| 284 | case IODA2_TBL_PEEV: |
| 285 | tptr = phb->ioda_PEEV; |
| 286 | mask = 3; |
| 287 | break; |
| 288 | default: |
| 289 | phb3_error(phb, "invalid IODA table %d", table); |
| 290 | return NULL; |
| 291 | } |
| 292 | index &= mask; |
| 293 | if (out_idx) { |
| 294 | *out_idx = index; |
| 295 | } |
| 296 | if (out_table) { |
| 297 | *out_table = table; |
| 298 | } |
| 299 | if (tptr) { |
| 300 | tptr += index; |
| 301 | } |
| 302 | if (adreg & PHB_IODA_AD_AUTOINC) { |
| 303 | index = (index + 1) & mask; |
| 304 | adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index); |
| 305 | } |
| 306 | phb->regs[PHB_IODA_ADDR >> 3] = adreg; |
| 307 | return tptr; |
| 308 | } |
| 309 | |
| 310 | static uint64_t pnv_phb3_ioda_read(PnvPHB3 *phb) |
| 311 | { |
| 312 | unsigned table; |
| 313 | uint64_t *tptr; |
| 314 | |
| 315 | tptr = pnv_phb3_ioda_access(phb, &table, NULL); |
| 316 | if (!tptr) { |
| 317 | /* Return 0 on unsupported tables, not ff's */ |
| 318 | return 0; |
| 319 | } |
| 320 | return *tptr; |
| 321 | } |
| 322 | |
| 323 | static void pnv_phb3_ioda_write(PnvPHB3 *phb, uint64_t val) |
| 324 | { |
| 325 | unsigned table, idx; |
| 326 | uint64_t *tptr; |
| 327 | |
| 328 | tptr = pnv_phb3_ioda_access(phb, &table, &idx); |
| 329 | if (!tptr) { |
| 330 | return; |
| 331 | } |
| 332 | |
| 333 | /* Handle side effects */ |
| 334 | switch (table) { |
| 335 | case IODA2_TBL_LXIVT: |
| 336 | pnv_phb3_lxivt_write(phb, idx, val); |
| 337 | break; |
| 338 | case IODA2_TBL_M64BT: |
| 339 | *tptr = val; |
| 340 | pnv_phb3_check_m64(phb, idx); |
| 341 | break; |
| 342 | default: |
| 343 | *tptr = val; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * This is called whenever the PHB LSI, MSI source ID register or |
| 349 | * the PBCQ irq filters are written. |
| 350 | */ |
| 351 | void pnv_phb3_remap_irqs(PnvPHB3 *phb) |
| 352 | { |
| 353 | ICSState *ics = &phb->lsis; |
| 354 | uint32_t local, global, count, mask, comp; |
| 355 | uint64_t baren; |
| 356 | PnvPBCQState *pbcq = &phb->pbcq; |
| 357 | |
| 358 | /* |
| 359 | * First check if we are enabled. Unlike real HW we don't separate |
| 360 | * TX and RX so we enable if both are set |
| 361 | */ |
| 362 | baren = pbcq->nest_regs[PBCQ_NEST_BAR_EN]; |
| 363 | if (!(baren & PBCQ_NEST_BAR_EN_IRSN_RX) || |
| 364 | !(baren & PBCQ_NEST_BAR_EN_IRSN_TX)) { |
| 365 | ics->offset = 0; |
| 366 | return; |
| 367 | } |
| 368 | |
| 369 | /* Grab local LSI source ID */ |
| 370 | local = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]) << 3; |
| 371 | |
| 372 | /* Grab global one and compare */ |
| 373 | global = GETFIELD(PBCQ_NEST_LSI_SRC, |
| 374 | pbcq->nest_regs[PBCQ_NEST_LSI_SRC_ID]) << 3; |
| 375 | if (global != local) { |
| 376 | /* |
| 377 | * This happens during initialization, let's come back when we |
| 378 | * are properly configured |
| 379 | */ |
| 380 | ics->offset = 0; |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | /* Get the base on the powerbus */ |
| 385 | comp = GETFIELD(PBCQ_NEST_IRSN_COMP, |
| 386 | pbcq->nest_regs[PBCQ_NEST_IRSN_COMPARE]); |
| 387 | mask = GETFIELD(PBCQ_NEST_IRSN_COMP, |
| 388 | pbcq->nest_regs[PBCQ_NEST_IRSN_MASK]); |
| 389 | count = ((~mask) + 1) & 0x7ffff; |
| 390 | phb->total_irq = count; |
| 391 | |
| 392 | /* Sanity checks */ |
| 393 | if ((global + PNV_PHB3_NUM_LSI) > count) { |
| 394 | phb3_error(phb, "LSIs out of reach: LSI base=%d total irq=%d", global, |
| 395 | count); |
| 396 | } |
| 397 | |
| 398 | if (count > 2048) { |
| 399 | phb3_error(phb, "More interrupts than supported: %d", count); |
| 400 | } |
| 401 | |
| 402 | if ((comp & mask) != comp) { |
| 403 | phb3_error(phb, "IRQ compare bits not in mask: comp=0x%x mask=0x%x", |
| 404 | comp, mask); |
| 405 | comp &= mask; |
| 406 | } |
| 407 | /* Setup LSI offset */ |
| 408 | ics->offset = comp + global; |
| 409 | |
| 410 | /* Setup MSI offset */ |
| 411 | pnv_phb3_msi_update_config(&phb->msis, comp, count - PNV_PHB3_NUM_LSI); |
| 412 | } |
| 413 | |
| 414 | static void pnv_phb3_lsi_src_id_write(PnvPHB3 *phb, uint64_t val) |
| 415 | { |
| 416 | /* Sanitize content */ |
| 417 | val &= PHB_LSI_SRC_ID; |
| 418 | phb->regs[PHB_LSI_SOURCE_ID >> 3] = val; |
| 419 | pnv_phb3_remap_irqs(phb); |
| 420 | } |
| 421 | |
| 422 | static void pnv_phb3_rtc_invalidate(PnvPHB3 *phb, uint64_t val) |
| 423 | { |
| 424 | PnvPhb3DMASpace *ds; |
| 425 | |
| 426 | /* Always invalidate all for now ... */ |
| 427 | QLIST_FOREACH(ds, &phb->dma_spaces, list) { |
| 428 | ds->pe_num = PHB_INVALID_PE; |
| 429 | } |
| 430 | } |
| 431 | |
| 432 | |
| 433 | static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds) |
| 434 | { |
| 435 | uint64_t cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3]; |
| 436 | |
| 437 | if (cfg & PHB_PHB3C_32BIT_MSI_EN) { |
| 438 | if (!memory_region_is_mapped(&ds->msi32_mr)) { |
| 439 | memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), |
| 440 | 0xffff0000, &ds->msi32_mr); |
| 441 | } |
| 442 | } else { |
| 443 | if (memory_region_is_mapped(&ds->msi32_mr)) { |
| 444 | memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), |
| 445 | &ds->msi32_mr); |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | if (cfg & PHB_PHB3C_64BIT_MSI_EN) { |
| 450 | if (!memory_region_is_mapped(&ds->msi64_mr)) { |
| 451 | memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), |
| 452 | (1ull << 60), &ds->msi64_mr); |
| 453 | } |
| 454 | } else { |
| 455 | if (memory_region_is_mapped(&ds->msi64_mr)) { |
| 456 | memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), |
| 457 | &ds->msi64_mr); |
| 458 | } |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb) |
| 463 | { |
| 464 | PnvPhb3DMASpace *ds; |
| 465 | |
| 466 | QLIST_FOREACH(ds, &phb->dma_spaces, list) { |
| 467 | pnv_phb3_update_msi_regions(ds); |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) |
| 472 | { |
| 473 | PnvPHB3 *phb = opaque; |
| 474 | bool changed; |
| 475 | |
| 476 | /* Special case configuration data */ |
| 477 | if ((off & 0xfffc) == PHB_CONFIG_DATA) { |
| 478 | if (size > 4) { |
| 479 | phb3_error(phb, "Invalid config access, offset: 0x%"PRIx64" size: %d", |
| 480 | off, size); |
| 481 | return; |
| 482 | } |
| 483 | pnv_phb3_config_write(phb, off & 0x3, size, val); |
| 484 | return; |
| 485 | } |
| 486 | |
| 487 | /* Other registers are 64-bit only */ |
| 488 | if (size != 8 || off & 0x7) { |
| 489 | phb3_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d", |
| 490 | off, size); |
| 491 | return; |
| 492 | } |
| 493 | |
| 494 | /* Handle masking & filtering */ |
| 495 | switch (off) { |
| 496 | case PHB_M64_UPPER_BITS: |
| 497 | val &= 0xfffc000000000000ull; |
| 498 | break; |
| 499 | case PHB_Q_DMA_R: |
| 500 | /* |
| 501 | * This is enough logic to make SW happy but we aren't actually |
| 502 | * quiescing the DMAs |
| 503 | */ |
| 504 | if (val & PHB_Q_DMA_R_AUTORESET) { |
| 505 | val = 0; |
| 506 | } else { |
| 507 | val &= PHB_Q_DMA_R_QUIESCE_DMA; |
| 508 | } |
| 509 | break; |
| 510 | /* LEM stuff */ |
| 511 | case PHB_LEM_FIR_AND_MASK: |
| 512 | phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val; |
| 513 | return; |
| 514 | case PHB_LEM_FIR_OR_MASK: |
| 515 | phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val; |
| 516 | return; |
| 517 | case PHB_LEM_ERROR_AND_MASK: |
| 518 | phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val; |
| 519 | return; |
| 520 | case PHB_LEM_ERROR_OR_MASK: |
| 521 | phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val; |
| 522 | return; |
| 523 | case PHB_LEM_WOF: |
| 524 | val = 0; |
| 525 | break; |
| 526 | } |
| 527 | |
| 528 | /* Record whether it changed */ |
| 529 | changed = phb->regs[off >> 3] != val; |
| 530 | |
| 531 | /* Store in register cache first */ |
| 532 | phb->regs[off >> 3] = val; |
| 533 | |
| 534 | /* Handle side effects */ |
| 535 | switch (off) { |
| 536 | case PHB_PHB3_CONFIG: |
| 537 | if (changed) { |
| 538 | pnv_phb3_update_all_msi_regions(phb); |
| 539 | } |
| 540 | /* fall through */ |
| 541 | case PHB_M32_BASE_ADDR: |
| 542 | case PHB_M32_BASE_MASK: |
| 543 | case PHB_M32_START_ADDR: |
| 544 | if (changed) { |
| 545 | pnv_phb3_check_m32(phb); |
| 546 | } |
| 547 | break; |
| 548 | case PHB_M64_UPPER_BITS: |
| 549 | if (changed) { |
| 550 | pnv_phb3_check_all_m64s(phb); |
| 551 | } |
| 552 | break; |
| 553 | case PHB_LSI_SOURCE_ID: |
| 554 | if (changed) { |
| 555 | pnv_phb3_lsi_src_id_write(phb, val); |
| 556 | } |
| 557 | break; |
| 558 | |
| 559 | /* IODA table accesses */ |
| 560 | case PHB_IODA_DATA0: |
| 561 | pnv_phb3_ioda_write(phb, val); |
| 562 | break; |
| 563 | |
| 564 | /* RTC invalidation */ |
| 565 | case PHB_RTC_INVALIDATE: |
| 566 | pnv_phb3_rtc_invalidate(phb, val); |
| 567 | break; |
| 568 | |
| 569 | /* FFI request */ |
| 570 | case PHB_FFI_REQUEST: |
| 571 | pnv_phb3_msi_ffi(&phb->msis, val); |
| 572 | break; |
| 573 | |
| 574 | /* Silent simple writes */ |
| 575 | case PHB_CONFIG_ADDRESS: |
| 576 | case PHB_IODA_ADDR: |
| 577 | case PHB_TCE_KILL: |
| 578 | case PHB_TCE_SPEC_CTL: |
| 579 | case PHB_PEST_BAR: |
| 580 | case PHB_PELTV_BAR: |
| 581 | case PHB_RTT_BAR: |
| 582 | case PHB_RBA_BAR: |
| 583 | case PHB_IVT_BAR: |
| 584 | case PHB_FFI_LOCK: |
| 585 | case PHB_LEM_FIR_ACCUM: |
| 586 | case PHB_LEM_ERROR_MASK: |
| 587 | case PHB_LEM_ACTION0: |
| 588 | case PHB_LEM_ACTION1: |
| 589 | break; |
| 590 | |
| 591 | /* Noise on anything else */ |
| 592 | default: |
| 593 | qemu_log_mask(LOG_UNIMP, "phb3: reg_write 0x%"PRIx64"=%"PRIx64"\n", |
| 594 | off, val); |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size) |
| 599 | { |
| 600 | PnvPHB3 *phb = opaque; |
| 601 | PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); |
| 602 | uint64_t val; |
| 603 | |
| 604 | if ((off & 0xfffc) == PHB_CONFIG_DATA) { |
| 605 | if (size > 4) { |
| 606 | phb3_error(phb, "Invalid config access, offset: 0x%"PRIx64" size: %d", |
| 607 | off, size); |
| 608 | return ~0ull; |
| 609 | } |
| 610 | return pnv_phb3_config_read(phb, off & 0x3, size); |
| 611 | } |
| 612 | |
| 613 | /* Other registers are 64-bit only */ |
| 614 | if (size != 8 || off & 0x7) { |
| 615 | phb3_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d", |
| 616 | off, size); |
| 617 | return ~0ull; |
| 618 | } |
| 619 | |
| 620 | /* Default read from cache */ |
| 621 | val = phb->regs[off >> 3]; |
| 622 | |
| 623 | switch (off) { |
| 624 | /* Simulate venice DD2.0 */ |
| 625 | case PHB_VERSION: |
| 626 | return 0x000000a300000005ull; |
| 627 | case PHB_PCIE_SYSTEM_CONFIG: |
| 628 | return 0x441100fc30000000; |
| 629 | |
| 630 | /* IODA table accesses */ |
| 631 | case PHB_IODA_DATA0: |
| 632 | return pnv_phb3_ioda_read(phb); |
| 633 | |
| 634 | /* Link training always appears trained */ |
| 635 | case PHB_PCIE_DLP_TRAIN_CTL: |
| 636 | if (!pci_find_device(pci->bus, 1, 0)) { |
| 637 | return 0; |
| 638 | } |
| 639 | return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TC_DL_LINKACT; |
| 640 | |
| 641 | /* FFI Lock */ |
| 642 | case PHB_FFI_LOCK: |
| 643 | /* Set lock and return previous value */ |
| 644 | phb->regs[off >> 3] |= PHB_FFI_LOCK_STATE; |
| 645 | return val; |
| 646 | |
| 647 | /* DMA read sync: make it look like it's complete */ |
| 648 | case PHB_DMARD_SYNC: |
| 649 | return PHB_DMARD_SYNC_COMPLETE; |
| 650 | |
| 651 | /* Silent simple reads */ |
| 652 | case PHB_PHB3_CONFIG: |
| 653 | case PHB_M32_BASE_ADDR: |
| 654 | case PHB_M32_BASE_MASK: |
| 655 | case PHB_M32_START_ADDR: |
| 656 | case PHB_CONFIG_ADDRESS: |
| 657 | case PHB_IODA_ADDR: |
| 658 | case PHB_RTC_INVALIDATE: |
| 659 | case PHB_TCE_KILL: |
| 660 | case PHB_TCE_SPEC_CTL: |
| 661 | case PHB_PEST_BAR: |
| 662 | case PHB_PELTV_BAR: |
| 663 | case PHB_RTT_BAR: |
| 664 | case PHB_RBA_BAR: |
| 665 | case PHB_IVT_BAR: |
| 666 | case PHB_M64_UPPER_BITS: |
| 667 | case PHB_LEM_FIR_ACCUM: |
| 668 | case PHB_LEM_ERROR_MASK: |
| 669 | case PHB_LEM_ACTION0: |
| 670 | case PHB_LEM_ACTION1: |
| 671 | break; |
| 672 | |
| 673 | /* Noise on anything else */ |
| 674 | default: |
| 675 | qemu_log_mask(LOG_UNIMP, "phb3: reg_read 0x%"PRIx64"=%"PRIx64"\n", |
| 676 | off, val); |
| 677 | } |
| 678 | return val; |
| 679 | } |
| 680 | |
| 681 | static const MemoryRegionOps pnv_phb3_reg_ops = { |
| 682 | .read = pnv_phb3_reg_read, |
| 683 | .write = pnv_phb3_reg_write, |
| 684 | .valid.min_access_size = 1, |
| 685 | .valid.max_access_size = 8, |
| 686 | .impl.min_access_size = 1, |
| 687 | .impl.max_access_size = 8, |
| 688 | .endianness = DEVICE_BIG_ENDIAN, |
| 689 | }; |
| 690 | |
| 691 | static int pnv_phb3_map_irq(PCIDevice *pci_dev, int irq_num) |
| 692 | { |
| 693 | /* Check that out properly ... */ |
| 694 | return irq_num & 3; |
| 695 | } |
| 696 | |
| 697 | static void pnv_phb3_set_irq(void *opaque, int irq_num, int level) |
| 698 | { |
| 699 | PnvPHB3 *phb = opaque; |
| 700 | |
| 701 | /* LSI only ... */ |
| 702 | if (irq_num > 3) { |
| 703 | phb3_error(phb, "Unknown IRQ to set %d", irq_num); |
| 704 | } |
| 705 | qemu_set_irq(phb->qirqs[irq_num], level); |
| 706 | } |
| 707 | |
| 708 | static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds) |
| 709 | { |
| 710 | uint64_t rtt, addr; |
| 711 | uint16_t rte; |
| 712 | int bus_num; |
| 713 | |
| 714 | /* Already resolved ? */ |
| 715 | if (ds->pe_num != PHB_INVALID_PE) { |
| 716 | return true; |
| 717 | } |
| 718 | |
| 719 | /* We need to lookup the RTT */ |
| 720 | rtt = ds->phb->regs[PHB_RTT_BAR >> 3]; |
| 721 | if (!(rtt & PHB_RTT_BAR_ENABLE)) { |
| 722 | phb3_error(ds->phb, "DMA with RTT BAR disabled !"); |
| 723 | /* Set error bits ? fence ? ... */ |
| 724 | return false; |
| 725 | } |
| 726 | |
| 727 | /* Read RTE */ |
| 728 | bus_num = pci_bus_num(ds->bus); |
| 729 | addr = rtt & PHB_RTT_BASE_ADDRESS_MASK; |
| 730 | addr += 2 * ((bus_num << 8) | ds->devfn); |
| 731 | if (dma_memory_read(&address_space_memory, addr, &rte, |
| 732 | sizeof(rte), MEMTXATTRS_UNSPECIFIED)) { |
| 733 | phb3_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); |
| 734 | /* Set error bits ? fence ? ... */ |
| 735 | return false; |
| 736 | } |
| 737 | rte = be16_to_cpu(rte); |
| 738 | |
| 739 | /* Fail upon reading of invalid PE# */ |
| 740 | if (rte >= PNV_PHB3_NUM_PE) { |
| 741 | phb3_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte); |
| 742 | /* Set error bits ? fence ? ... */ |
| 743 | return false; |
| 744 | } |
| 745 | ds->pe_num = rte; |
| 746 | return true; |
| 747 | } |
| 748 | |
| 749 | static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr, |
| 750 | bool is_write, uint64_t tve, |
| 751 | IOMMUTLBEntry *tlb) |
| 752 | { |
| 753 | uint64_t tta = GETFIELD(IODA2_TVT_TABLE_ADDR, tve); |
| 754 | int32_t lev = GETFIELD(IODA2_TVT_NUM_LEVELS, tve); |
| 755 | uint32_t tts = GETFIELD(IODA2_TVT_TCE_TABLE_SIZE, tve); |
| 756 | uint32_t tps = GETFIELD(IODA2_TVT_IO_PSIZE, tve); |
| 757 | PnvPHB3 *phb = ds->phb; |
| 758 | |
| 759 | /* Invalid levels */ |
| 760 | if (lev > 4) { |
| 761 | phb3_error(phb, "Invalid #levels in TVE %d", lev); |
| 762 | return; |
| 763 | } |
| 764 | |
| 765 | /* IO Page Size of 0 means untranslated, else use TCEs */ |
| 766 | if (tps == 0) { |
| 767 | /* |
| 768 | * We only support non-translate in top window. |
| 769 | * |
| 770 | * TODO: Venice/Murano support it on bottom window above 4G and |
| 771 | * Naples supports it on everything |
| 772 | */ |
| 773 | if (!(tve & PPC_BIT(51))) { |
| 774 | phb3_error(phb, "xlate for invalid non-translate TVE"); |
| 775 | return; |
| 776 | } |
| 777 | /* TODO: Handle boundaries */ |
| 778 | |
| 779 | /* Use 4k pages like q35 ... for now */ |
| 780 | tlb->iova = addr & 0xfffffffffffff000ull; |
| 781 | tlb->translated_addr = addr & 0x0003fffffffff000ull; |
| 782 | tlb->addr_mask = 0xfffull; |
| 783 | tlb->perm = IOMMU_RW; |
| 784 | } else { |
| 785 | uint32_t tce_shift, tbl_shift, sh; |
| 786 | uint64_t base, taddr, tce, tce_mask; |
| 787 | |
| 788 | /* TVE disabled ? */ |
| 789 | if (tts == 0) { |
| 790 | phb3_error(phb, "xlate for invalid translated TVE"); |
| 791 | return; |
| 792 | } |
| 793 | |
| 794 | /* Address bits per bottom level TCE entry */ |
| 795 | tce_shift = tps + 11; |
| 796 | |
| 797 | /* Address bits per table level */ |
| 798 | tbl_shift = tts + 8; |
| 799 | |
| 800 | /* Top level table base address */ |
| 801 | base = tta << 12; |
| 802 | |
| 803 | /* Total shift to first level */ |
| 804 | sh = tbl_shift * lev + tce_shift; |
| 805 | |
| 806 | /* TODO: Multi-level untested */ |
| 807 | do { |
| 808 | lev--; |
| 809 | |
| 810 | /* Grab the TCE address */ |
| 811 | taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); |
| 812 | if (dma_memory_read(&address_space_memory, taddr, &tce, |
| 813 | sizeof(tce), MEMTXATTRS_UNSPECIFIED)) { |
| 814 | phb3_error(phb, "Failed to read TCE at 0x%"PRIx64, taddr); |
| 815 | return; |
| 816 | } |
| 817 | tce = be64_to_cpu(tce); |
| 818 | |
| 819 | /* Check permission for indirect TCE */ |
| 820 | if ((lev >= 0) && !(tce & 3)) { |
| 821 | phb3_error(phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); |
| 822 | phb3_error(phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, |
| 823 | is_write ? 'W' : 'R', tve); |
| 824 | phb3_error(phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", |
| 825 | tta, lev, tts, tps); |
| 826 | return; |
| 827 | } |
| 828 | sh -= tbl_shift; |
| 829 | base = tce & ~0xfffull; |
| 830 | } while (lev >= 0); |
| 831 | |
| 832 | /* We exit the loop with TCE being the final TCE */ |
| 833 | if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { |
| 834 | phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr); |
| 835 | phb3_error(phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, |
| 836 | is_write ? 'W' : 'R', tve); |
| 837 | phb3_error(phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", |
| 838 | tta, lev, tts, tps); |
| 839 | return; |
| 840 | } |
| 841 | tce_mask = ~((1ull << tce_shift) - 1); |
| 842 | tlb->iova = addr & tce_mask; |
| 843 | tlb->translated_addr = tce & tce_mask; |
| 844 | tlb->addr_mask = ~tce_mask; |
| 845 | tlb->perm = tce & 3; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | static IOMMUTLBEntry pnv_phb3_translate_iommu(IOMMUMemoryRegion *iommu, |
| 850 | hwaddr addr, |
| 851 | IOMMUAccessFlags flag, |
| 852 | int iommu_idx) |
| 853 | { |
| 854 | PnvPhb3DMASpace *ds = container_of(iommu, PnvPhb3DMASpace, dma_mr); |
| 855 | int tve_sel; |
| 856 | uint64_t tve, cfg; |
| 857 | IOMMUTLBEntry ret = { |
| 858 | .target_as = &address_space_memory, |
| 859 | .iova = addr, |
| 860 | .translated_addr = 0, |
| 861 | .addr_mask = ~(hwaddr)0, |
| 862 | .perm = IOMMU_NONE, |
| 863 | }; |
| 864 | PnvPHB3 *phb = ds->phb; |
| 865 | |
| 866 | /* Resolve PE# */ |
| 867 | if (!pnv_phb3_resolve_pe(ds)) { |
| 868 | phb3_error(phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", |
| 869 | ds->bus, pci_bus_num(ds->bus), ds->devfn); |
| 870 | return ret; |
| 871 | } |
| 872 | |
| 873 | /* Check top bits */ |
| 874 | switch (addr >> 60) { |
| 875 | case 00: |
| 876 | /* DMA or 32-bit MSI ? */ |
| 877 | cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3]; |
| 878 | if ((cfg & PHB_PHB3C_32BIT_MSI_EN) && |
| 879 | ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) { |
| 880 | phb3_error(phb, "xlate on 32-bit MSI region"); |
| 881 | return ret; |
| 882 | } |
| 883 | /* Choose TVE XXX Use PHB3 Control Register */ |
| 884 | tve_sel = (addr >> 59) & 1; |
| 885 | tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel]; |
| 886 | pnv_phb3_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret); |
| 887 | break; |
| 888 | case 01: |
| 889 | phb3_error(phb, "xlate on 64-bit MSI region"); |
| 890 | break; |
| 891 | default: |
| 892 | phb3_error(phb, "xlate on unsupported address 0x%"PRIx64, addr); |
| 893 | } |
| 894 | return ret; |
| 895 | } |
| 896 | |
| 897 | #define TYPE_PNV_PHB3_IOMMU_MEMORY_REGION "pnv-phb3-iommu-memory-region" |
| 898 | DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB3_IOMMU_MEMORY_REGION, |
| 899 | TYPE_PNV_PHB3_IOMMU_MEMORY_REGION) |
| 900 | |
| 901 | static void pnv_phb3_iommu_memory_region_class_init(ObjectClass *klass, |
| 902 | const void *data) |
| 903 | { |
| 904 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); |
| 905 | |
| 906 | imrc->translate = pnv_phb3_translate_iommu; |
| 907 | } |
| 908 | |
| 909 | static const TypeInfo pnv_phb3_iommu_memory_region_info = { |
| 910 | .parent = TYPE_IOMMU_MEMORY_REGION, |
| 911 | .name = TYPE_PNV_PHB3_IOMMU_MEMORY_REGION, |
| 912 | .class_init = pnv_phb3_iommu_memory_region_class_init, |
| 913 | }; |
| 914 | |
| 915 | /* |
| 916 | * MSI/MSIX memory region implementation. |
| 917 | * The handler handles both MSI and MSIX. |
| 918 | */ |
| 919 | static void pnv_phb3_msi_write(void *opaque, hwaddr addr, |
| 920 | uint64_t data, unsigned size) |
| 921 | { |
| 922 | PnvPhb3DMASpace *ds = opaque; |
| 923 | |
| 924 | /* Resolve PE# */ |
| 925 | if (!pnv_phb3_resolve_pe(ds)) { |
| 926 | phb3_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", |
| 927 | ds->bus, pci_bus_num(ds->bus), ds->devfn); |
| 928 | return; |
| 929 | } |
| 930 | |
| 931 | pnv_phb3_msi_send(&ds->phb->msis, addr, data, ds->pe_num); |
| 932 | } |
| 933 | |
| 934 | /* There is no .read as the read result is undefined by PCI spec */ |
| 935 | static uint64_t pnv_phb3_msi_read(void *opaque, hwaddr addr, unsigned size) |
| 936 | { |
| 937 | PnvPhb3DMASpace *ds = opaque; |
| 938 | |
| 939 | phb3_error(ds->phb, "invalid read @ 0x%" HWADDR_PRIx, addr); |
| 940 | return -1; |
| 941 | } |
| 942 | |
| 943 | static const MemoryRegionOps pnv_phb3_msi_ops = { |
| 944 | .read = pnv_phb3_msi_read, |
| 945 | .write = pnv_phb3_msi_write, |
| 946 | .endianness = DEVICE_LITTLE_ENDIAN |
| 947 | }; |
| 948 | |
| 949 | static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
| 950 | { |
| 951 | PnvPHB3 *phb = opaque; |
| 952 | PnvPhb3DMASpace *ds; |
| 953 | |
| 954 | QLIST_FOREACH(ds, &phb->dma_spaces, list) { |
| 955 | if (ds->bus == bus && ds->devfn == devfn) { |
| 956 | break; |
| 957 | } |
| 958 | } |
| 959 | |
| 960 | if (ds == NULL) { |
| 961 | ds = g_new0(PnvPhb3DMASpace, 1); |
| 962 | ds->bus = bus; |
| 963 | ds->devfn = devfn; |
| 964 | ds->pe_num = PHB_INVALID_PE; |
| 965 | ds->phb = phb; |
| 966 | memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr), |
| 967 | TYPE_PNV_PHB3_IOMMU_MEMORY_REGION, |
| 968 | OBJECT(phb), "phb3_iommu", UINT64_MAX); |
| 969 | address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr), |
| 970 | "phb3_iommu"); |
| 971 | memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb3_msi_ops, |
| 972 | ds, "msi32", 0x10000); |
| 973 | memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb3_msi_ops, |
| 974 | ds, "msi64", 0x100000); |
| 975 | pnv_phb3_update_msi_regions(ds); |
| 976 | |
| 977 | QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list); |
| 978 | } |
| 979 | return &ds->dma_as; |
| 980 | } |
| 981 | |
| 982 | static PCIIOMMUOps pnv_phb3_iommu_ops = { |
| 983 | .get_address_space = pnv_phb3_dma_iommu, |
| 984 | }; |
| 985 | |
| 986 | static void pnv_phb3_instance_init(Object *obj) |
| 987 | { |
| 988 | PnvPHB3 *phb = PNV_PHB3(obj); |
| 989 | |
| 990 | QLIST_INIT(&phb->dma_spaces); |
| 991 | |
| 992 | /* LSI sources */ |
| 993 | object_initialize_child(obj, "lsi", &phb->lsis, TYPE_ICS); |
| 994 | |
| 995 | /* Default init ... will be fixed by HW inits */ |
| 996 | phb->lsis.offset = 0; |
| 997 | |
| 998 | /* MSI sources */ |
| 999 | object_initialize_child(obj, "msi", &phb->msis, TYPE_PHB3_MSI); |
| 1000 | |
| 1001 | /* Power Bus Common Queue */ |
| 1002 | object_initialize_child(obj, "pbcq", &phb->pbcq, TYPE_PNV_PBCQ); |
| 1003 | |
| 1004 | } |
| 1005 | |
| 1006 | void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb) |
| 1007 | { |
| 1008 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
| 1009 | |
| 1010 | /* |
| 1011 | * PHB3 doesn't support IO space. However, qemu gets very upset if |
| 1012 | * we don't have an IO region to anchor IO BARs onto so we just |
| 1013 | * initialize one which we never hook up to anything |
| 1014 | */ |
| 1015 | memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000); |
| 1016 | memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio", |
| 1017 | PCI_MMIO_TOTAL_SIZE); |
| 1018 | |
| 1019 | pci->bus = pci_register_root_bus(dev, |
| 1020 | dev->id ? dev->id : NULL, |
| 1021 | pnv_phb3_set_irq, pnv_phb3_map_irq, phb, |
| 1022 | &phb->pci_mmio, &phb->pci_io, |
| 1023 | 0, 4, TYPE_PNV_PHB3_ROOT_BUS); |
| 1024 | |
| 1025 | object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id, |
| 1026 | &error_abort); |
| 1027 | object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id, |
| 1028 | &error_abort); |
| 1029 | |
| 1030 | pci_setup_iommu(pci->bus, &pnv_phb3_iommu_ops, phb); |
| 1031 | } |
| 1032 | |
| 1033 | static void pnv_phb3_realize(DeviceState *dev, Error **errp) |
| 1034 | { |
| 1035 | PnvPHB3 *phb = PNV_PHB3(dev); |
| 1036 | PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); |
| 1037 | int i; |
| 1038 | |
| 1039 | if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { |
| 1040 | error_setg(errp, "invalid PHB index: %d", phb->phb_id); |
| 1041 | return; |
| 1042 | } |
| 1043 | |
| 1044 | /* LSI sources */ |
| 1045 | object_property_set_link(OBJECT(&phb->lsis), "xics", OBJECT(pnv), |
| 1046 | &error_abort); |
| 1047 | object_property_set_int(OBJECT(&phb->lsis), "nr-irqs", PNV_PHB3_NUM_LSI, |
| 1048 | &error_abort); |
| 1049 | if (!qdev_realize(DEVICE(&phb->lsis), NULL, errp)) { |
| 1050 | return; |
| 1051 | } |
| 1052 | |
| 1053 | for (i = 0; i < phb->lsis.nr_irqs; i++) { |
| 1054 | ics_set_irq_type(&phb->lsis, i, true); |
| 1055 | } |
| 1056 | |
| 1057 | phb->qirqs = qemu_allocate_irqs(ics_set_irq, &phb->lsis, phb->lsis.nr_irqs); |
| 1058 | |
| 1059 | /* MSI sources */ |
| 1060 | object_property_set_link(OBJECT(&phb->msis), "phb", OBJECT(phb), |
| 1061 | &error_abort); |
| 1062 | object_property_set_link(OBJECT(&phb->msis), "xics", OBJECT(pnv), |
| 1063 | &error_abort); |
| 1064 | object_property_set_int(OBJECT(&phb->msis), "nr-irqs", PHB3_MAX_MSI, |
| 1065 | &error_abort); |
| 1066 | if (!qdev_realize(DEVICE(&phb->msis), NULL, errp)) { |
| 1067 | return; |
| 1068 | } |
| 1069 | |
| 1070 | /* Power Bus Common Queue */ |
| 1071 | object_property_set_link(OBJECT(&phb->pbcq), "phb", OBJECT(phb), |
| 1072 | &error_abort); |
| 1073 | if (!qdev_realize(DEVICE(&phb->pbcq), NULL, errp)) { |
| 1074 | return; |
| 1075 | } |
| 1076 | |
| 1077 | /* Controller Registers */ |
| 1078 | memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb, |
| 1079 | "phb3-regs", 0x1000); |
| 1080 | } |
| 1081 | |
| 1082 | void pnv_phb3_update_regions(PnvPHB3 *phb) |
| 1083 | { |
| 1084 | PnvPBCQState *pbcq = &phb->pbcq; |
| 1085 | |
| 1086 | /* Unmap first always */ |
| 1087 | if (memory_region_is_mapped(&phb->mr_regs)) { |
| 1088 | memory_region_del_subregion(&pbcq->phbbar, &phb->mr_regs); |
| 1089 | } |
| 1090 | |
| 1091 | /* Map registers if enabled */ |
| 1092 | if (memory_region_is_mapped(&pbcq->phbbar)) { |
| 1093 | /* TODO: We should use the PHB BAR 2 register but we don't ... */ |
| 1094 | memory_region_add_subregion(&pbcq->phbbar, 0, &phb->mr_regs); |
| 1095 | } |
| 1096 | |
| 1097 | /* Check/update m32 */ |
| 1098 | if (memory_region_is_mapped(&phb->mr_m32)) { |
| 1099 | pnv_phb3_check_m32(phb); |
| 1100 | } |
| 1101 | pnv_phb3_check_all_m64s(phb); |
| 1102 | } |
| 1103 | |
| 1104 | static const Property pnv_phb3_properties[] = { |
| 1105 | DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), |
| 1106 | DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), |
| 1107 | DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), |
| 1108 | DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *), |
| 1109 | }; |
| 1110 | |
| 1111 | static void pnv_phb3_class_init(ObjectClass *klass, const void *data) |
| 1112 | { |
| 1113 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1114 | |
| 1115 | dc->realize = pnv_phb3_realize; |
| 1116 | device_class_set_props(dc, pnv_phb3_properties); |
| 1117 | dc->user_creatable = false; |
| 1118 | } |
| 1119 | |
| 1120 | static const TypeInfo pnv_phb3_type_info = { |
| 1121 | .name = TYPE_PNV_PHB3, |
| 1122 | .parent = TYPE_DEVICE, |
| 1123 | .instance_size = sizeof(PnvPHB3), |
| 1124 | .class_init = pnv_phb3_class_init, |
| 1125 | .instance_init = pnv_phb3_instance_init, |
| 1126 | }; |
| 1127 | |
| 1128 | static void pnv_phb3_root_bus_get_prop(Object *obj, Visitor *v, |
| 1129 | const char *name, |
| 1130 | void *opaque, Error **errp) |
| 1131 | { |
| 1132 | PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj); |
| 1133 | uint64_t value = 0; |
| 1134 | |
| 1135 | if (strcmp(name, "phb-id") == 0) { |
| 1136 | value = bus->phb_id; |
| 1137 | } else { |
| 1138 | value = bus->chip_id; |
| 1139 | } |
| 1140 | |
| 1141 | visit_type_size(v, name, &value, errp); |
| 1142 | } |
| 1143 | |
| 1144 | static void pnv_phb3_root_bus_set_prop(Object *obj, Visitor *v, |
| 1145 | const char *name, |
| 1146 | void *opaque, Error **errp) |
| 1147 | |
| 1148 | { |
| 1149 | PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj); |
| 1150 | uint64_t value; |
| 1151 | |
| 1152 | if (!visit_type_size(v, name, &value, errp)) { |
| 1153 | return; |
| 1154 | } |
| 1155 | |
| 1156 | if (strcmp(name, "phb-id") == 0) { |
| 1157 | bus->phb_id = value; |
| 1158 | } else { |
| 1159 | bus->chip_id = value; |
| 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | static void pnv_phb3_root_bus_class_init(ObjectClass *klass, const void *data) |
| 1164 | { |
| 1165 | BusClass *k = BUS_CLASS(klass); |
| 1166 | |
| 1167 | object_class_property_add(klass, "phb-id", "int", |
| 1168 | pnv_phb3_root_bus_get_prop, |
| 1169 | pnv_phb3_root_bus_set_prop, |
| 1170 | NULL, NULL); |
| 1171 | |
| 1172 | object_class_property_add(klass, "chip-id", "int", |
| 1173 | pnv_phb3_root_bus_get_prop, |
| 1174 | pnv_phb3_root_bus_set_prop, |
| 1175 | NULL, NULL); |
| 1176 | |
| 1177 | /* |
| 1178 | * PHB3 has only a single root complex. Enforce the limit on the |
| 1179 | * parent bus |
| 1180 | */ |
| 1181 | k->max_dev = 1; |
| 1182 | } |
| 1183 | |
| 1184 | static const TypeInfo pnv_phb3_root_bus_info = { |
| 1185 | .name = TYPE_PNV_PHB3_ROOT_BUS, |
| 1186 | .parent = TYPE_PCIE_BUS, |
| 1187 | .instance_size = sizeof(PnvPHB3RootBus), |
| 1188 | .class_init = pnv_phb3_root_bus_class_init, |
| 1189 | }; |
| 1190 | |
| 1191 | static void pnv_phb3_register_types(void) |
| 1192 | { |
| 1193 | type_register_static(&pnv_phb3_root_bus_info); |
| 1194 | type_register_static(&pnv_phb3_type_info); |
| 1195 | type_register_static(&pnv_phb3_iommu_memory_region_info); |
| 1196 | } |
| 1197 | |
| 1198 | type_init(pnv_phb3_register_types) |