| 1 | /* |
| 2 | * QEMU PowerPC PowerNV (POWER9) PHB4 model |
| 3 | * |
| 4 | * Copyright (c) 2018-2020, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "qapi/error.h" |
| 11 | #include "qemu/log.h" |
| 12 | #include "target/ppc/cpu.h" |
| 13 | #include "hw/ppc/fdt.h" |
| 14 | #include "hw/pci-host/pnv_phb4_regs.h" |
| 15 | #include "hw/pci-host/pnv_phb4.h" |
| 16 | #include "hw/ppc/pnv_xscom.h" |
| 17 | #include "hw/pci/pci_bridge.h" |
| 18 | #include "hw/pci/pci_bus.h" |
| 19 | #include "hw/ppc/pnv.h" |
| 20 | #include "hw/ppc/pnv_chip.h" |
| 21 | #include "hw/core/qdev-properties.h" |
| 22 | #include "system/system.h" |
| 23 | |
| 24 | #include <libfdt.h> |
| 25 | |
| 26 | #define phb_pec_error(pec, fmt, ...) \ |
| 27 | qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ |
| 28 | (pec)->chip_id, (pec)->index, ## __VA_ARGS__) |
| 29 | |
| 30 | |
| 31 | static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr, |
| 32 | unsigned size) |
| 33 | { |
| 34 | PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); |
| 35 | uint32_t reg = addr >> 3; |
| 36 | |
| 37 | /* All registers are readable */ |
| 38 | return pec->nest_regs[reg]; |
| 39 | } |
| 40 | |
| 41 | static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr, |
| 42 | uint64_t val, unsigned size) |
| 43 | { |
| 44 | PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); |
| 45 | uint32_t reg = addr >> 3; |
| 46 | |
| 47 | switch (reg) { |
| 48 | case PEC_NEST_DROP_PRIO_CTRL: |
| 49 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 25); |
| 50 | break; |
| 51 | case PEC_NEST_PBCQ_ERR_INJECT: |
| 52 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 11); |
| 53 | break; |
| 54 | case PEC_NEST_PCI_NEST_CLK_TRACE_CTL: |
| 55 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 16); |
| 56 | break; |
| 57 | case PEC_NEST_PBCQ_PMON_CTRL: |
| 58 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 37); |
| 59 | break; |
| 60 | case PEC_NEST_PBCQ_PBUS_ADDR_EXT: |
| 61 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 6); |
| 62 | break; |
| 63 | case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT: |
| 64 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 15); |
| 65 | break; |
| 66 | case PEC_NEST_PBCQ_READ_STK_OVR: |
| 67 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 48); |
| 68 | break; |
| 69 | case PEC_NEST_PBCQ_WRITE_STK_OVR: |
| 70 | case PEC_NEST_PBCQ_STORE_STK_OVR: |
| 71 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 24); |
| 72 | break; |
| 73 | case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL: |
| 74 | pec->nest_regs[reg] = val & PPC_BITMASK(0, 41); |
| 75 | break; |
| 76 | case PEC_NEST_PBCQ_HW_CONFIG: |
| 77 | case PEC_NEST_CAPP_CTRL: |
| 78 | pec->nest_regs[reg] = val; |
| 79 | break; |
| 80 | default: |
| 81 | phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, |
| 82 | addr, val); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | static const MemoryRegionOps pnv_pec_nest_xscom_ops = { |
| 87 | .read = pnv_pec_nest_xscom_read, |
| 88 | .write = pnv_pec_nest_xscom_write, |
| 89 | .valid.min_access_size = 8, |
| 90 | .valid.max_access_size = 8, |
| 91 | .impl.min_access_size = 8, |
| 92 | .impl.max_access_size = 8, |
| 93 | .endianness = DEVICE_BIG_ENDIAN, |
| 94 | }; |
| 95 | |
| 96 | static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr, |
| 97 | unsigned size) |
| 98 | { |
| 99 | PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); |
| 100 | uint32_t reg = addr >> 3; |
| 101 | |
| 102 | /* All registers are readable */ |
| 103 | return pec->pci_regs[reg]; |
| 104 | } |
| 105 | |
| 106 | static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr, |
| 107 | uint64_t val, unsigned size) |
| 108 | { |
| 109 | PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); |
| 110 | uint32_t reg = addr >> 3; |
| 111 | |
| 112 | switch (reg) { |
| 113 | case PEC_PCI_PBAIB_HW_CONFIG: |
| 114 | pec->pci_regs[reg] = val & PPC_BITMASK(0, 42); |
| 115 | break; |
| 116 | case PEC_PCI_PBAIB_HW_OVR: |
| 117 | pec->pci_regs[reg] = val & PPC_BITMASK(0, 15); |
| 118 | break; |
| 119 | case PEC_PCI_PBAIB_READ_STK_OVR: |
| 120 | pec->pci_regs[reg] = val & PPC_BITMASK(0, 48); |
| 121 | break; |
| 122 | default: |
| 123 | phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, |
| 124 | addr, val); |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | static const MemoryRegionOps pnv_pec_pci_xscom_ops = { |
| 129 | .read = pnv_pec_pci_xscom_read, |
| 130 | .write = pnv_pec_pci_xscom_write, |
| 131 | .valid.min_access_size = 8, |
| 132 | .valid.max_access_size = 8, |
| 133 | .impl.min_access_size = 8, |
| 134 | .impl.max_access_size = 8, |
| 135 | .endianness = DEVICE_BIG_ENDIAN, |
| 136 | }; |
| 137 | |
| 138 | PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) |
| 139 | { |
| 140 | PnvPhb4PecState *pecs = NULL; |
| 141 | int chip_id = phb->chip_id; |
| 142 | int index = phb->phb_id; |
| 143 | int i, j; |
| 144 | |
| 145 | if (phb->version == 4) { |
| 146 | Pnv9Chip *chip9 = PNV9_CHIP(chip); |
| 147 | |
| 148 | pecs = chip9->pecs; |
| 149 | } else if (phb->version == 5) { |
| 150 | Pnv10Chip *chip10 = PNV10_CHIP(chip); |
| 151 | |
| 152 | pecs = chip10->pecs; |
| 153 | } else { |
| 154 | g_assert_not_reached(); |
| 155 | } |
| 156 | |
| 157 | for (i = 0; i < chip->num_pecs; i++) { |
| 158 | /* |
| 159 | * For each PEC, check the amount of phbs it supports |
| 160 | * and see if the given phb4 index matches an index. |
| 161 | */ |
| 162 | PnvPhb4PecState *pec = &pecs[i]; |
| 163 | |
| 164 | for (j = 0; j < pec->num_phbs; j++) { |
| 165 | if (index == pnv_phb4_pec_get_phb_id(pec, j)) { |
| 166 | pec->phbs[j] = phb; |
| 167 | phb->pec = pec; |
| 168 | return pec; |
| 169 | } |
| 170 | } |
| 171 | } |
| 172 | error_setg(errp, |
| 173 | "pnv-phb4 chip-id %d index %d didn't match any existing PEC", |
| 174 | chip_id, index); |
| 175 | |
| 176 | return NULL; |
| 177 | } |
| 178 | |
| 179 | static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecState *pec, |
| 180 | int stack_no, |
| 181 | Error **errp) |
| 182 | { |
| 183 | PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); |
| 184 | int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); |
| 185 | |
| 186 | object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); |
| 187 | object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), |
| 188 | &error_abort); |
| 189 | object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, |
| 190 | &error_fatal); |
| 191 | object_property_set_int(OBJECT(phb), "index", phb_id, |
| 192 | &error_fatal); |
| 193 | |
| 194 | if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { |
| 195 | return NULL; |
| 196 | } |
| 197 | return phb; |
| 198 | } |
| 199 | |
| 200 | #define XPEC_P9_PCI_LANE_CFG PPC_BITMASK(10, 11) |
| 201 | #define XPEC_P10_PCI_LANE_CFG PPC_BITMASK(0, 1) |
| 202 | |
| 203 | static void pnv_pec_realize(DeviceState *dev, Error **errp) |
| 204 | { |
| 205 | PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); |
| 206 | PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); |
| 207 | char name[64]; |
| 208 | int i; |
| 209 | |
| 210 | if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { |
| 211 | error_setg(errp, "invalid PEC index: %d", pec->index); |
| 212 | return; |
| 213 | } |
| 214 | |
| 215 | pec->num_phbs = pecc->num_phbs[pec->index]; |
| 216 | |
| 217 | /* Pervasive chiplet */ |
| 218 | object_initialize_child(OBJECT(pec), "nest-pervasive-common", |
| 219 | &pec->nest_pervasive, |
| 220 | TYPE_PNV_NEST_CHIPLET_PERVASIVE); |
| 221 | if (!qdev_realize(DEVICE(&pec->nest_pervasive), NULL, errp)) { |
| 222 | return; |
| 223 | } |
| 224 | |
| 225 | /* Set up pervasive chiplet registers */ |
| 226 | /* |
| 227 | * Most registers are not set up, this just sets the PCI CONF1 link-width |
| 228 | * field because skiboot probes it. |
| 229 | */ |
| 230 | if (pecc->version == PNV_PHB4_VERSION) { |
| 231 | /* |
| 232 | * On P9, PEC2 has configurable 1/2/3-furcation). |
| 233 | * Make it trifurcated (x8, x4, x4) to match pnv_pec_num_phbs. |
| 234 | */ |
| 235 | if (pec->index == 2) { |
| 236 | pec->nest_pervasive.control_regs.cplt_cfg1 = |
| 237 | SETFIELD(XPEC_P9_PCI_LANE_CFG, |
| 238 | pec->nest_pervasive.control_regs.cplt_cfg1, |
| 239 | 0b10); |
| 240 | } |
| 241 | } else if (pecc->version == PNV_PHB5_VERSION) { |
| 242 | /* |
| 243 | * On P10, both PECs are configurable 1/2/3-furcation). |
| 244 | * Both are trifurcated to match pnv_phb5_pec_num_stacks. |
| 245 | */ |
| 246 | pec->nest_pervasive.control_regs.cplt_cfg1 = |
| 247 | SETFIELD(XPEC_P10_PCI_LANE_CFG, |
| 248 | pec->nest_pervasive.control_regs.cplt_cfg1, |
| 249 | 0b10); |
| 250 | } else { |
| 251 | g_assert_not_reached(); |
| 252 | } |
| 253 | |
| 254 | /* Create PHBs if running with defaults */ |
| 255 | if (defaults_enabled()) { |
| 256 | g_assert(pec->num_phbs <= MAX_PHBS_PER_PEC); |
| 257 | for (i = 0; i < pec->num_phbs; i++) { |
| 258 | pec->phbs[i] = pnv_pec_default_phb_realize(pec, i, errp); |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | /* Initialize the XSCOM regions for the PEC registers */ |
| 263 | snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id, |
| 264 | pec->index); |
| 265 | pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev), |
| 266 | &pnv_pec_nest_xscom_ops, pec, name, |
| 267 | PHB4_PEC_NEST_REGS_COUNT); |
| 268 | |
| 269 | snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id, |
| 270 | pec->index); |
| 271 | pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev), |
| 272 | &pnv_pec_pci_xscom_ops, pec, name, |
| 273 | PHB4_PEC_PCI_REGS_COUNT); |
| 274 | } |
| 275 | |
| 276 | static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, |
| 277 | int xscom_offset) |
| 278 | { |
| 279 | PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); |
| 280 | PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev); |
| 281 | uint32_t nbase = pecc->xscom_nest_base(pec); |
| 282 | uint32_t pbase = pecc->xscom_pci_base(pec); |
| 283 | int offset, i; |
| 284 | char *name; |
| 285 | uint32_t reg[] = { |
| 286 | cpu_to_be32(nbase), |
| 287 | cpu_to_be32(pecc->xscom_nest_size), |
| 288 | cpu_to_be32(pbase), |
| 289 | cpu_to_be32(pecc->xscom_pci_size), |
| 290 | }; |
| 291 | |
| 292 | name = g_strdup_printf("pbcq@%x", nbase); |
| 293 | offset = fdt_add_subnode(fdt, xscom_offset, name); |
| 294 | _FDT(offset); |
| 295 | g_free(name); |
| 296 | |
| 297 | _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); |
| 298 | |
| 299 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index))); |
| 300 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1))); |
| 301 | _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0))); |
| 302 | _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat, |
| 303 | pecc->compat_size))); |
| 304 | |
| 305 | for (i = 0; i < pec->num_phbs; i++) { |
| 306 | int stk_offset; |
| 307 | |
| 308 | if (!pec->phbs[i]) { |
| 309 | continue; |
| 310 | } |
| 311 | |
| 312 | name = g_strdup_printf("stack@%x", i); |
| 313 | stk_offset = fdt_add_subnode(fdt, offset, name); |
| 314 | _FDT(stk_offset); |
| 315 | g_free(name); |
| 316 | _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, |
| 317 | pecc->stk_compat_size))); |
| 318 | _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); |
| 319 | _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", |
| 320 | pec->phbs[i]->phb_id))); |
| 321 | } |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static const Property pnv_pec_properties[] = { |
| 327 | DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), |
| 328 | DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), |
| 329 | DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, |
| 330 | PnvChip *), |
| 331 | }; |
| 332 | |
| 333 | #define XPEC_PCI_CPLT_OFFSET 0x1000000ULL |
| 334 | |
| 335 | static uint32_t pnv_pec_xscom_cplt_base(PnvPhb4PecState *pec) |
| 336 | { |
| 337 | return PNV9_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index; |
| 338 | } |
| 339 | |
| 340 | static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) |
| 341 | { |
| 342 | return PNV9_XSCOM_PEC_PCI_BASE + XPEC_PCI_CPLT_OFFSET * pec->index; |
| 343 | } |
| 344 | |
| 345 | static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) |
| 346 | { |
| 347 | return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; |
| 348 | } |
| 349 | |
| 350 | /* |
| 351 | * PEC0 -> 1 phb |
| 352 | * PEC1 -> 2 phb |
| 353 | * PEC2 -> 3 phbs |
| 354 | */ |
| 355 | static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 }; |
| 356 | |
| 357 | static void pnv_pec_class_init(ObjectClass *klass, const void *data) |
| 358 | { |
| 359 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 360 | PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); |
| 361 | PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); |
| 362 | static const char compat[] = "ibm,power9-pbcq"; |
| 363 | static const char stk_compat[] = "ibm,power9-phb-stack"; |
| 364 | |
| 365 | xdc->dt_xscom = pnv_pec_dt_xscom; |
| 366 | |
| 367 | dc->realize = pnv_pec_realize; |
| 368 | device_class_set_props(dc, pnv_pec_properties); |
| 369 | dc->user_creatable = false; |
| 370 | |
| 371 | pecc->xscom_cplt_base = pnv_pec_xscom_cplt_base; |
| 372 | pecc->xscom_nest_base = pnv_pec_xscom_nest_base; |
| 373 | pecc->xscom_pci_base = pnv_pec_xscom_pci_base; |
| 374 | pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE; |
| 375 | pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE; |
| 376 | pecc->compat = compat; |
| 377 | pecc->compat_size = sizeof(compat); |
| 378 | pecc->stk_compat = stk_compat; |
| 379 | pecc->stk_compat_size = sizeof(stk_compat); |
| 380 | pecc->version = PNV_PHB4_VERSION; |
| 381 | pecc->phb_type = TYPE_PNV_PHB4; |
| 382 | pecc->num_phbs = pnv_pec_num_phbs; |
| 383 | } |
| 384 | |
| 385 | static const TypeInfo pnv_pec_type_info = { |
| 386 | .name = TYPE_PNV_PHB4_PEC, |
| 387 | .parent = TYPE_DEVICE, |
| 388 | .instance_size = sizeof(PnvPhb4PecState), |
| 389 | .class_init = pnv_pec_class_init, |
| 390 | .class_size = sizeof(PnvPhb4PecClass), |
| 391 | .interfaces = (const InterfaceInfo[]) { |
| 392 | { TYPE_PNV_XSCOM_INTERFACE }, |
| 393 | { } |
| 394 | } |
| 395 | }; |
| 396 | |
| 397 | static void pnv_pec_register_types(void) |
| 398 | { |
| 399 | type_register_static(&pnv_pec_type_info); |
| 400 | } |
| 401 | |
| 402 | type_init(pnv_pec_register_types); |