| 1 | /* |
| 2 | * QEMU MCH/ICH9 PCI Bridge Emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * Copyright (c) 2009, 2010, 2011 |
| 6 | * Isaku Yamahata <yamahata at valinux co jp> |
| 7 | * VA Linux Systems Japan K.K. |
| 8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> |
| 9 | * |
| 10 | * This is based on piix.c, but heavily modified. |
| 11 | * |
| 12 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 13 | * of this software and associated documentation files (the "Software"), to deal |
| 14 | * in the Software without restriction, including without limitation the rights |
| 15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 16 | * copies of the Software, and to permit persons to whom the Software is |
| 17 | * furnished to do so, subject to the following conditions: |
| 18 | * |
| 19 | * The above copyright notice and this permission notice shall be included in |
| 20 | * all copies or substantial portions of the Software. |
| 21 | * |
| 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 28 | * THE SOFTWARE. |
| 29 | */ |
| 30 | |
| 31 | #include "qemu/osdep.h" |
| 32 | #include "qemu/log.h" |
| 33 | #include "hw/i386/pc.h" |
| 34 | #include "hw/pci-host/q35.h" |
| 35 | #include "hw/core/qdev-properties.h" |
| 36 | #include "migration/vmstate.h" |
| 37 | #include "qapi/error.h" |
| 38 | #include "qapi/visitor.h" |
| 39 | #include "qemu/module.h" |
| 40 | |
| 41 | /**************************************************************************** |
| 42 | * Q35 host |
| 43 | */ |
| 44 | |
| 45 | #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) |
| 46 | |
| 47 | static void q35_host_realize(DeviceState *dev, Error **errp) |
| 48 | { |
| 49 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
| 50 | Q35PCIHost *s = Q35_HOST_DEVICE(dev); |
| 51 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 52 | |
| 53 | memory_region_add_subregion(s->mch.address_space_io, |
| 54 | MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); |
| 55 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); |
| 56 | |
| 57 | memory_region_add_subregion(s->mch.address_space_io, |
| 58 | MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); |
| 59 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); |
| 60 | |
| 61 | /* register q35 0xcf8 port as coalesced pio */ |
| 62 | memory_region_set_flush_coalesced(&pci->data_mem); |
| 63 | memory_region_add_coalescing(&pci->conf_mem, 0, 4); |
| 64 | |
| 65 | pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", |
| 66 | s->mch.pci_address_space, |
| 67 | s->mch.address_space_io, |
| 68 | 0, TYPE_PCIE_BUS); |
| 69 | |
| 70 | qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); |
| 71 | } |
| 72 | |
| 73 | static const char *q35_host_root_bus_path(PCIHostState *host_bridge, |
| 74 | PCIBus *rootbus) |
| 75 | { |
| 76 | return "0000:00"; |
| 77 | } |
| 78 | |
| 79 | static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, |
| 80 | const char *name, void *opaque, |
| 81 | Error **errp) |
| 82 | { |
| 83 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); |
| 84 | uint64_t val64; |
| 85 | uint32_t value; |
| 86 | |
| 87 | val64 = range_is_empty(&s->mch.pci_hole) |
| 88 | ? 0 : range_lob(&s->mch.pci_hole); |
| 89 | value = val64; |
| 90 | assert(value == val64); |
| 91 | visit_type_uint32(v, name, &value, errp); |
| 92 | } |
| 93 | |
| 94 | static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, |
| 95 | const char *name, void *opaque, |
| 96 | Error **errp) |
| 97 | { |
| 98 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); |
| 99 | uint64_t val64; |
| 100 | uint32_t value; |
| 101 | |
| 102 | val64 = range_is_empty(&s->mch.pci_hole) |
| 103 | ? 0 : range_upb(&s->mch.pci_hole) + 1; |
| 104 | value = val64; |
| 105 | assert(value == val64); |
| 106 | visit_type_uint32(v, name, &value, errp); |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * The 64bit PCI hole start is set by the Guest firmware |
| 111 | * as the address of the first 64bit PCI MEM resource. |
| 112 | * If no PCI device has resources on the 64bit area, |
| 113 | * the 64bit PCI hole will start after "over 4G RAM" and the |
| 114 | * reserved space for memory hotplug if any. |
| 115 | */ |
| 116 | static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) |
| 117 | { |
| 118 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 119 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); |
| 120 | Range w64; |
| 121 | uint64_t value; |
| 122 | |
| 123 | pci_bus_get_w64_range(h->bus, &w64); |
| 124 | value = range_is_empty(&w64) ? 0 : range_lob(&w64); |
| 125 | if (!value && s->pci_hole64_fix) { |
| 126 | value = pc_pci_hole64_start(); |
| 127 | } |
| 128 | return value; |
| 129 | } |
| 130 | |
| 131 | static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, |
| 132 | const char *name, void *opaque, |
| 133 | Error **errp) |
| 134 | { |
| 135 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 136 | uint64_t hole64_start; |
| 137 | |
| 138 | if (!h->bus) { |
| 139 | error_setg(errp, "PCI host bridge not realized"); |
| 140 | return; |
| 141 | } |
| 142 | hole64_start = q35_host_get_pci_hole64_start_value(obj); |
| 143 | visit_type_uint64(v, name, &hole64_start, errp); |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * The 64bit PCI hole end is set by the Guest firmware |
| 148 | * as the address of the last 64bit PCI MEM resource. |
| 149 | * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE |
| 150 | * that can be configured by the user. |
| 151 | */ |
| 152 | static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, |
| 153 | const char *name, void *opaque, |
| 154 | Error **errp) |
| 155 | { |
| 156 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
| 157 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); |
| 158 | uint64_t hole64_start; |
| 159 | Range w64; |
| 160 | uint64_t value, hole64_end; |
| 161 | |
| 162 | if (!h->bus) { |
| 163 | error_setg(errp, "PCI host bridge not realized"); |
| 164 | return; |
| 165 | } |
| 166 | hole64_start = q35_host_get_pci_hole64_start_value(obj); |
| 167 | pci_bus_get_w64_range(h->bus, &w64); |
| 168 | value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; |
| 169 | hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); |
| 170 | if (s->pci_hole64_fix && value < hole64_end) { |
| 171 | value = hole64_end; |
| 172 | } |
| 173 | visit_type_uint64(v, name, &value, errp); |
| 174 | } |
| 175 | |
| 176 | /* |
| 177 | * NOTE: setting defaults for the mch.* fields in this table |
| 178 | * doesn't work, because mch is a separate QOM object that is |
| 179 | * zeroed by the object_initialize(&s->mch, ...) call inside |
| 180 | * q35_host_initfn(). The default values for those |
| 181 | * properties need to be initialized manually by |
| 182 | * q35_host_initfn() after the object_initialize() call. |
| 183 | */ |
| 184 | static const Property q35_host_props[] = { |
| 185 | DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, |
| 186 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), |
| 187 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, |
| 188 | mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), |
| 189 | DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, |
| 190 | mch.below_4g_mem_size, 0), |
| 191 | DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, |
| 192 | mch.above_4g_mem_size, 0), |
| 193 | DEFINE_PROP_BOOL(PCI_HOST_PROP_SMM_RANGES, Q35PCIHost, |
| 194 | mch.has_smm_ranges, true), |
| 195 | DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), |
| 196 | }; |
| 197 | |
| 198 | static void q35_host_class_init(ObjectClass *klass, const void *data) |
| 199 | { |
| 200 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 201 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
| 202 | |
| 203 | hc->root_bus_path = q35_host_root_bus_path; |
| 204 | dc->realize = q35_host_realize; |
| 205 | device_class_set_props(dc, q35_host_props); |
| 206 | /* Reason: needs to be wired up by pc_q35_init */ |
| 207 | dc->user_creatable = false; |
| 208 | dc->fw_name = "pci"; |
| 209 | } |
| 210 | |
| 211 | static void q35_host_initfn(Object *obj) |
| 212 | { |
| 213 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); |
| 214 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); |
| 215 | PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); |
| 216 | |
| 217 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, |
| 218 | "pci-conf-idx", 4); |
| 219 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, |
| 220 | "pci-conf-data", 4); |
| 221 | |
| 222 | object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); |
| 223 | qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); |
| 224 | qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); |
| 225 | /* mch's object_initialize resets the default value, set it again */ |
| 226 | qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, |
| 227 | Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); |
| 228 | |
| 229 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", |
| 230 | q35_host_get_pci_hole_start, |
| 231 | NULL, NULL, NULL); |
| 232 | |
| 233 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", |
| 234 | q35_host_get_pci_hole_end, |
| 235 | NULL, NULL, NULL); |
| 236 | |
| 237 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", |
| 238 | q35_host_get_pci_hole64_start, |
| 239 | NULL, NULL, NULL); |
| 240 | |
| 241 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", |
| 242 | q35_host_get_pci_hole64_end, |
| 243 | NULL, NULL, NULL); |
| 244 | |
| 245 | object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, |
| 246 | &pehb->size, OBJ_PROP_FLAG_READ); |
| 247 | |
| 248 | object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, |
| 249 | (Object **) &s->mch.ram_memory, |
| 250 | qdev_prop_allow_set_link_before_realize, 0); |
| 251 | |
| 252 | object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, |
| 253 | (Object **) &s->mch.pci_address_space, |
| 254 | qdev_prop_allow_set_link_before_realize, 0); |
| 255 | |
| 256 | object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, |
| 257 | (Object **) &s->mch.system_memory, |
| 258 | qdev_prop_allow_set_link_before_realize, 0); |
| 259 | |
| 260 | object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, |
| 261 | (Object **) &s->mch.address_space_io, |
| 262 | qdev_prop_allow_set_link_before_realize, 0); |
| 263 | } |
| 264 | |
| 265 | static const TypeInfo q35_host_info = { |
| 266 | .name = TYPE_Q35_HOST_DEVICE, |
| 267 | .parent = TYPE_PCIE_HOST_BRIDGE, |
| 268 | .instance_size = sizeof(Q35PCIHost), |
| 269 | .instance_init = q35_host_initfn, |
| 270 | .class_init = q35_host_class_init, |
| 271 | }; |
| 272 | |
| 273 | /**************************************************************************** |
| 274 | * MCH D0:F0 |
| 275 | */ |
| 276 | |
| 277 | static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) |
| 278 | { |
| 279 | return 0xffffffff; |
| 280 | } |
| 281 | |
| 282 | static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, |
| 283 | unsigned width) |
| 284 | { |
| 285 | /* nothing */ |
| 286 | } |
| 287 | |
| 288 | static const MemoryRegionOps blackhole_ops = { |
| 289 | .read = blackhole_read, |
| 290 | .write = blackhole_write, |
| 291 | .valid.min_access_size = 1, |
| 292 | .valid.max_access_size = 4, |
| 293 | .impl.min_access_size = 4, |
| 294 | .impl.max_access_size = 4, |
| 295 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 296 | }; |
| 297 | |
| 298 | /* PCIe MMCFG */ |
| 299 | static void mch_update_pciexbar(MCHPCIState *mch) |
| 300 | { |
| 301 | PCIDevice *pci_dev = PCI_DEVICE(mch); |
| 302 | BusState *bus = qdev_get_parent_bus(DEVICE(mch)); |
| 303 | PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); |
| 304 | |
| 305 | uint64_t pciexbar; |
| 306 | int enable; |
| 307 | uint64_t addr; |
| 308 | uint64_t addr_mask; |
| 309 | uint32_t length; |
| 310 | |
| 311 | pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); |
| 312 | enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; |
| 313 | addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; |
| 314 | switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { |
| 315 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: |
| 316 | length = 256 * 1024 * 1024; |
| 317 | break; |
| 318 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: |
| 319 | length = 128 * 1024 * 1024; |
| 320 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; |
| 321 | break; |
| 322 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: |
| 323 | length = 64 * 1024 * 1024; |
| 324 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK | |
| 325 | MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; |
| 326 | break; |
| 327 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: |
| 328 | qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); |
| 329 | return; |
| 330 | default: |
| 331 | abort(); |
| 332 | } |
| 333 | addr = pciexbar & addr_mask; |
| 334 | pcie_host_mmcfg_update(pehb, enable, addr, length); |
| 335 | } |
| 336 | |
| 337 | /* PAM */ |
| 338 | static void mch_update_pam(MCHPCIState *mch) |
| 339 | { |
| 340 | PCIDevice *pd = PCI_DEVICE(mch); |
| 341 | int i; |
| 342 | |
| 343 | memory_region_transaction_begin(); |
| 344 | for (i = 0; i < 13; i++) { |
| 345 | pam_update(&mch->pam_regions[i], i, |
| 346 | pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); |
| 347 | } |
| 348 | memory_region_transaction_commit(); |
| 349 | } |
| 350 | |
| 351 | /* SMRAM */ |
| 352 | static void mch_update_smram(MCHPCIState *mch) |
| 353 | { |
| 354 | PCIDevice *pd = PCI_DEVICE(mch); |
| 355 | bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); |
| 356 | uint32_t tseg_size; |
| 357 | |
| 358 | /* implement SMRAM.D_LCK */ |
| 359 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { |
| 360 | pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; |
| 361 | pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; |
| 362 | pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; |
| 363 | } |
| 364 | |
| 365 | memory_region_transaction_begin(); |
| 366 | |
| 367 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { |
| 368 | /* Hide (!) low SMRAM if H_SMRAME = 1 */ |
| 369 | memory_region_set_enabled(&mch->smram_region, h_smrame); |
| 370 | /* Show high SMRAM if H_SMRAME = 1 */ |
| 371 | memory_region_set_enabled(&mch->open_high_smram, h_smrame); |
| 372 | } else { |
| 373 | /* Hide high SMRAM and low SMRAM */ |
| 374 | memory_region_set_enabled(&mch->smram_region, true); |
| 375 | memory_region_set_enabled(&mch->open_high_smram, false); |
| 376 | } |
| 377 | |
| 378 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { |
| 379 | memory_region_set_enabled(&mch->low_smram, !h_smrame); |
| 380 | memory_region_set_enabled(&mch->high_smram, h_smrame); |
| 381 | } else { |
| 382 | memory_region_set_enabled(&mch->low_smram, false); |
| 383 | memory_region_set_enabled(&mch->high_smram, false); |
| 384 | } |
| 385 | |
| 386 | if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && |
| 387 | (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { |
| 388 | switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & |
| 389 | MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { |
| 390 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: |
| 391 | tseg_size = 1024 * 1024; |
| 392 | break; |
| 393 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: |
| 394 | tseg_size = 1024 * 1024 * 2; |
| 395 | break; |
| 396 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: |
| 397 | tseg_size = 1024 * 1024 * 8; |
| 398 | break; |
| 399 | default: |
| 400 | tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; |
| 401 | break; |
| 402 | } |
| 403 | } else { |
| 404 | tseg_size = 0; |
| 405 | } |
| 406 | memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); |
| 407 | memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); |
| 408 | memory_region_set_size(&mch->tseg_blackhole, tseg_size); |
| 409 | memory_region_add_subregion_overlap(mch->system_memory, |
| 410 | mch->below_4g_mem_size - tseg_size, |
| 411 | &mch->tseg_blackhole, 1); |
| 412 | |
| 413 | memory_region_set_enabled(&mch->tseg_window, tseg_size); |
| 414 | memory_region_set_size(&mch->tseg_window, tseg_size); |
| 415 | memory_region_set_address(&mch->tseg_window, |
| 416 | mch->below_4g_mem_size - tseg_size); |
| 417 | memory_region_set_alias_offset(&mch->tseg_window, |
| 418 | mch->below_4g_mem_size - tseg_size); |
| 419 | |
| 420 | memory_region_transaction_commit(); |
| 421 | } |
| 422 | |
| 423 | static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) |
| 424 | { |
| 425 | PCIDevice *pd = PCI_DEVICE(mch); |
| 426 | uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; |
| 427 | |
| 428 | if (mch->ext_tseg_mbytes > 0 && |
| 429 | pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { |
| 430 | pci_set_word(reg, mch->ext_tseg_mbytes); |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | static void mch_update_smbase_smram(MCHPCIState *mch) |
| 435 | { |
| 436 | PCIDevice *pd = PCI_DEVICE(mch); |
| 437 | uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; |
| 438 | bool lck; |
| 439 | |
| 440 | if (!mch->has_smram_at_smbase) { |
| 441 | return; |
| 442 | } |
| 443 | |
| 444 | if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { |
| 445 | pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = MCH_HOST_BRIDGE_F_SMBASE_LCK; |
| 446 | *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; |
| 447 | return; |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * reg value can come from register write/reset/migration source, |
| 452 | * update wmask to be in sync with it regardless of source |
| 453 | */ |
| 454 | if (*reg == MCH_HOST_BRIDGE_F_SMBASE_IN_RAM) { |
| 455 | pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = MCH_HOST_BRIDGE_F_SMBASE_LCK; |
| 456 | return; |
| 457 | } |
| 458 | if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { |
| 459 | /* lock register at 0x2 and disable all writes */ |
| 460 | pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0; |
| 461 | *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; |
| 462 | } |
| 463 | |
| 464 | lck = *reg & MCH_HOST_BRIDGE_F_SMBASE_LCK; |
| 465 | memory_region_transaction_begin(); |
| 466 | memory_region_set_enabled(&mch->smbase_blackhole, lck); |
| 467 | memory_region_set_enabled(&mch->smbase_window, lck); |
| 468 | memory_region_transaction_commit(); |
| 469 | } |
| 470 | |
| 471 | static void mch_write_config(PCIDevice *d, |
| 472 | uint32_t address, uint32_t val, int len) |
| 473 | { |
| 474 | MCHPCIState *mch = MCH_PCI_DEVICE(d); |
| 475 | |
| 476 | pci_default_write_config(d, address, val, len); |
| 477 | |
| 478 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, |
| 479 | MCH_HOST_BRIDGE_PAM_SIZE)) { |
| 480 | mch_update_pam(mch); |
| 481 | } |
| 482 | |
| 483 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, |
| 484 | MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { |
| 485 | mch_update_pciexbar(mch); |
| 486 | } |
| 487 | |
| 488 | if (mch->has_smm_ranges) { |
| 489 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, |
| 490 | MCH_HOST_BRIDGE_SMRAM_SIZE)) { |
| 491 | mch_update_smram(mch); |
| 492 | } |
| 493 | |
| 494 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, |
| 495 | MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { |
| 496 | mch_update_ext_tseg_mbytes(mch); |
| 497 | } |
| 498 | |
| 499 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { |
| 500 | mch_update_smbase_smram(mch); |
| 501 | } |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | static void mch_update(MCHPCIState *mch) |
| 506 | { |
| 507 | mch_update_pciexbar(mch); |
| 508 | |
| 509 | mch_update_pam(mch); |
| 510 | if (mch->has_smm_ranges) { |
| 511 | mch_update_smram(mch); |
| 512 | mch_update_ext_tseg_mbytes(mch); |
| 513 | mch_update_smbase_smram(mch); |
| 514 | } |
| 515 | |
| 516 | /* |
| 517 | * pci hole goes from end-of-low-ram to io-apic. |
| 518 | * mmconfig will be excluded by the dsdt builder. |
| 519 | */ |
| 520 | range_set_bounds(&mch->pci_hole, |
| 521 | mch->below_4g_mem_size, |
| 522 | IO_APIC_DEFAULT_ADDRESS - 1); |
| 523 | } |
| 524 | |
| 525 | static int mch_post_load(void *opaque, int version_id) |
| 526 | { |
| 527 | MCHPCIState *mch = opaque; |
| 528 | mch_update(mch); |
| 529 | return 0; |
| 530 | } |
| 531 | |
| 532 | static const VMStateDescription vmstate_mch = { |
| 533 | .name = "mch", |
| 534 | .version_id = 1, |
| 535 | .minimum_version_id = 1, |
| 536 | .post_load = mch_post_load, |
| 537 | .fields = (const VMStateField[]) { |
| 538 | VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), |
| 539 | /* Used to be smm_enabled, which was basically always zero because |
| 540 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. |
| 541 | */ |
| 542 | VMSTATE_UNUSED(1), |
| 543 | VMSTATE_END_OF_LIST() |
| 544 | } |
| 545 | }; |
| 546 | |
| 547 | static void mch_reset(DeviceState *qdev) |
| 548 | { |
| 549 | PCIDevice *d = PCI_DEVICE(qdev); |
| 550 | MCHPCIState *mch = MCH_PCI_DEVICE(d); |
| 551 | |
| 552 | pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, |
| 553 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); |
| 554 | |
| 555 | if (mch->has_smm_ranges) { |
| 556 | d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; |
| 557 | d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; |
| 558 | d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; |
| 559 | d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; |
| 560 | |
| 561 | if (mch->ext_tseg_mbytes > 0) { |
| 562 | pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, |
| 563 | MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); |
| 564 | } |
| 565 | |
| 566 | d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; |
| 567 | d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; |
| 568 | } |
| 569 | |
| 570 | mch_update(mch); |
| 571 | } |
| 572 | |
| 573 | static void mch_init_smram_regions(MCHPCIState *mch) |
| 574 | { |
| 575 | /* Initialize all the SMRAM specific MemoryRegions */ |
| 576 | memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", |
| 577 | mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 578 | MCH_HOST_BRIDGE_SMRAM_C_SIZE); |
| 579 | memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, |
| 580 | &mch->open_high_smram, 1); |
| 581 | memory_region_set_enabled(&mch->open_high_smram, false); |
| 582 | |
| 583 | /* smram, as seen by SMM CPUs */ |
| 584 | memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB); |
| 585 | memory_region_set_enabled(&mch->smram, true); |
| 586 | memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", |
| 587 | mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 588 | MCH_HOST_BRIDGE_SMRAM_C_SIZE); |
| 589 | memory_region_set_enabled(&mch->low_smram, true); |
| 590 | memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 591 | &mch->low_smram); |
| 592 | memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", |
| 593 | mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 594 | MCH_HOST_BRIDGE_SMRAM_C_SIZE); |
| 595 | memory_region_set_enabled(&mch->high_smram, true); |
| 596 | memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); |
| 597 | |
| 598 | memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), |
| 599 | &blackhole_ops, NULL, |
| 600 | "tseg-blackhole", 0); |
| 601 | memory_region_set_enabled(&mch->tseg_blackhole, false); |
| 602 | memory_region_add_subregion_overlap(mch->system_memory, |
| 603 | mch->below_4g_mem_size, |
| 604 | &mch->tseg_blackhole, 1); |
| 605 | |
| 606 | memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", |
| 607 | mch->ram_memory, mch->below_4g_mem_size, 0); |
| 608 | memory_region_set_enabled(&mch->tseg_window, false); |
| 609 | memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, |
| 610 | &mch->tseg_window); |
| 611 | |
| 612 | /* |
| 613 | * This is not what hardware does, so it's QEMU specific hack. |
| 614 | * See commit message for details. |
| 615 | */ |
| 616 | memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, |
| 617 | NULL, "smbase-blackhole", |
| 618 | MCH_HOST_BRIDGE_SMBASE_SIZE); |
| 619 | memory_region_set_enabled(&mch->smbase_blackhole, false); |
| 620 | memory_region_add_subregion_overlap(mch->system_memory, |
| 621 | MCH_HOST_BRIDGE_SMBASE_ADDR, |
| 622 | &mch->smbase_blackhole, 1); |
| 623 | |
| 624 | memory_region_init_alias(&mch->smbase_window, OBJECT(mch), |
| 625 | "smbase-window", mch->ram_memory, |
| 626 | MCH_HOST_BRIDGE_SMBASE_ADDR, |
| 627 | MCH_HOST_BRIDGE_SMBASE_SIZE); |
| 628 | memory_region_set_enabled(&mch->smbase_window, false); |
| 629 | memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, |
| 630 | &mch->smbase_window); |
| 631 | } |
| 632 | |
| 633 | static void mch_realize(PCIDevice *d, Error **errp) |
| 634 | { |
| 635 | int i; |
| 636 | MCHPCIState *mch = MCH_PCI_DEVICE(d); |
| 637 | |
| 638 | if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { |
| 639 | error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, |
| 640 | mch->ext_tseg_mbytes); |
| 641 | return; |
| 642 | } |
| 643 | |
| 644 | /* setup pci memory mapping */ |
| 645 | pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); |
| 646 | |
| 647 | /* PAM */ |
| 648 | init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory, |
| 649 | mch->system_memory, mch->pci_address_space, |
| 650 | PAM_BIOS_BASE, PAM_BIOS_SIZE); |
| 651 | for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { |
| 652 | init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory, |
| 653 | mch->system_memory, mch->pci_address_space, |
| 654 | PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); |
| 655 | } |
| 656 | |
| 657 | /* |
| 658 | * This memory region looks like it's SMM specific, but it is not. |
| 659 | * It's an alias that makes the pci_address_space appear in system |
| 660 | * memory at the SMRAM_C_BASE address. The alias is enabled when the |
| 661 | * CPU should not see SMRAM, and *disabled* when the low SMRAM should be |
| 662 | * visible. So for non-SMM configs we need to create the alias, and |
| 663 | * leave it permanently enabled. |
| 664 | */ |
| 665 | memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", |
| 666 | mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 667 | MCH_HOST_BRIDGE_SMRAM_C_SIZE); |
| 668 | memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, |
| 669 | &mch->smram_region, 1); |
| 670 | memory_region_set_enabled(&mch->smram_region, true); |
| 671 | |
| 672 | if (mch->has_smm_ranges) { |
| 673 | mch_init_smram_regions(mch); |
| 674 | object_property_add_const_link(qdev_get_machine(), "smram", |
| 675 | OBJECT(&mch->smram)); |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | static const Property mch_props[] = { |
| 680 | DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, |
| 681 | 64), |
| 682 | DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), |
| 683 | }; |
| 684 | |
| 685 | static void mch_class_init(ObjectClass *klass, const void *data) |
| 686 | { |
| 687 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 688 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 689 | |
| 690 | k->realize = mch_realize; |
| 691 | k->config_write = mch_write_config; |
| 692 | device_class_set_legacy_reset(dc, mch_reset); |
| 693 | device_class_set_props(dc, mch_props); |
| 694 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 695 | dc->desc = "Host bridge"; |
| 696 | dc->vmsd = &vmstate_mch; |
| 697 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 698 | /* |
| 699 | * The 'q35' machine type implements an Intel Series 3 chipset, |
| 700 | * of which there are several variants. The key difference between |
| 701 | * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that |
| 702 | * the latter has an integrated graphics adapter. QEMU does not |
| 703 | * implement integrated graphics, so uses the PCI ID for the 82P35 |
| 704 | * chipset. |
| 705 | */ |
| 706 | k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; |
| 707 | k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; |
| 708 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 709 | /* |
| 710 | * PCI-facing part of the host bridge, not usable without the |
| 711 | * host-facing part, which can't be device_add'ed, yet. |
| 712 | */ |
| 713 | dc->user_creatable = false; |
| 714 | } |
| 715 | |
| 716 | static const TypeInfo mch_info = { |
| 717 | .name = TYPE_MCH_PCI_DEVICE, |
| 718 | .parent = TYPE_PCI_DEVICE, |
| 719 | .instance_size = sizeof(MCHPCIState), |
| 720 | .class_init = mch_class_init, |
| 721 | .interfaces = (const InterfaceInfo[]) { |
| 722 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 723 | { }, |
| 724 | }, |
| 725 | }; |
| 726 | |
| 727 | static void q35_register(void) |
| 728 | { |
| 729 | type_register_static(&mch_info); |
| 730 | type_register_static(&q35_host_info); |
| 731 | } |
| 732 | |
| 733 | type_init(q35_register); |