| 1 | /* |
| 2 | * pci_host.c |
| 3 | * |
| 4 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> |
| 5 | * VA Linux Systems Japan K.K. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "hw/pci/pci.h" |
| 23 | #include "hw/pci/pci_bridge.h" |
| 24 | #include "hw/pci/pci_host.h" |
| 25 | #include "hw/core/qdev-properties.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "hw/pci/pci_bus.h" |
| 28 | #include "migration/vmstate.h" |
| 29 | #include "trace.h" |
| 30 | |
| 31 | /* debug PCI */ |
| 32 | //#define DEBUG_PCI |
| 33 | |
| 34 | #ifdef DEBUG_PCI |
| 35 | #define PCI_DPRINTF(fmt, ...) \ |
| 36 | do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) |
| 37 | #else |
| 38 | #define PCI_DPRINTF(fmt, ...) |
| 39 | #endif |
| 40 | |
| 41 | /* |
| 42 | * PCI address |
| 43 | * bit 16 - 24: bus number |
| 44 | * bit 8 - 15: devfun number |
| 45 | * bit 0 - 7: offset in configuration space of a given pci device |
| 46 | */ |
| 47 | |
| 48 | /* the helper function to get a PCIDevice* for a given pci address */ |
| 49 | static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) |
| 50 | { |
| 51 | uint8_t bus_num = addr >> 16; |
| 52 | uint8_t devfn = addr >> 8; |
| 53 | |
| 54 | return pci_find_device(bus, bus_num, devfn); |
| 55 | } |
| 56 | |
| 57 | static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) |
| 58 | { |
| 59 | if ((*limit > PCI_CONFIG_SPACE_SIZE) && |
| 60 | !pci_bus_allows_extended_config_space(bus)) { |
| 61 | *limit = PCI_CONFIG_SPACE_SIZE; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | static bool is_pci_dev_ejected(PCIDevice *pci_dev) |
| 66 | { |
| 67 | /* |
| 68 | * device unplug was requested and the guest acked it, |
| 69 | * so we stop responding config accesses even if the |
| 70 | * device is not deleted (failover flow) |
| 71 | */ |
| 72 | return pci_dev && pci_dev->partially_hotplugged && |
| 73 | !pci_dev->qdev.pending_deleted_event; |
| 74 | } |
| 75 | |
| 76 | void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, |
| 77 | uint32_t limit, uint32_t val, uint32_t len) |
| 78 | { |
| 79 | pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); |
| 80 | if (limit <= addr) { |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | if (len > 4) { |
| 85 | PCI_DPRINTF("%s: invalid length access: addr " HWADDR_FMT_plx " \ |
| 86 | len %d val %"PRIx32"\n", __func__, addr, len, val); |
| 87 | return; |
| 88 | } |
| 89 | |
| 90 | /* non-zero functions are only exposed when function 0 is present, |
| 91 | * allowing direct removal of unexposed functions. |
| 92 | */ |
| 93 | if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || |
| 94 | !pci_dev->enabled || is_pci_dev_ejected(pci_dev)) { |
| 95 | return; |
| 96 | } |
| 97 | |
| 98 | trace_pci_cfg_write(pci_dev->name, pci_dev_bus_num(pci_dev), |
| 99 | PCI_SLOT(pci_dev->devfn), |
| 100 | PCI_FUNC(pci_dev->devfn), addr, val); |
| 101 | pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); |
| 102 | } |
| 103 | |
| 104 | uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, |
| 105 | uint32_t limit, uint32_t len) |
| 106 | { |
| 107 | uint32_t ret; |
| 108 | |
| 109 | pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); |
| 110 | if (limit <= addr) { |
| 111 | return ~0x0; |
| 112 | } |
| 113 | |
| 114 | if (len > 4) { |
| 115 | PCI_DPRINTF("%s: invalid length access: addr " HWADDR_FMT_plx " \ |
| 116 | len %d val %"PRIx32"\n", __func__, addr, len, val); |
| 117 | return ~0x0; |
| 118 | } |
| 119 | |
| 120 | /* non-zero functions are only exposed when function 0 is present, |
| 121 | * allowing direct removal of unexposed functions. |
| 122 | */ |
| 123 | if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || |
| 124 | !pci_dev->enabled || is_pci_dev_ejected(pci_dev)) { |
| 125 | return ~0x0; |
| 126 | } |
| 127 | |
| 128 | ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); |
| 129 | trace_pci_cfg_read(pci_dev->name, pci_dev_bus_num(pci_dev), |
| 130 | PCI_SLOT(pci_dev->devfn), |
| 131 | PCI_FUNC(pci_dev->devfn), addr, ret); |
| 132 | |
| 133 | return ret; |
| 134 | } |
| 135 | |
| 136 | void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len) |
| 137 | { |
| 138 | PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
| 139 | uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); |
| 140 | |
| 141 | if (!pci_dev) { |
| 142 | trace_pci_cfg_write("empty", extract32(addr, 16, 8), |
| 143 | extract32(addr, 11, 5), extract32(addr, 8, 3), |
| 144 | config_addr, val); |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, |
| 149 | val, len); |
| 150 | } |
| 151 | |
| 152 | uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len) |
| 153 | { |
| 154 | PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
| 155 | uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); |
| 156 | |
| 157 | if (!pci_dev) { |
| 158 | trace_pci_cfg_read("empty", extract32(addr, 16, 8), |
| 159 | extract32(addr, 11, 5), extract32(addr, 8, 3), |
| 160 | config_addr, ~0x0); |
| 161 | return ~0x0; |
| 162 | } |
| 163 | |
| 164 | return pci_host_config_read_common(pci_dev, config_addr, |
| 165 | PCI_CONFIG_SPACE_SIZE, len); |
| 166 | } |
| 167 | |
| 168 | static void pci_host_config_write(void *opaque, hwaddr addr, |
| 169 | uint64_t val, unsigned len) |
| 170 | { |
| 171 | PCIHostState *s = opaque; |
| 172 | |
| 173 | PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n", |
| 174 | __func__, addr, len, val); |
| 175 | if (addr != 0 || len != 4) { |
| 176 | return; |
| 177 | } |
| 178 | s->config_reg = val; |
| 179 | } |
| 180 | |
| 181 | static uint64_t pci_host_config_read(void *opaque, hwaddr addr, |
| 182 | unsigned len) |
| 183 | { |
| 184 | PCIHostState *s = opaque; |
| 185 | uint32_t val = s->config_reg; |
| 186 | |
| 187 | PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n", |
| 188 | __func__, addr, len, val); |
| 189 | return val; |
| 190 | } |
| 191 | |
| 192 | static void pci_host_data_write(void *opaque, hwaddr addr, |
| 193 | uint64_t val, unsigned len) |
| 194 | { |
| 195 | PCIHostState *s = opaque; |
| 196 | |
| 197 | if (s->config_reg & (1u << 31)) |
| 198 | pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); |
| 199 | } |
| 200 | |
| 201 | static uint64_t pci_host_data_read(void *opaque, |
| 202 | hwaddr addr, unsigned len) |
| 203 | { |
| 204 | PCIHostState *s = opaque; |
| 205 | |
| 206 | if (!(s->config_reg & (1U << 31))) { |
| 207 | return 0xffffffff; |
| 208 | } |
| 209 | return pci_data_read(s->bus, s->config_reg | (addr & 3), len); |
| 210 | } |
| 211 | |
| 212 | const MemoryRegionOps pci_host_conf_le_ops = { |
| 213 | .read = pci_host_config_read, |
| 214 | .write = pci_host_config_write, |
| 215 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 216 | }; |
| 217 | |
| 218 | const MemoryRegionOps pci_host_conf_be_ops = { |
| 219 | .read = pci_host_config_read, |
| 220 | .write = pci_host_config_write, |
| 221 | .endianness = DEVICE_BIG_ENDIAN, |
| 222 | }; |
| 223 | |
| 224 | const MemoryRegionOps pci_host_data_le_ops = { |
| 225 | .read = pci_host_data_read, |
| 226 | .write = pci_host_data_write, |
| 227 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 228 | }; |
| 229 | |
| 230 | static bool pci_host_needed(void *opaque) |
| 231 | { |
| 232 | PCIHostState *s = opaque; |
| 233 | return s->mig_enabled; |
| 234 | } |
| 235 | |
| 236 | const VMStateDescription vmstate_pcihost = { |
| 237 | .name = "PCIHost", |
| 238 | .needed = pci_host_needed, |
| 239 | .version_id = 1, |
| 240 | .minimum_version_id = 1, |
| 241 | .fields = (const VMStateField[]) { |
| 242 | VMSTATE_UINT32(config_reg, PCIHostState), |
| 243 | VMSTATE_END_OF_LIST() |
| 244 | } |
| 245 | }; |
| 246 | |
| 247 | static const Property pci_host_properties_common[] = { |
| 248 | DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, |
| 249 | mig_enabled, true), |
| 250 | DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false), |
| 251 | }; |
| 252 | |
| 253 | static void pci_host_class_init(ObjectClass *klass, const void *data) |
| 254 | { |
| 255 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 256 | device_class_set_props(dc, pci_host_properties_common); |
| 257 | dc->vmsd = &vmstate_pcihost; |
| 258 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 259 | } |
| 260 | |
| 261 | static const TypeInfo pci_host_type_info = { |
| 262 | .name = TYPE_PCI_HOST_BRIDGE, |
| 263 | .parent = TYPE_SYS_BUS_DEVICE, |
| 264 | .abstract = true, |
| 265 | .class_size = sizeof(PCIHostBridgeClass), |
| 266 | .instance_size = sizeof(PCIHostState), |
| 267 | .class_init = pci_host_class_init, |
| 268 | }; |
| 269 | |
| 270 | static void pci_host_register_types(void) |
| 271 | { |
| 272 | type_register_static(&pci_host_type_info); |
| 273 | } |
| 274 | |
| 275 | type_init(pci_host_register_types) |