| 1 | /* |
| 2 | * pcie.c |
| 3 | * |
| 4 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> |
| 5 | * VA Linux Systems Japan K.K. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "hw/pci/pci_bridge.h" |
| 24 | #include "hw/pci/pcie.h" |
| 25 | #include "hw/pci/msix.h" |
| 26 | #include "hw/pci/msi.h" |
| 27 | #include "hw/pci/pci_bus.h" |
| 28 | #include "hw/pci/pcie_regs.h" |
| 29 | #include "hw/pci/pcie_port.h" |
| 30 | #include "qemu/range.h" |
| 31 | #include "trace.h" |
| 32 | |
| 33 | //#define DEBUG_PCIE |
| 34 | #ifdef DEBUG_PCIE |
| 35 | # define PCIE_DPRINTF(fmt, ...) \ |
| 36 | fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) |
| 37 | #else |
| 38 | # define PCIE_DPRINTF(fmt, ...) do {} while (0) |
| 39 | #endif |
| 40 | #define PCIE_DEV_PRINTF(dev, fmt, ...) \ |
| 41 | PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) |
| 42 | |
| 43 | static bool pcie_sltctl_powered_off(uint16_t sltctl) |
| 44 | { |
| 45 | return (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF |
| 46 | && (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF; |
| 47 | } |
| 48 | |
| 49 | static const char *pcie_led_state_to_str(uint16_t value) |
| 50 | { |
| 51 | switch (value) { |
| 52 | case PCI_EXP_SLTCTL_PWR_IND_ON: |
| 53 | case PCI_EXP_SLTCTL_ATTN_IND_ON: |
| 54 | return "on"; |
| 55 | case PCI_EXP_SLTCTL_PWR_IND_BLINK: |
| 56 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
| 57 | return "blink"; |
| 58 | case PCI_EXP_SLTCTL_PWR_IND_OFF: |
| 59 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
| 60 | return "off"; |
| 61 | default: |
| 62 | return "invalid"; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | /*************************************************************************** |
| 67 | * pci express capability helper functions |
| 68 | */ |
| 69 | |
| 70 | static void |
| 71 | pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) |
| 72 | { |
| 73 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 74 | uint8_t *cmask = dev->cmask + dev->exp.exp_cap; |
| 75 | |
| 76 | /* capability register |
| 77 | interrupt message number defaults to 0 */ |
| 78 | pci_set_word(exp_cap + PCI_EXP_FLAGS, |
| 79 | ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | |
| 80 | version); |
| 81 | |
| 82 | /* device capability register |
| 83 | * table 7-12: |
| 84 | * roll based error reporting bit must be set by all |
| 85 | * Functions conforming to the ECN, PCI Express Base |
| 86 | * Specification, Revision 1.1., or subsequent PCI Express Base |
| 87 | * Specification revisions. |
| 88 | */ |
| 89 | uint32_t devcap = PCI_EXP_DEVCAP_RBER; |
| 90 | |
| 91 | if (dev->cap_present & QEMU_PCIE_EXT_TAG) { |
| 92 | devcap = PCI_EXP_DEVCAP_RBER | PCI_EXP_DEVCAP_EXT_TAG; |
| 93 | } |
| 94 | |
| 95 | pci_set_long(exp_cap + PCI_EXP_DEVCAP, devcap); |
| 96 | |
| 97 | pci_set_long(exp_cap + PCI_EXP_LNKCAP, |
| 98 | (port << PCI_EXP_LNKCAP_PN_SHIFT) | |
| 99 | PCI_EXP_LNKCAP_ASPMS_0S | |
| 100 | QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | |
| 101 | QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); |
| 102 | |
| 103 | pci_set_word(exp_cap + PCI_EXP_LNKSTA, |
| 104 | QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | |
| 105 | QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); |
| 106 | |
| 107 | /* We changed link status bits over time, and changing them across |
| 108 | * migrations is generally fine as hardware changes them too. |
| 109 | * Let's not bother checking. |
| 110 | */ |
| 111 | pci_set_word(cmask + PCI_EXP_LNKSTA, 0); |
| 112 | } |
| 113 | |
| 114 | /* Includes setting the target speed default */ |
| 115 | static void pcie_cap_fill_lnk(uint8_t *exp_cap, PCIExpLinkWidth width, |
| 116 | PCIExpLinkSpeed speed, bool flitmode) |
| 117 | { |
| 118 | /* Clear and fill LNKCAP from what was configured above */ |
| 119 | pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, |
| 120 | PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); |
| 121 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, |
| 122 | QEMU_PCI_EXP_LNKCAP_MLW(width) | |
| 123 | QEMU_PCI_EXP_LNKCAP_MLS(speed)); |
| 124 | |
| 125 | if (speed > QEMU_PCI_EXP_LNK_2_5GT) { |
| 126 | /* |
| 127 | * Target Link Speed defaults to the highest link speed supported by |
| 128 | * the component. 2.5GT/s devices are permitted to hardwire to zero. |
| 129 | */ |
| 130 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, |
| 131 | PCI_EXP_LNKCTL2_TLS); |
| 132 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, |
| 133 | QEMU_PCI_EXP_LNKCAP_MLS(speed) & |
| 134 | PCI_EXP_LNKCTL2_TLS); |
| 135 | } |
| 136 | |
| 137 | /* |
| 138 | * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is |
| 139 | * actually a reference to the highest bit supported in this register. |
| 140 | * We assume the device supports all link speeds. |
| 141 | */ |
| 142 | if (speed > QEMU_PCI_EXP_LNK_5GT) { |
| 143 | pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); |
| 144 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, |
| 145 | PCI_EXP_LNKCAP2_SLS_2_5GB | |
| 146 | PCI_EXP_LNKCAP2_SLS_5_0GB | |
| 147 | PCI_EXP_LNKCAP2_SLS_8_0GB); |
| 148 | if (speed > QEMU_PCI_EXP_LNK_8GT) { |
| 149 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, |
| 150 | PCI_EXP_LNKCAP2_SLS_16_0GB); |
| 151 | } |
| 152 | if (speed > QEMU_PCI_EXP_LNK_16GT) { |
| 153 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, |
| 154 | PCI_EXP_LNKCAP2_SLS_32_0GB); |
| 155 | } |
| 156 | if (speed > QEMU_PCI_EXP_LNK_32GT) { |
| 157 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, |
| 158 | PCI_EXP_LNKCAP2_SLS_64_0GB); |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | if (flitmode) { |
| 163 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA2, |
| 164 | PCI_EXP_LNKSTA2_FLIT); |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, |
| 169 | PCIExpLinkSpeed speed, bool flitmode) |
| 170 | { |
| 171 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 172 | |
| 173 | /* |
| 174 | * For an end point or USP need to set the current status as well |
| 175 | * as the capabilities. |
| 176 | */ |
| 177 | pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, |
| 178 | PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); |
| 179 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, |
| 180 | QEMU_PCI_EXP_LNKSTA_NLW(width) | |
| 181 | QEMU_PCI_EXP_LNKSTA_CLS(speed)); |
| 182 | |
| 183 | pcie_cap_fill_lnk(exp_cap, width, speed, flitmode); |
| 184 | } |
| 185 | |
| 186 | static void pcie_cap_fill_slot_lnk(PCIDevice *dev) |
| 187 | { |
| 188 | PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); |
| 189 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 190 | |
| 191 | /* Skip anything that isn't a PCIESlot */ |
| 192 | if (!s) { |
| 193 | return; |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Link bandwidth notification is required for all root ports and |
| 198 | * downstream ports supporting links wider than x1 or multiple link |
| 199 | * speeds. |
| 200 | */ |
| 201 | if (s->width > QEMU_PCI_EXP_LNK_X1 || |
| 202 | s->speed > QEMU_PCI_EXP_LNK_2_5GT) { |
| 203 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, |
| 204 | PCI_EXP_LNKCAP_LBNC); |
| 205 | } |
| 206 | |
| 207 | if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { |
| 208 | /* |
| 209 | * Hot-plug capable downstream ports and downstream ports supporting |
| 210 | * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC |
| 211 | * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which |
| 212 | * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also |
| 213 | * technically implement this, but it's not done here for compatibility. |
| 214 | */ |
| 215 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, |
| 216 | PCI_EXP_LNKCAP_DLLLARC); |
| 217 | /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ |
| 218 | } |
| 219 | |
| 220 | pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); |
| 221 | } |
| 222 | |
| 223 | int pcie_cap_init(PCIDevice *dev, uint8_t offset, |
| 224 | uint8_t type, uint8_t port, |
| 225 | Error **errp) |
| 226 | { |
| 227 | /* PCIe cap v2 init */ |
| 228 | int pos; |
| 229 | uint8_t *exp_cap; |
| 230 | |
| 231 | assert(pci_is_express(dev)); |
| 232 | |
| 233 | pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, |
| 234 | PCI_EXP_VER2_SIZEOF, errp); |
| 235 | if (pos < 0) { |
| 236 | return pos; |
| 237 | } |
| 238 | dev->exp.exp_cap = pos; |
| 239 | exp_cap = dev->config + pos; |
| 240 | |
| 241 | /* Filling values common with v1 */ |
| 242 | pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); |
| 243 | |
| 244 | /* Fill link speed and width options */ |
| 245 | pcie_cap_fill_slot_lnk(dev); |
| 246 | |
| 247 | /* Filling v2 specific values */ |
| 248 | pci_set_long(exp_cap + PCI_EXP_DEVCAP2, |
| 249 | PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); |
| 250 | |
| 251 | pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); |
| 252 | |
| 253 | /* read-only to behave like a 'NULL' Extended Capability Header */ |
| 254 | pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); |
| 255 | |
| 256 | return pos; |
| 257 | } |
| 258 | |
| 259 | int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, |
| 260 | uint8_t port) |
| 261 | { |
| 262 | /* PCIe cap v1 init */ |
| 263 | int pos; |
| 264 | Error *local_err = NULL; |
| 265 | |
| 266 | assert(pci_is_express(dev)); |
| 267 | |
| 268 | pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, |
| 269 | PCI_EXP_VER1_SIZEOF, &local_err); |
| 270 | if (pos < 0) { |
| 271 | error_report_err(local_err); |
| 272 | return pos; |
| 273 | } |
| 274 | dev->exp.exp_cap = pos; |
| 275 | |
| 276 | pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); |
| 277 | |
| 278 | return pos; |
| 279 | } |
| 280 | |
| 281 | static int |
| 282 | pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) |
| 283 | { |
| 284 | uint8_t type = PCI_EXP_TYPE_ENDPOINT; |
| 285 | Error *local_err = NULL; |
| 286 | int ret; |
| 287 | |
| 288 | /* |
| 289 | * Windows guests will report Code 10, device cannot start, if |
| 290 | * a regular Endpoint type is exposed on a root complex. These |
| 291 | * should instead be Root Complex Integrated Endpoints. |
| 292 | */ |
| 293 | if (pci_bus_is_express(pci_get_bus(dev)) |
| 294 | && pci_bus_is_root(pci_get_bus(dev))) { |
| 295 | type = PCI_EXP_TYPE_RC_END; |
| 296 | } |
| 297 | |
| 298 | if (cap_size == PCI_EXP_VER1_SIZEOF) { |
| 299 | return pcie_cap_v1_init(dev, offset, type, 0); |
| 300 | } else { |
| 301 | ret = pcie_cap_init(dev, offset, type, 0, &local_err); |
| 302 | |
| 303 | if (ret < 0) { |
| 304 | error_report_err(local_err); |
| 305 | } |
| 306 | |
| 307 | return ret; |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) |
| 312 | { |
| 313 | return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); |
| 314 | } |
| 315 | |
| 316 | int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) |
| 317 | { |
| 318 | return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); |
| 319 | } |
| 320 | |
| 321 | void pcie_cap_exit(PCIDevice *dev) |
| 322 | { |
| 323 | pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); |
| 324 | } |
| 325 | |
| 326 | void pcie_cap_v1_exit(PCIDevice *dev) |
| 327 | { |
| 328 | pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); |
| 329 | } |
| 330 | |
| 331 | uint8_t pcie_cap_get_type(const PCIDevice *dev) |
| 332 | { |
| 333 | uint32_t pos = dev->exp.exp_cap; |
| 334 | assert(pos > 0); |
| 335 | return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & |
| 336 | PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; |
| 337 | } |
| 338 | |
| 339 | uint8_t pcie_cap_get_version(const PCIDevice *dev) |
| 340 | { |
| 341 | uint32_t pos = dev->exp.exp_cap; |
| 342 | assert(pos > 0); |
| 343 | return pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_VERS; |
| 344 | } |
| 345 | |
| 346 | /* MSI/MSI-X */ |
| 347 | /* pci express interrupt message number */ |
| 348 | /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ |
| 349 | void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) |
| 350 | { |
| 351 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 352 | assert(vector < 32); |
| 353 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); |
| 354 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, |
| 355 | vector << PCI_EXP_FLAGS_IRQ_SHIFT); |
| 356 | } |
| 357 | |
| 358 | uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) |
| 359 | { |
| 360 | return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & |
| 361 | PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; |
| 362 | } |
| 363 | |
| 364 | void pcie_cap_deverr_init(PCIDevice *dev) |
| 365 | { |
| 366 | uint32_t pos = dev->exp.exp_cap; |
| 367 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, |
| 368 | PCI_EXP_DEVCAP_RBER); |
| 369 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, |
| 370 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | |
| 371 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); |
| 372 | pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, |
| 373 | PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | |
| 374 | PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); |
| 375 | } |
| 376 | |
| 377 | void pcie_cap_deverr_reset(PCIDevice *dev) |
| 378 | { |
| 379 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; |
| 380 | pci_long_test_and_clear_mask(devctl, |
| 381 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | |
| 382 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); |
| 383 | } |
| 384 | |
| 385 | void pcie_cap_lnkctl_init(PCIDevice *dev) |
| 386 | { |
| 387 | uint32_t pos = dev->exp.exp_cap; |
| 388 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, |
| 389 | PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); |
| 390 | } |
| 391 | |
| 392 | void pcie_cap_lnkctl_reset(PCIDevice *dev) |
| 393 | { |
| 394 | uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; |
| 395 | pci_long_test_and_clear_mask(lnkctl, |
| 396 | PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); |
| 397 | } |
| 398 | |
| 399 | static void hotplug_event_update_event_status(PCIDevice *dev) |
| 400 | { |
| 401 | uint32_t pos = dev->exp.exp_cap; |
| 402 | uint8_t *exp_cap = dev->config + pos; |
| 403 | uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
| 404 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
| 405 | |
| 406 | dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && |
| 407 | (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); |
| 408 | } |
| 409 | |
| 410 | static void hotplug_event_notify(PCIDevice *dev) |
| 411 | { |
| 412 | bool prev = dev->exp.hpev_notified; |
| 413 | |
| 414 | hotplug_event_update_event_status(dev); |
| 415 | |
| 416 | if (prev == dev->exp.hpev_notified) { |
| 417 | return; |
| 418 | } |
| 419 | |
| 420 | /* Note: the logic above does not take into account whether interrupts |
| 421 | * are masked. The result is that interrupt will be sent when it is |
| 422 | * subsequently unmasked. This appears to be legal: Section 6.7.3.4: |
| 423 | * The Port may optionally send an MSI when there are hot-plug events that |
| 424 | * occur while interrupt generation is disabled, and interrupt generation is |
| 425 | * subsequently enabled. */ |
| 426 | if (msix_enabled(dev)) { |
| 427 | msix_notify(dev, pcie_cap_flags_get_vector(dev)); |
| 428 | } else if (msi_enabled(dev)) { |
| 429 | msi_notify(dev, pcie_cap_flags_get_vector(dev)); |
| 430 | } else if (pci_intx(dev) != -1) { |
| 431 | pci_set_irq(dev, dev->exp.hpev_notified); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | static void hotplug_event_clear(PCIDevice *dev) |
| 436 | { |
| 437 | hotplug_event_update_event_status(dev); |
| 438 | if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 && |
| 439 | !dev->exp.hpev_notified) { |
| 440 | pci_irq_deassert(dev); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | void pcie_cap_slot_enable_power(PCIDevice *dev) |
| 445 | { |
| 446 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 447 | uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); |
| 448 | |
| 449 | if (sltcap & PCI_EXP_SLTCAP_PCP) { |
| 450 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
| 451 | PCI_EXP_SLTCTL_PCC); |
| 452 | } |
| 453 | } |
| 454 | |
| 455 | static void pcie_set_power_device(PCIBus *bus, PCIDevice *dev, void *opaque) |
| 456 | { |
| 457 | bool *power = opaque; |
| 458 | |
| 459 | pci_set_power(dev, *power); |
| 460 | } |
| 461 | |
| 462 | static void pcie_cap_update_power(PCIDevice *hotplug_dev) |
| 463 | { |
| 464 | uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; |
| 465 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(hotplug_dev)); |
| 466 | uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); |
| 467 | uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
| 468 | bool power = true; |
| 469 | |
| 470 | if (sltcap & PCI_EXP_SLTCAP_PCP) { |
| 471 | power = (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_ON; |
| 472 | /* Don't we need to check also (sltctl & PCI_EXP_SLTCTL_PIC) ? */ |
| 473 | } |
| 474 | |
| 475 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), |
| 476 | pcie_set_power_device, &power); |
| 477 | } |
| 478 | |
| 479 | /* |
| 480 | * A PCI Express Hot-Plug Event has occurred, so update slot status register |
| 481 | * and notify OS of the event if necessary. |
| 482 | * |
| 483 | * 6.7.3 PCI Express Hot-Plug Events |
| 484 | * 6.7.3.4 Software Notification of Hot-Plug Events |
| 485 | */ |
| 486 | static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) |
| 487 | { |
| 488 | /* Minor optimization: if nothing changed - no event is needed. */ |
| 489 | if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + |
| 490 | PCI_EXP_SLTSTA, event) == event) { |
| 491 | return; |
| 492 | } |
| 493 | hotplug_event_notify(dev); |
| 494 | } |
| 495 | |
| 496 | static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, |
| 497 | Error **errp) |
| 498 | { |
| 499 | uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; |
| 500 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
| 501 | |
| 502 | PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); |
| 503 | if (sltsta & PCI_EXP_SLTSTA_EIS) { |
| 504 | /* the slot is electromechanically locked. |
| 505 | * This error is propagated up to qdev and then to HMP/QMP. |
| 506 | */ |
| 507 | error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 512 | Error **errp) |
| 513 | { |
| 514 | PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); |
| 515 | uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; |
| 516 | uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); |
| 517 | |
| 518 | /* Check if hot-plug is disabled on the slot */ |
| 519 | if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { |
| 520 | error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", |
| 521 | DEVICE(hotplug_pdev)->id); |
| 522 | return; |
| 523 | } |
| 524 | |
| 525 | pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); |
| 526 | } |
| 527 | |
| 528 | void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 529 | Error **errp) |
| 530 | { |
| 531 | PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); |
| 532 | uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; |
| 533 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
| 534 | uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); |
| 535 | |
| 536 | if (pci_is_vf(pci_dev)) { |
| 537 | /* Virtual function cannot be physically disconnected */ |
| 538 | return; |
| 539 | } |
| 540 | |
| 541 | /* Don't send event when device is enabled during qemu machine creation: |
| 542 | * it is present on boot, no hotplug event is necessary. We do send an |
| 543 | * event when the device is disabled later. */ |
| 544 | if (!dev->hotplugged) { |
| 545 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
| 546 | PCI_EXP_SLTSTA_PDS); |
| 547 | if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || |
| 548 | (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { |
| 549 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, |
| 550 | PCI_EXP_LNKSTA_DLLLA); |
| 551 | } |
| 552 | pcie_cap_update_power(hotplug_pdev); |
| 553 | return; |
| 554 | } |
| 555 | |
| 556 | /* To enable multifunction hot-plug, we just ensure the function |
| 557 | * 0 added last. When function 0 is added, we set the sltsta and |
| 558 | * inform OS via event notification. |
| 559 | */ |
| 560 | if (pci_get_function_0(pci_dev)) { |
| 561 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
| 562 | PCI_EXP_SLTSTA_PDS); |
| 563 | if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || |
| 564 | (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { |
| 565 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, |
| 566 | PCI_EXP_LNKSTA_DLLLA); |
| 567 | } |
| 568 | pcie_cap_slot_event(hotplug_pdev, |
| 569 | PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); |
| 570 | pcie_cap_update_power(hotplug_pdev); |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 575 | Error **errp) |
| 576 | { |
| 577 | qdev_unrealize(dev); |
| 578 | } |
| 579 | |
| 580 | static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) |
| 581 | { |
| 582 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); |
| 583 | |
| 584 | if (dev->partially_hotplugged) { |
| 585 | dev->qdev.pending_deleted_event = false; |
| 586 | return; |
| 587 | } |
| 588 | hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); |
| 589 | object_unparent(OBJECT(dev)); |
| 590 | } |
| 591 | |
| 592 | static void pcie_cap_slot_do_unplug(PCIDevice *dev) |
| 593 | { |
| 594 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); |
| 595 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 596 | uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); |
| 597 | |
| 598 | pci_for_each_device_under_bus(sec_bus, pcie_unplug_device, NULL); |
| 599 | |
| 600 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
| 601 | PCI_EXP_SLTSTA_PDS); |
| 602 | if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || |
| 603 | (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { |
| 604 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, |
| 605 | PCI_EXP_LNKSTA_DLLLA); |
| 606 | } |
| 607 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
| 608 | PCI_EXP_SLTSTA_PDC); |
| 609 | } |
| 610 | |
| 611 | void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, |
| 612 | DeviceState *dev, Error **errp) |
| 613 | { |
| 614 | Error *local_err = NULL; |
| 615 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
| 616 | PCIBus *bus = pci_get_bus(pci_dev); |
| 617 | PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); |
| 618 | uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; |
| 619 | uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); |
| 620 | uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
| 621 | |
| 622 | /* Check if hot-unplug is disabled on the slot */ |
| 623 | if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) { |
| 624 | error_setg(errp, "Hot-unplug failed: " |
| 625 | "unsupported by the port device '%s'", |
| 626 | DEVICE(hotplug_pdev)->id); |
| 627 | return; |
| 628 | } |
| 629 | |
| 630 | pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err); |
| 631 | if (local_err) { |
| 632 | error_propagate(errp, local_err); |
| 633 | return; |
| 634 | } |
| 635 | |
| 636 | if ((sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_BLINK) { |
| 637 | error_setg(errp, "Hot-unplug failed: " |
| 638 | "guest is busy (power indicator blinking)"); |
| 639 | return; |
| 640 | } |
| 641 | |
| 642 | dev->pending_deleted_event = true; |
| 643 | dev->pending_deleted_expires_ms = |
| 644 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 5000; /* 5 secs */ |
| 645 | |
| 646 | /* In case user cancel the operation of multi-function hot-add, |
| 647 | * remove the function that is unexposed to guest individually, |
| 648 | * without interaction with guest. |
| 649 | */ |
| 650 | if (pci_dev->devfn && |
| 651 | !bus->devices[0]) { |
| 652 | pcie_unplug_device(bus, pci_dev, NULL); |
| 653 | |
| 654 | return; |
| 655 | } |
| 656 | |
| 657 | if (pcie_sltctl_powered_off(sltctl)) { |
| 658 | /* slot is powered off -> unplug without round-trip to the guest */ |
| 659 | pcie_cap_slot_do_unplug(hotplug_pdev); |
| 660 | hotplug_event_notify(hotplug_pdev); |
| 661 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
| 662 | PCI_EXP_SLTSTA_ABP); |
| 663 | return; |
| 664 | } |
| 665 | |
| 666 | pcie_cap_slot_push_attention_button(hotplug_pdev); |
| 667 | } |
| 668 | |
| 669 | /* pci express slot for pci express root/downstream port |
| 670 | PCI express capability slot registers */ |
| 671 | void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) |
| 672 | { |
| 673 | uint32_t pos = dev->exp.exp_cap; |
| 674 | |
| 675 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, |
| 676 | PCI_EXP_FLAGS_SLOT); |
| 677 | |
| 678 | pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, |
| 679 | ~PCI_EXP_SLTCAP_PSN); |
| 680 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, |
| 681 | (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | |
| 682 | PCI_EXP_SLTCAP_EIP | |
| 683 | PCI_EXP_SLTCAP_PIP | |
| 684 | PCI_EXP_SLTCAP_AIP | |
| 685 | PCI_EXP_SLTCAP_ABP); |
| 686 | |
| 687 | /* |
| 688 | * Expose native hot-plug on all bridges if hot-plug is enabled on the slot. |
| 689 | * (unless broken 6.1 ABI is enforced for compat reasons) |
| 690 | */ |
| 691 | if (s->hotplug && |
| 692 | (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) { |
| 693 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, |
| 694 | PCI_EXP_SLTCAP_HPS | |
| 695 | PCI_EXP_SLTCAP_HPC); |
| 696 | } |
| 697 | |
| 698 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
| 699 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, |
| 700 | PCI_EXP_SLTCAP_PCP); |
| 701 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, |
| 702 | PCI_EXP_SLTCTL_PCC); |
| 703 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, |
| 704 | PCI_EXP_SLTCTL_PCC); |
| 705 | } |
| 706 | |
| 707 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, |
| 708 | PCI_EXP_SLTCTL_PIC | |
| 709 | PCI_EXP_SLTCTL_AIC); |
| 710 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, |
| 711 | PCI_EXP_SLTCTL_PWR_IND_OFF | |
| 712 | PCI_EXP_SLTCTL_ATTN_IND_OFF); |
| 713 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, |
| 714 | PCI_EXP_SLTCTL_PIC | |
| 715 | PCI_EXP_SLTCTL_AIC | |
| 716 | PCI_EXP_SLTCTL_HPIE | |
| 717 | PCI_EXP_SLTCTL_CCIE | |
| 718 | PCI_EXP_SLTCTL_PDCE | |
| 719 | PCI_EXP_SLTCTL_ABPE); |
| 720 | /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, |
| 721 | * make the bit writable here in order to detect 1b is written. |
| 722 | * pcie_cap_slot_write_config() test-and-clear the bit, so |
| 723 | * this bit always returns 0 to the guest. |
| 724 | */ |
| 725 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, |
| 726 | PCI_EXP_SLTCTL_EIC); |
| 727 | |
| 728 | pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, |
| 729 | PCI_EXP_HP_EV_SUPPORTED); |
| 730 | |
| 731 | /* Avoid migration abortion when this device hot-removed by guest */ |
| 732 | pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA, |
| 733 | PCI_EXP_SLTSTA_PDS); |
| 734 | |
| 735 | dev->exp.hpev_notified = false; |
| 736 | |
| 737 | qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), |
| 738 | OBJECT(dev)); |
| 739 | } |
| 740 | |
| 741 | void pcie_cap_slot_reset(PCIDevice *dev) |
| 742 | { |
| 743 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
| 744 | uint8_t port_type = pcie_cap_get_type(dev); |
| 745 | |
| 746 | assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || |
| 747 | port_type == PCI_EXP_TYPE_ROOT_PORT); |
| 748 | |
| 749 | PCIE_DEV_PRINTF(dev, "reset\n"); |
| 750 | |
| 751 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
| 752 | PCI_EXP_SLTCTL_EIC | |
| 753 | PCI_EXP_SLTCTL_PIC | |
| 754 | PCI_EXP_SLTCTL_AIC | |
| 755 | PCI_EXP_SLTCTL_HPIE | |
| 756 | PCI_EXP_SLTCTL_CCIE | |
| 757 | PCI_EXP_SLTCTL_PDCE | |
| 758 | PCI_EXP_SLTCTL_ABPE); |
| 759 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, |
| 760 | PCI_EXP_SLTCTL_PWR_IND_OFF | |
| 761 | PCI_EXP_SLTCTL_ATTN_IND_OFF); |
| 762 | |
| 763 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
| 764 | /* Downstream ports enforce device number 0. */ |
| 765 | bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; |
| 766 | uint16_t pic; |
| 767 | |
| 768 | if (populated) { |
| 769 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
| 770 | PCI_EXP_SLTCTL_PCC); |
| 771 | } else { |
| 772 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, |
| 773 | PCI_EXP_SLTCTL_PCC); |
| 774 | } |
| 775 | |
| 776 | pic = populated ? |
| 777 | PCI_EXP_SLTCTL_PWR_IND_ON : PCI_EXP_SLTCTL_PWR_IND_OFF; |
| 778 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); |
| 779 | } |
| 780 | |
| 781 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
| 782 | PCI_EXP_SLTSTA_EIS |/* on reset, |
| 783 | the lock is released */ |
| 784 | PCI_EXP_SLTSTA_CC | |
| 785 | PCI_EXP_SLTSTA_PDC | |
| 786 | PCI_EXP_SLTSTA_ABP); |
| 787 | |
| 788 | pcie_cap_update_power(dev); |
| 789 | hotplug_event_update_event_status(dev); |
| 790 | } |
| 791 | |
| 792 | void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta) |
| 793 | { |
| 794 | uint32_t pos = dev->exp.exp_cap; |
| 795 | uint8_t *exp_cap = dev->config + pos; |
| 796 | *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
| 797 | *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
| 798 | } |
| 799 | |
| 800 | static void find_child_fn(PCIBus *bus, PCIDevice *dev, void *opaque) |
| 801 | { |
| 802 | PCIDevice **child = opaque; |
| 803 | |
| 804 | if (!*child) { |
| 805 | *child = dev; |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | /* |
| 810 | * Returns the plugged device or first function of multifunction plugged device |
| 811 | */ |
| 812 | static PCIDevice *pcie_cap_slot_find_child(PCIDevice *dev) |
| 813 | { |
| 814 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); |
| 815 | PCIDevice *child = NULL; |
| 816 | |
| 817 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), find_child_fn, &child); |
| 818 | |
| 819 | return child; |
| 820 | } |
| 821 | |
| 822 | void pcie_cap_slot_write_config(PCIDevice *dev, |
| 823 | uint16_t old_slt_ctl, uint16_t old_slt_sta, |
| 824 | uint32_t addr, uint32_t val, int len) |
| 825 | { |
| 826 | uint32_t pos = dev->exp.exp_cap; |
| 827 | uint8_t *exp_cap = dev->config + pos; |
| 828 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
| 829 | |
| 830 | if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { |
| 831 | /* |
| 832 | * Guests tend to clears all bits during init. |
| 833 | * If they clear bits that weren't set this is racy and will lose events: |
| 834 | * not a big problem for manual button presses, but a problem for us. |
| 835 | * As a work-around, detect this and revert status to what it was |
| 836 | * before the write. |
| 837 | * |
| 838 | * Note: in theory this can be detected as a duplicate button press |
| 839 | * which cancels the previous press. Does not seem to happen in |
| 840 | * practice as guests seem to only have this bug during init. |
| 841 | */ |
| 842 | #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \ |
| 843 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \ |
| 844 | PCI_EXP_SLTSTA_CC) |
| 845 | |
| 846 | if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) { |
| 847 | sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS); |
| 848 | pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); |
| 849 | } |
| 850 | hotplug_event_clear(dev); |
| 851 | } |
| 852 | |
| 853 | if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { |
| 854 | return; |
| 855 | } |
| 856 | |
| 857 | if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
| 858 | PCI_EXP_SLTCTL_EIC)) { |
| 859 | sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ |
| 860 | pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); |
| 861 | PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " |
| 862 | "sltsta -> 0x%02"PRIx16"\n", |
| 863 | sltsta); |
| 864 | } |
| 865 | |
| 866 | if (trace_event_get_state_backends(TRACE_PCIE_CAP_SLOT_WRITE_CONFIG)) { |
| 867 | DeviceState *parent = DEVICE(dev); |
| 868 | DeviceState *child = DEVICE(pcie_cap_slot_find_child(dev)); |
| 869 | |
| 870 | trace_pcie_cap_slot_write_config( |
| 871 | parent->canonical_path, |
| 872 | child ? child->canonical_path : "no-child", |
| 873 | (sltsta & PCI_EXP_SLTSTA_PDS) ? "present" : "not present", |
| 874 | pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_PIC), |
| 875 | pcie_led_state_to_str(val & PCI_EXP_SLTCTL_PIC), |
| 876 | pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_AIC), |
| 877 | pcie_led_state_to_str(val & PCI_EXP_SLTCTL_AIC), |
| 878 | (old_slt_ctl & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on", |
| 879 | (val & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on"); |
| 880 | } |
| 881 | |
| 882 | /* |
| 883 | * If the slot is populated, power indicator is off and power |
| 884 | * controller is off, it is safe to detach the devices. |
| 885 | * |
| 886 | * Note: don't detach if condition was already true: |
| 887 | * this is a work around for guests that overwrite |
| 888 | * control of powered off slots before powering them on. |
| 889 | */ |
| 890 | if ((sltsta & PCI_EXP_SLTSTA_PDS) && pcie_sltctl_powered_off(val) && |
| 891 | !pcie_sltctl_powered_off(old_slt_ctl)) |
| 892 | { |
| 893 | pcie_cap_slot_do_unplug(dev); |
| 894 | } |
| 895 | pcie_cap_update_power(dev); |
| 896 | |
| 897 | hotplug_event_notify(dev); |
| 898 | |
| 899 | /* |
| 900 | * 6.7.3.2 Command Completed Events |
| 901 | * |
| 902 | * Software issues a command to a hot-plug capable Downstream Port by |
| 903 | * issuing a write transaction that targets any portion of the Port’s Slot |
| 904 | * Control register. A single write to the Slot Control register is |
| 905 | * considered to be a single command, even if the write affects more than |
| 906 | * one field in the Slot Control register. In response to this transaction, |
| 907 | * the Port must carry out the requested actions and then set the |
| 908 | * associated status field for the command completed event. */ |
| 909 | |
| 910 | /* Real hardware might take a while to complete requested command because |
| 911 | * physical movement would be involved like locking the electromechanical |
| 912 | * lock. However in our case, command is completed instantaneously above, |
| 913 | * so send a command completion event right now. |
| 914 | */ |
| 915 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); |
| 916 | } |
| 917 | |
| 918 | int pcie_cap_slot_post_load(void *opaque, int version_id) |
| 919 | { |
| 920 | PCIDevice *dev = opaque; |
| 921 | hotplug_event_update_event_status(dev); |
| 922 | pcie_cap_update_power(dev); |
| 923 | return 0; |
| 924 | } |
| 925 | |
| 926 | void pcie_cap_slot_push_attention_button(PCIDevice *dev) |
| 927 | { |
| 928 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); |
| 929 | } |
| 930 | |
| 931 | /* root control/capabilities/status. PME isn't emulated for now */ |
| 932 | void pcie_cap_root_init(PCIDevice *dev) |
| 933 | { |
| 934 | pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, |
| 935 | PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | |
| 936 | PCI_EXP_RTCTL_SEFEE); |
| 937 | } |
| 938 | |
| 939 | void pcie_cap_root_reset(PCIDevice *dev) |
| 940 | { |
| 941 | pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); |
| 942 | } |
| 943 | |
| 944 | /* function level reset(FLR) */ |
| 945 | void pcie_cap_flr_init(PCIDevice *dev) |
| 946 | { |
| 947 | pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, |
| 948 | PCI_EXP_DEVCAP_FLR); |
| 949 | |
| 950 | /* Although reading BCR_FLR returns always 0, |
| 951 | * the bit is made writable here in order to detect the 1b is written |
| 952 | * pcie_cap_flr_write_config() test-and-clear the bit, so |
| 953 | * this bit always returns 0 to the guest. |
| 954 | */ |
| 955 | pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, |
| 956 | PCI_EXP_DEVCTL_BCR_FLR); |
| 957 | } |
| 958 | |
| 959 | void pcie_cap_flr_write_config(PCIDevice *dev, |
| 960 | uint32_t addr, uint32_t val, int len) |
| 961 | { |
| 962 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; |
| 963 | if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { |
| 964 | /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler |
| 965 | so the handler can detect FLR by looking at this bit. */ |
| 966 | pci_device_reset(dev); |
| 967 | pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | /* Alternative Routing-ID Interpretation (ARI) |
| 972 | * forwarding support for root and downstream ports |
| 973 | */ |
| 974 | void pcie_cap_arifwd_init(PCIDevice *dev) |
| 975 | { |
| 976 | uint32_t pos = dev->exp.exp_cap; |
| 977 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, |
| 978 | PCI_EXP_DEVCAP2_ARI); |
| 979 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, |
| 980 | PCI_EXP_DEVCTL2_ARI); |
| 981 | } |
| 982 | |
| 983 | void pcie_cap_arifwd_reset(PCIDevice *dev) |
| 984 | { |
| 985 | uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; |
| 986 | pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); |
| 987 | } |
| 988 | |
| 989 | bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) |
| 990 | { |
| 991 | if (!pci_is_express(dev)) { |
| 992 | return false; |
| 993 | } |
| 994 | if (!dev->exp.exp_cap) { |
| 995 | return false; |
| 996 | } |
| 997 | |
| 998 | return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & |
| 999 | PCI_EXP_DEVCTL2_ARI; |
| 1000 | } |
| 1001 | |
| 1002 | /************************************************************************** |
| 1003 | * pci express extended capability list management functions |
| 1004 | * uint16_t ext_cap_id (16 bit) |
| 1005 | * uint8_t cap_ver (4 bit) |
| 1006 | * uint16_t cap_offset (12 bit) |
| 1007 | * uint16_t ext_cap_size |
| 1008 | */ |
| 1009 | |
| 1010 | /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ |
| 1011 | static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, |
| 1012 | uint16_t *prev_p) |
| 1013 | { |
| 1014 | uint16_t prev = 0; |
| 1015 | uint16_t next; |
| 1016 | uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); |
| 1017 | |
| 1018 | if (!header) { |
| 1019 | /* no extended capability */ |
| 1020 | next = 0; |
| 1021 | goto out; |
| 1022 | } |
| 1023 | for (next = PCI_CONFIG_SPACE_SIZE; next; |
| 1024 | prev = next, next = PCI_EXT_CAP_NEXT(header)) { |
| 1025 | |
| 1026 | assert(next >= PCI_CONFIG_SPACE_SIZE); |
| 1027 | assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); |
| 1028 | |
| 1029 | header = pci_get_long(dev->config + next); |
| 1030 | if (PCI_EXT_CAP_ID(header) == cap_id) { |
| 1031 | break; |
| 1032 | } |
| 1033 | } |
| 1034 | |
| 1035 | out: |
| 1036 | if (prev_p) { |
| 1037 | *prev_p = prev; |
| 1038 | } |
| 1039 | return next; |
| 1040 | } |
| 1041 | |
| 1042 | uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) |
| 1043 | { |
| 1044 | return pcie_find_capability_list(dev, cap_id, NULL); |
| 1045 | } |
| 1046 | |
| 1047 | static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) |
| 1048 | { |
| 1049 | uint32_t header = pci_get_long(dev->config + pos); |
| 1050 | assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); |
| 1051 | header = (header & ~PCI_EXT_CAP_NEXT_MASK) | |
| 1052 | ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); |
| 1053 | pci_set_long(dev->config + pos, header); |
| 1054 | } |
| 1055 | |
| 1056 | /* |
| 1057 | * Insert a PCIe extended capability at a given offset. |
| 1058 | * |
| 1059 | * This helper only validates that the insertion does not overwrite an |
| 1060 | * existing PCIe extended capability header, as corrupting a header would |
| 1061 | * break the extended capability linked list. |
| 1062 | * |
| 1063 | * The caller must ensure that (offset, size) does not overlap with other |
| 1064 | * registers or capability-specific register blocks. Overlaps with |
| 1065 | * capability-specific registers are not checked and are considered a |
| 1066 | * user-controlled override. |
| 1067 | * |
| 1068 | * Note: Best effort helper. The PCIe spec does not require extended |
| 1069 | * capabilities to be ordered, but most devices use a forward-linked list. |
| 1070 | * Devices that do not consistently use a forward-linked list may cause |
| 1071 | * insertion to fail. |
| 1072 | */ |
| 1073 | bool pcie_insert_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, |
| 1074 | uint16_t offset, uint16_t size) |
| 1075 | { |
| 1076 | uint16_t pos = PCI_CONFIG_SPACE_SIZE, prev = 0; |
| 1077 | uint32_t header; |
| 1078 | |
| 1079 | assert(pci_is_express(dev)); |
| 1080 | |
| 1081 | if (!QEMU_IS_ALIGNED(offset, PCI_EXT_CAP_ALIGN) || |
| 1082 | size < 8 || |
| 1083 | offset < PCI_CONFIG_SPACE_SIZE || |
| 1084 | offset >= PCIE_CONFIG_SPACE_SIZE || |
| 1085 | offset + size > PCIE_CONFIG_SPACE_SIZE) { |
| 1086 | return false; |
| 1087 | } |
| 1088 | |
| 1089 | header = pci_get_long(dev->config + pos); |
| 1090 | if (!header) { |
| 1091 | /* No extended capability present, insertion must be at the ECAP head */ |
| 1092 | if (offset != pos) { |
| 1093 | return false; |
| 1094 | } |
| 1095 | pci_set_long(dev->config + pos, PCI_EXT_CAP(cap_id, cap_ver, 0)); |
| 1096 | goto out; |
| 1097 | } |
| 1098 | |
| 1099 | while (header && pos && offset >= pos) { |
| 1100 | uint16_t next = PCI_EXT_CAP_NEXT(header); |
| 1101 | |
| 1102 | /* Reject insertion inside an existing ECAP header (4 bytes) */ |
| 1103 | if (offset < pos + PCI_EXT_CAP_ALIGN) { |
| 1104 | return false; |
| 1105 | } |
| 1106 | |
| 1107 | prev = pos; |
| 1108 | pos = next; |
| 1109 | header = pos ? pci_get_long(dev->config + pos) : 0; |
| 1110 | } |
| 1111 | |
| 1112 | pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, pos)); |
| 1113 | if (prev) { |
| 1114 | pcie_ext_cap_set_next(dev, prev, offset); |
| 1115 | } |
| 1116 | |
| 1117 | out: |
| 1118 | /* Make capability read-only by default */ |
| 1119 | memset(dev->wmask + offset, 0, size); |
| 1120 | memset(dev->w1cmask + offset, 0, size); |
| 1121 | /* Check capability by default */ |
| 1122 | memset(dev->cmask + offset, 0xFF, size); |
| 1123 | return true; |
| 1124 | } |
| 1125 | /* |
| 1126 | * Caller must supply valid (offset, size) such that the range wouldn't |
| 1127 | * overlap with other capability or other registers. |
| 1128 | * This function doesn't check it. |
| 1129 | */ |
| 1130 | void pcie_add_capability(PCIDevice *dev, |
| 1131 | uint16_t cap_id, uint8_t cap_ver, |
| 1132 | uint16_t offset, uint16_t size) |
| 1133 | { |
| 1134 | assert(offset >= PCI_CONFIG_SPACE_SIZE); |
| 1135 | assert(offset < (uint16_t)(offset + size)); |
| 1136 | assert((uint16_t)(offset + size) <= PCIE_CONFIG_SPACE_SIZE); |
| 1137 | assert(size >= 8); |
| 1138 | assert(pci_is_express(dev)); |
| 1139 | |
| 1140 | if (offset != PCI_CONFIG_SPACE_SIZE) { |
| 1141 | uint16_t prev; |
| 1142 | |
| 1143 | /* |
| 1144 | * 0xffffffff is not a valid cap id (it's a 16 bit field). use |
| 1145 | * internally to find the last capability in the linked list. |
| 1146 | */ |
| 1147 | pcie_find_capability_list(dev, 0xffffffff, &prev); |
| 1148 | assert(prev >= PCI_CONFIG_SPACE_SIZE); |
| 1149 | pcie_ext_cap_set_next(dev, prev, offset); |
| 1150 | } |
| 1151 | pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); |
| 1152 | |
| 1153 | /* Make capability read-only by default */ |
| 1154 | memset(dev->wmask + offset, 0, size); |
| 1155 | memset(dev->w1cmask + offset, 0, size); |
| 1156 | /* Check capability by default */ |
| 1157 | memset(dev->cmask + offset, 0xFF, size); |
| 1158 | } |
| 1159 | |
| 1160 | /* |
| 1161 | * Sync the PCIe Link Status negotiated speed and width of a bridge with the |
| 1162 | * downstream device. If downstream device is not present, re-write with the |
| 1163 | * Link Capability fields. If downstream device reports invalid width or |
| 1164 | * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such |
| 1165 | * values interfere with PCIe native hotplug detecting new devices). Limit |
| 1166 | * width and speed to bridge capabilities for compatibility. Use config_read |
| 1167 | * to access the downstream device since it could be an assigned device with |
| 1168 | * volatile link information. |
| 1169 | */ |
| 1170 | void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) |
| 1171 | { |
| 1172 | PCIBridge *br = PCI_BRIDGE(bridge_dev); |
| 1173 | PCIBus *bus = pci_bridge_get_sec_bus(br); |
| 1174 | PCIDevice *target = bus->devices[0]; |
| 1175 | uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; |
| 1176 | uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP); |
| 1177 | |
| 1178 | if (!target || !target->exp.exp_cap) { |
| 1179 | lnksta = lnkcap; |
| 1180 | } else { |
| 1181 | uint16_t lnksta2; |
| 1182 | |
| 1183 | lnksta = target->config_read(target, |
| 1184 | target->exp.exp_cap + PCI_EXP_LNKSTA, |
| 1185 | sizeof(lnksta)); |
| 1186 | |
| 1187 | if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) { |
| 1188 | lnksta &= ~PCI_EXP_LNKSTA_NLW; |
| 1189 | lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW; |
| 1190 | } |
| 1191 | |
| 1192 | if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) { |
| 1193 | lnksta &= ~PCI_EXP_LNKSTA_CLS; |
| 1194 | lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS; |
| 1195 | } |
| 1196 | |
| 1197 | lnksta2 = target->config_read(target, |
| 1198 | target->exp.exp_cap + PCI_EXP_LNKSTA2, |
| 1199 | sizeof(lnksta2)); |
| 1200 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA2, |
| 1201 | PCI_EXP_LNKSTA2_FLIT); |
| 1202 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA2, |
| 1203 | lnksta2 & PCI_EXP_LNKSTA2_FLIT); |
| 1204 | } |
| 1205 | |
| 1206 | if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { |
| 1207 | lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1); |
| 1208 | } |
| 1209 | |
| 1210 | if (!(lnksta & PCI_EXP_LNKSTA_CLS)) { |
| 1211 | lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT); |
| 1212 | } |
| 1213 | |
| 1214 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, |
| 1215 | PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); |
| 1216 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & |
| 1217 | (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); |
| 1218 | } |
| 1219 | |
| 1220 | /************************************************************************** |
| 1221 | * pci express extended capability helper functions |
| 1222 | */ |
| 1223 | |
| 1224 | /* ARI */ |
| 1225 | void pcie_ari_init(PCIDevice *dev, uint16_t offset) |
| 1226 | { |
| 1227 | uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; |
| 1228 | |
| 1229 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, |
| 1230 | offset, PCI_ARI_SIZEOF); |
| 1231 | pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); |
| 1232 | } |
| 1233 | |
| 1234 | void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) |
| 1235 | { |
| 1236 | static const int pci_dsn_ver = 1; |
| 1237 | static const int pci_dsn_cap = 4; |
| 1238 | |
| 1239 | pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, |
| 1240 | PCI_EXT_CAP_DSN_SIZEOF); |
| 1241 | pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); |
| 1242 | } |
| 1243 | |
| 1244 | void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned) |
| 1245 | { |
| 1246 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, |
| 1247 | offset, PCI_EXT_CAP_ATS_SIZEOF); |
| 1248 | |
| 1249 | dev->exp.ats_cap = offset; |
| 1250 | |
| 1251 | /* Invalidate Queue Depth 0 */ |
| 1252 | if (aligned) { |
| 1253 | pci_set_word(dev->config + offset + PCI_ATS_CAP, |
| 1254 | PCI_ATS_CAP_PAGE_ALIGNED); |
| 1255 | } |
| 1256 | /* STU 0, Disabled by default */ |
| 1257 | pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); |
| 1258 | |
| 1259 | pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); |
| 1260 | } |
| 1261 | |
| 1262 | /* ACS (Access Control Services) */ |
| 1263 | void pcie_acs_init(PCIDevice *dev, uint16_t offset) |
| 1264 | { |
| 1265 | bool is_downstream = pci_is_express_downstream_port(dev); |
| 1266 | uint16_t cap_bits = 0; |
| 1267 | |
| 1268 | /* For endpoints, only multifunction devs may have an ACS capability: */ |
| 1269 | assert(is_downstream || |
| 1270 | (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || |
| 1271 | PCI_FUNC(dev->devfn)); |
| 1272 | |
| 1273 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, |
| 1274 | PCI_ACS_SIZEOF); |
| 1275 | dev->exp.acs_cap = offset; |
| 1276 | |
| 1277 | if (is_downstream) { |
| 1278 | /* |
| 1279 | * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with |
| 1280 | * caveats on the latter four that we ignore for simplicity). |
| 1281 | * Endpoints may also implement a subset of ACS capabilities, |
| 1282 | * but these are optional if the endpoint does not support |
| 1283 | * peer-to-peer between functions and thus omitted here. |
| 1284 | */ |
| 1285 | cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | |
| 1286 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; |
| 1287 | } |
| 1288 | |
| 1289 | pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); |
| 1290 | pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); |
| 1291 | } |
| 1292 | |
| 1293 | void pcie_acs_reset(PCIDevice *dev) |
| 1294 | { |
| 1295 | if (dev->exp.acs_cap) { |
| 1296 | pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); |
| 1297 | } |
| 1298 | } |
| 1299 | |
| 1300 | void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, |
| 1301 | uint8_t pasid_width, bool exec_perm, bool priv_mod) |
| 1302 | { |
| 1303 | static const uint16_t control_reg_rw_mask = 0x07; |
| 1304 | uint16_t capability_reg; |
| 1305 | |
| 1306 | assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH); |
| 1307 | capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT; |
| 1308 | capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0; |
| 1309 | capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0; |
| 1310 | pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg); |
| 1311 | |
| 1312 | /* Everything is disabled by default */ |
| 1313 | pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0); |
| 1314 | |
| 1315 | pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask); |
| 1316 | |
| 1317 | dev->exp.pasid_cap = offset; |
| 1318 | |
| 1319 | } |
| 1320 | |
| 1321 | /* PASID */ |
| 1322 | void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, |
| 1323 | bool exec_perm, bool priv_mod) |
| 1324 | { |
| 1325 | pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, |
| 1326 | PCI_EXT_CAP_PASID_SIZEOF); |
| 1327 | pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod); |
| 1328 | } |
| 1329 | |
| 1330 | /* PRI */ |
| 1331 | void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap, |
| 1332 | bool prg_response_pasid_req) |
| 1333 | { |
| 1334 | static const uint16_t control_reg_rw_mask = 0x3; |
| 1335 | static const uint16_t status_reg_rw1_mask = 0x3; |
| 1336 | static const uint32_t pr_alloc_reg_rw_mask = 0xffffffff; |
| 1337 | uint16_t status_reg; |
| 1338 | |
| 1339 | status_reg = prg_response_pasid_req ? PCI_PRI_STATUS_PASID : 0; |
| 1340 | status_reg |= PCI_PRI_STATUS_STOPPED; /* Stopped by default */ |
| 1341 | |
| 1342 | pcie_add_capability(dev, PCI_EXT_CAP_ID_PRI, PCI_PRI_VER, offset, |
| 1343 | PCI_EXT_CAP_PRI_SIZEOF); |
| 1344 | /* Disabled by default */ |
| 1345 | |
| 1346 | pci_set_word(dev->config + offset + PCI_PRI_STATUS, status_reg); |
| 1347 | pci_set_long(dev->config + offset + PCI_PRI_MAX_REQ, outstanding_pr_cap); |
| 1348 | |
| 1349 | pci_set_word(dev->wmask + offset + PCI_PRI_CTRL, control_reg_rw_mask); |
| 1350 | pci_set_word(dev->w1cmask + offset + PCI_PRI_STATUS, status_reg_rw1_mask); |
| 1351 | pci_set_long(dev->wmask + offset + PCI_PRI_ALLOC_REQ, pr_alloc_reg_rw_mask); |
| 1352 | |
| 1353 | dev->exp.pri_cap = offset; |
| 1354 | } |
| 1355 | |
| 1356 | static inline bool pcie_pasid_check_ctrl_bit_enabled(const PCIDevice *dev, |
| 1357 | uint16_t mask) |
| 1358 | { |
| 1359 | if (!pci_is_express(dev) || !dev->exp.pasid_cap) { |
| 1360 | return false; |
| 1361 | } |
| 1362 | return (pci_get_word(dev->config + dev->exp.pasid_cap + PCI_PASID_CTRL) & |
| 1363 | mask) != 0; |
| 1364 | } |
| 1365 | |
| 1366 | uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev) |
| 1367 | { |
| 1368 | if (!pcie_pri_enabled(dev)) { |
| 1369 | return 0; |
| 1370 | } |
| 1371 | return pci_get_long(dev->config + dev->exp.pri_cap + PCI_PRI_ALLOC_REQ); |
| 1372 | } |
| 1373 | |
| 1374 | bool pcie_pri_enabled(const PCIDevice *dev) |
| 1375 | { |
| 1376 | if (!pci_is_express(dev) || !dev->exp.pri_cap) { |
| 1377 | return false; |
| 1378 | } |
| 1379 | return (pci_get_word(dev->config + dev->exp.pri_cap + PCI_PRI_CTRL) & |
| 1380 | PCI_PRI_CTRL_ENABLE) != 0; |
| 1381 | } |
| 1382 | |
| 1383 | bool pcie_pasid_enabled(const PCIDevice *dev) |
| 1384 | { |
| 1385 | return pcie_pasid_check_ctrl_bit_enabled(dev, PCI_PASID_CTRL_ENABLE); |
| 1386 | } |
| 1387 | |
| 1388 | bool pcie_pasid_priv_enabled(PCIDevice *dev) |
| 1389 | { |
| 1390 | return pcie_pasid_check_ctrl_bit_enabled(dev, PCI_PASID_CTRL_PRIV); |
| 1391 | } |
| 1392 | |
| 1393 | bool pcie_ats_enabled(const PCIDevice *dev) |
| 1394 | { |
| 1395 | if (!pci_is_express(dev) || !dev->exp.ats_cap) { |
| 1396 | return false; |
| 1397 | } |
| 1398 | return (pci_get_word(dev->config + dev->exp.ats_cap + PCI_ATS_CTRL) & |
| 1399 | PCI_ATS_CTRL_ENABLE) != 0; |
| 1400 | } |