| 1 | /* |
| 2 | * pcie_port.c |
| 3 | * |
| 4 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> |
| 5 | * VA Linux Systems Japan K.K. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "hw/pci/pcie_port.h" |
| 23 | #include "hw/core/qdev-properties.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "hw/core/hotplug.h" |
| 26 | |
| 27 | void pcie_port_init_reg(PCIDevice *d) |
| 28 | { |
| 29 | /* Unlike pci bridge, |
| 30 | 66MHz and fast back to back don't apply to pci express port. */ |
| 31 | pci_set_word(d->config + PCI_STATUS, 0); |
| 32 | pci_set_word(d->config + PCI_SEC_STATUS, 0); |
| 33 | |
| 34 | /* |
| 35 | * Unlike conventional pci bridge, for some bits the spec states: |
| 36 | * Does not apply to PCI Express and must be hardwired to 0. |
| 37 | */ |
| 38 | pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL, |
| 39 | PCI_BRIDGE_CTL_MASTER_ABORT | |
| 40 | PCI_BRIDGE_CTL_FAST_BACK | |
| 41 | PCI_BRIDGE_CTL_DISCARD | |
| 42 | PCI_BRIDGE_CTL_SEC_DISCARD | |
| 43 | PCI_BRIDGE_CTL_DISCARD_STATUS | |
| 44 | PCI_BRIDGE_CTL_DISCARD_SERR); |
| 45 | } |
| 46 | |
| 47 | /************************************************************************** |
| 48 | * (chassis number, pcie physical slot number) -> pcie slot conversion |
| 49 | */ |
| 50 | struct PCIEChassis { |
| 51 | uint8_t number; |
| 52 | |
| 53 | QLIST_HEAD(, PCIESlot) slots; |
| 54 | QLIST_ENTRY(PCIEChassis) next; |
| 55 | }; |
| 56 | |
| 57 | static QLIST_HEAD(, PCIEChassis) chassis = QLIST_HEAD_INITIALIZER(chassis); |
| 58 | |
| 59 | static struct PCIEChassis *pcie_chassis_find(uint8_t chassis_number) |
| 60 | { |
| 61 | struct PCIEChassis *c; |
| 62 | QLIST_FOREACH(c, &chassis, next) { |
| 63 | if (c->number == chassis_number) { |
| 64 | break; |
| 65 | } |
| 66 | } |
| 67 | return c; |
| 68 | } |
| 69 | |
| 70 | void pcie_chassis_create(uint8_t chassis_number) |
| 71 | { |
| 72 | struct PCIEChassis *c; |
| 73 | c = pcie_chassis_find(chassis_number); |
| 74 | if (c) { |
| 75 | return; |
| 76 | } |
| 77 | c = g_malloc0(sizeof(*c)); |
| 78 | c->number = chassis_number; |
| 79 | QLIST_INIT(&c->slots); |
| 80 | QLIST_INSERT_HEAD(&chassis, c, next); |
| 81 | } |
| 82 | |
| 83 | static PCIESlot *pcie_chassis_find_slot_with_chassis(struct PCIEChassis *c, |
| 84 | uint8_t slot) |
| 85 | { |
| 86 | PCIESlot *s; |
| 87 | QLIST_FOREACH(s, &c->slots, next) { |
| 88 | if (s->slot == slot) { |
| 89 | break; |
| 90 | } |
| 91 | } |
| 92 | return s; |
| 93 | } |
| 94 | |
| 95 | int pcie_chassis_add_slot(struct PCIESlot *slot) |
| 96 | { |
| 97 | struct PCIEChassis *c; |
| 98 | c = pcie_chassis_find(slot->chassis); |
| 99 | if (!c) { |
| 100 | return -ENODEV; |
| 101 | } |
| 102 | if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) { |
| 103 | return -EBUSY; |
| 104 | } |
| 105 | QLIST_INSERT_HEAD(&c->slots, slot, next); |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | void pcie_chassis_del_slot(PCIESlot *s) |
| 110 | { |
| 111 | QLIST_REMOVE(s, next); |
| 112 | } |
| 113 | |
| 114 | static const Property pcie_port_props[] = { |
| 115 | DEFINE_PROP_UINT8("port", PCIEPort, port, 0), |
| 116 | DEFINE_PROP_UINT16("aer_log_max", PCIEPort, |
| 117 | parent_obj.parent_obj.exp.aer_log.log_max, |
| 118 | PCIE_AER_LOG_MAX_DEFAULT), |
| 119 | }; |
| 120 | |
| 121 | static void pcie_port_class_init(ObjectClass *oc, const void *data) |
| 122 | { |
| 123 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 124 | |
| 125 | device_class_set_props(dc, pcie_port_props); |
| 126 | } |
| 127 | |
| 128 | PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn) |
| 129 | { |
| 130 | int devfn; |
| 131 | |
| 132 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
| 133 | PCIDevice *d = bus->devices[devfn]; |
| 134 | PCIEPort *port; |
| 135 | |
| 136 | if (!d || !pci_is_express(d) || !d->exp.exp_cap) { |
| 137 | continue; |
| 138 | } |
| 139 | |
| 140 | if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { |
| 141 | continue; |
| 142 | } |
| 143 | |
| 144 | port = PCIE_PORT(d); |
| 145 | if (port->port == pn) { |
| 146 | return d; |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | return NULL; |
| 151 | } |
| 152 | |
| 153 | /* Find first port in devfn number order */ |
| 154 | PCIDevice *pcie_find_port_first(PCIBus *bus) |
| 155 | { |
| 156 | int devfn; |
| 157 | |
| 158 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
| 159 | PCIDevice *d = bus->devices[devfn]; |
| 160 | |
| 161 | if (!d || !pci_is_express(d) || !d->exp.exp_cap) { |
| 162 | continue; |
| 163 | } |
| 164 | |
| 165 | if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { |
| 166 | return d; |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | return NULL; |
| 171 | } |
| 172 | |
| 173 | int pcie_count_ds_ports(PCIBus *bus) |
| 174 | { |
| 175 | int dsp_count = 0; |
| 176 | int devfn; |
| 177 | |
| 178 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
| 179 | PCIDevice *d = bus->devices[devfn]; |
| 180 | |
| 181 | if (!d || !pci_is_express(d) || !d->exp.exp_cap) { |
| 182 | continue; |
| 183 | } |
| 184 | if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { |
| 185 | dsp_count++; |
| 186 | } |
| 187 | } |
| 188 | return dsp_count; |
| 189 | } |
| 190 | |
| 191 | static bool pcie_slot_is_hotpluggable_bus(HotplugHandler *plug_handler, |
| 192 | BusState *bus) |
| 193 | { |
| 194 | PCIESlot *s = PCIE_SLOT(bus->parent); |
| 195 | return s->hotplug; |
| 196 | } |
| 197 | |
| 198 | static const TypeInfo pcie_port_type_info = { |
| 199 | .name = TYPE_PCIE_PORT, |
| 200 | .parent = TYPE_PCI_BRIDGE, |
| 201 | .instance_size = sizeof(PCIEPort), |
| 202 | .abstract = true, |
| 203 | .class_init = pcie_port_class_init, |
| 204 | }; |
| 205 | |
| 206 | static const Property pcie_slot_props[] = { |
| 207 | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
| 208 | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
| 209 | DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true), |
| 210 | DEFINE_PROP_BOOL("x-do-not-expose-native-hotplug-cap", PCIESlot, |
| 211 | hide_native_hotplug_cap, false), |
| 212 | }; |
| 213 | |
| 214 | static void pcie_slot_class_init(ObjectClass *oc, const void *data) |
| 215 | { |
| 216 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 217 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
| 218 | |
| 219 | device_class_set_props(dc, pcie_slot_props); |
| 220 | hc->pre_plug = pcie_cap_slot_pre_plug_cb; |
| 221 | hc->plug = pcie_cap_slot_plug_cb; |
| 222 | hc->unplug = pcie_cap_slot_unplug_cb; |
| 223 | hc->unplug_request = pcie_cap_slot_unplug_request_cb; |
| 224 | hc->is_hotpluggable_bus = pcie_slot_is_hotpluggable_bus; |
| 225 | } |
| 226 | |
| 227 | static const TypeInfo pcie_slot_type_info = { |
| 228 | .name = TYPE_PCIE_SLOT, |
| 229 | .parent = TYPE_PCIE_PORT, |
| 230 | .instance_size = sizeof(PCIESlot), |
| 231 | .abstract = true, |
| 232 | .class_init = pcie_slot_class_init, |
| 233 | .interfaces = (const InterfaceInfo[]) { |
| 234 | { TYPE_HOTPLUG_HANDLER }, |
| 235 | { } |
| 236 | } |
| 237 | }; |
| 238 | |
| 239 | static void pcie_port_register_types(void) |
| 240 | { |
| 241 | type_register_static(&pcie_port_type_info); |
| 242 | type_register_static(&pcie_slot_type_info); |
| 243 | } |
| 244 | |
| 245 | type_init(pcie_port_register_types) |