| 1 | /* |
| 2 | * QEMU Eyetech AmigaOne/Mai Logic Teron emulation |
| 3 | * |
| 4 | * Copyright (c) 2023 BALATON Zoltan |
| 5 | * |
| 6 | * This work is licensed under the GNU GPL license version 2 or later. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qemu/units.h" |
| 12 | #include "qemu/datadir.h" |
| 13 | #include "qemu/log.h" |
| 14 | #include "qemu/error-report.h" |
| 15 | #include "qapi/error.h" |
| 16 | #include "hw/ppc/ppc.h" |
| 17 | #include "hw/core/boards.h" |
| 18 | #include "hw/core/loader.h" |
| 19 | #include "hw/pci-host/articia.h" |
| 20 | #include "hw/isa/vt82c686.h" |
| 21 | #include "hw/ide/pci.h" |
| 22 | #include "hw/i2c/smbus_eeprom.h" |
| 23 | #include "exec/cpu-common.h" |
| 24 | #include "system/block-backend.h" |
| 25 | #include "system/physmem.h" |
| 26 | #include "system/qtest.h" |
| 27 | #include "system/reset.h" |
| 28 | #include "kvm_ppc.h" |
| 29 | #include "elf.h" |
| 30 | |
| 31 | #include <zlib.h> /* for crc32 */ |
| 32 | |
| 33 | #define BUS_FREQ_HZ 100000000 |
| 34 | |
| 35 | #define INITRD_MIN_ADDR 0x600000 |
| 36 | #define INIT_RAM_ADDR 0x40000000 |
| 37 | |
| 38 | #define PCI_HIGH_ADDR 0x80000000 |
| 39 | #define PCI_HIGH_SIZE 0x7d000000 |
| 40 | #define PCI_LOW_ADDR 0xfd000000 |
| 41 | #define PCI_LOW_SIZE 0xe0000 |
| 42 | |
| 43 | #define ARTICIA_ADDR 0xfe000000 |
| 44 | |
| 45 | /* |
| 46 | * Firmware binary available at |
| 47 | * https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28 |
| 48 | * then "tail -c 524288 updater.image >u-boot-amigaone.bin" |
| 49 | * |
| 50 | * BIOS emulator in firmware cannot run QEMU vgabios and hangs on it, use |
| 51 | * -device VGA,romfile=VGABIOS-lgpl-latest.bin |
| 52 | * from http://www.nongnu.org/vgabios/ instead. |
| 53 | */ |
| 54 | #define PROM_ADDR 0xfff00000 |
| 55 | #define PROM_SIZE (512 * KiB) |
| 56 | |
| 57 | /* AmigaOS calls this routine from ROM, use this if no firmware loaded */ |
| 58 | static const char dummy_fw[] = { |
| 59 | 0x54, 0x63, 0xc2, 0x3e, /* srwi r3,r3,8 */ |
| 60 | 0x7c, 0x63, 0x18, 0xf8, /* not r3,r3 */ |
| 61 | 0x4e, 0x80, 0x00, 0x20, /* blr */ |
| 62 | }; |
| 63 | |
| 64 | #define NVRAM_ADDR 0xfd0e0000 |
| 65 | #define NVRAM_SIZE (4 * KiB) |
| 66 | |
| 67 | static const char default_env[] = |
| 68 | "baudrate=115200\0" |
| 69 | "stdout=vga\0" |
| 70 | "stdin=ps2kbd\0" |
| 71 | "bootcmd=boota; menu; run menuboot_cmd\0" |
| 72 | "boot1=ide\0" |
| 73 | "boot2=cdrom\0" |
| 74 | "boota_timeout=3\0" |
| 75 | "ide_doreset=on\0" |
| 76 | "pci_irqa=9\0" |
| 77 | "pci_irqa_select=level\0" |
| 78 | "pci_irqb=10\0" |
| 79 | "pci_irqb_select=level\0" |
| 80 | "pci_irqc=11\0" |
| 81 | "pci_irqc_select=level\0" |
| 82 | "pci_irqd=7\0" |
| 83 | "pci_irqd_select=level\0" |
| 84 | "a1ide_irq=1111\0" |
| 85 | "a1ide_xfer=FFFF\0"; |
| 86 | #define CRC32_DEFAULT_ENV 0xb5548481 |
| 87 | #define CRC32_ALL_ZEROS 0x603b0489 |
| 88 | |
| 89 | #define TYPE_A1_NVRAM "a1-nvram" |
| 90 | OBJECT_DECLARE_SIMPLE_TYPE(A1NVRAMState, A1_NVRAM) |
| 91 | |
| 92 | struct A1NVRAMState { |
| 93 | SysBusDevice parent_obj; |
| 94 | |
| 95 | MemoryRegion mr; |
| 96 | BlockBackend *blk; |
| 97 | }; |
| 98 | |
| 99 | static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned int size) |
| 100 | { |
| 101 | /* read callback not used because of romd mode */ |
| 102 | g_assert_not_reached(); |
| 103 | } |
| 104 | |
| 105 | static void nvram_write(void *opaque, hwaddr addr, uint64_t val, |
| 106 | unsigned int size) |
| 107 | { |
| 108 | A1NVRAMState *s = opaque; |
| 109 | uint8_t *p = memory_region_get_ram_ptr(&s->mr); |
| 110 | |
| 111 | p[addr] = val; |
| 112 | if (s->blk && blk_pwrite(s->blk, addr, 1, &val, 0) < 0) { |
| 113 | error_report("%s: could not write %s", __func__, blk_name(s->blk)); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | static const MemoryRegionOps nvram_ops = { |
| 118 | .read = nvram_read, |
| 119 | .write = nvram_write, |
| 120 | .endianness = DEVICE_BIG_ENDIAN, |
| 121 | .impl = { |
| 122 | .min_access_size = 1, |
| 123 | .max_access_size = 1, |
| 124 | }, |
| 125 | }; |
| 126 | |
| 127 | static void nvram_realize(DeviceState *dev, Error **errp) |
| 128 | { |
| 129 | A1NVRAMState *s = A1_NVRAM(dev); |
| 130 | void *p; |
| 131 | uint32_t crc, *c; |
| 132 | |
| 133 | memory_region_init_rom_device(&s->mr, NULL, &nvram_ops, s, "nvram", |
| 134 | NVRAM_SIZE, &error_fatal); |
| 135 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); |
| 136 | c = p = memory_region_get_ram_ptr(&s->mr); |
| 137 | if (s->blk) { |
| 138 | if (blk_getlength(s->blk) != NVRAM_SIZE) { |
| 139 | error_setg(errp, "NVRAM backing file size must be %" PRId64 "bytes", |
| 140 | NVRAM_SIZE); |
| 141 | return; |
| 142 | } |
| 143 | blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, |
| 144 | BLK_PERM_ALL, &error_fatal); |
| 145 | if (blk_pread(s->blk, 0, NVRAM_SIZE, p, 0) < 0) { |
| 146 | error_setg(errp, "Cannot read NVRAM contents from backing file"); |
| 147 | return; |
| 148 | } |
| 149 | } |
| 150 | crc = crc32(0, p + 4, NVRAM_SIZE - 4); |
| 151 | if (crc == CRC32_ALL_ZEROS) { /* If env is uninitialized set default */ |
| 152 | *c = cpu_to_be32(CRC32_DEFAULT_ENV); |
| 153 | /* Also copies terminating \0 as env is terminated by \0\0 */ |
| 154 | memcpy(p + 4, default_env, sizeof(default_env)); |
| 155 | if (s->blk && |
| 156 | blk_pwrite(s->blk, 0, sizeof(crc) + sizeof(default_env), p, 0) < 0 |
| 157 | ) { |
| 158 | error_report("%s: could not write %s", __func__, blk_name(s->blk)); |
| 159 | } |
| 160 | return; |
| 161 | } |
| 162 | if (*c == 0) { |
| 163 | *c = cpu_to_be32(crc32(0, p + 4, NVRAM_SIZE - 4)); |
| 164 | if (s->blk && blk_pwrite(s->blk, 0, 4, p, 0) < 0) { |
| 165 | error_report("%s: could not write %s", __func__, blk_name(s->blk)); |
| 166 | } |
| 167 | } |
| 168 | if (be32_to_cpu(*c) != crc) { |
| 169 | warn_report("NVRAM checksum mismatch"); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | static const Property nvram_properties[] = { |
| 174 | DEFINE_PROP_DRIVE("drive", A1NVRAMState, blk), |
| 175 | }; |
| 176 | |
| 177 | static void nvram_class_init(ObjectClass *oc, const void *data) |
| 178 | { |
| 179 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 180 | |
| 181 | dc->realize = nvram_realize; |
| 182 | device_class_set_props(dc, nvram_properties); |
| 183 | } |
| 184 | |
| 185 | static const TypeInfo nvram_types[] = { |
| 186 | { |
| 187 | .name = TYPE_A1_NVRAM, |
| 188 | .parent = TYPE_SYS_BUS_DEVICE, |
| 189 | .instance_size = sizeof(A1NVRAMState), |
| 190 | .class_init = nvram_class_init, |
| 191 | }, |
| 192 | }; |
| 193 | DEFINE_TYPES(nvram_types) |
| 194 | |
| 195 | struct boot_info { |
| 196 | hwaddr entry; |
| 197 | hwaddr stack; |
| 198 | hwaddr bd_info; |
| 199 | hwaddr initrd_start; |
| 200 | hwaddr initrd_end; |
| 201 | hwaddr cmdline_start; |
| 202 | hwaddr cmdline_end; |
| 203 | }; |
| 204 | |
| 205 | /* Board info struct from U-Boot */ |
| 206 | struct bd_info { |
| 207 | uint32_t bi_memstart; |
| 208 | uint32_t bi_memsize; |
| 209 | uint32_t bi_flashstart; |
| 210 | uint32_t bi_flashsize; |
| 211 | uint32_t bi_flashoffset; |
| 212 | uint32_t bi_sramstart; |
| 213 | uint32_t bi_sramsize; |
| 214 | uint32_t bi_bootflags; |
| 215 | uint32_t bi_ip_addr; |
| 216 | uint8_t bi_enetaddr[6]; |
| 217 | uint16_t bi_ethspeed; |
| 218 | uint32_t bi_intfreq; |
| 219 | uint32_t bi_busfreq; |
| 220 | uint32_t bi_baudrate; |
| 221 | } QEMU_PACKED; |
| 222 | |
| 223 | static void create_bd_info(hwaddr addr, ram_addr_t ram_size) |
| 224 | { |
| 225 | g_autofree struct bd_info *bd = g_new0(struct bd_info, 1); |
| 226 | |
| 227 | bd->bi_memsize = cpu_to_be32(ram_size); |
| 228 | bd->bi_flashstart = cpu_to_be32(PROM_ADDR); |
| 229 | bd->bi_flashsize = cpu_to_be32(1); /* match what U-Boot detects */ |
| 230 | bd->bi_bootflags = cpu_to_be32(1); |
| 231 | bd->bi_intfreq = cpu_to_be32(11.5 * BUS_FREQ_HZ); |
| 232 | bd->bi_busfreq = cpu_to_be32(BUS_FREQ_HZ); |
| 233 | bd->bi_baudrate = cpu_to_be32(115200); |
| 234 | |
| 235 | physical_memory_write(addr, bd, sizeof(*bd)); |
| 236 | } |
| 237 | |
| 238 | static void amigaone_cpu_reset(void *opaque) |
| 239 | { |
| 240 | PowerPCCPU *cpu = opaque; |
| 241 | CPUPPCState *env = &cpu->env; |
| 242 | |
| 243 | cpu_reset(CPU(cpu)); |
| 244 | if (env->load_info) { |
| 245 | struct boot_info *bi = env->load_info; |
| 246 | |
| 247 | env->gpr[1] = bi->stack; |
| 248 | env->gpr[2] = 1024; |
| 249 | env->gpr[3] = bi->bd_info; |
| 250 | env->gpr[4] = bi->initrd_start; |
| 251 | env->gpr[5] = bi->initrd_end; |
| 252 | env->gpr[6] = bi->cmdline_start; |
| 253 | env->gpr[7] = bi->cmdline_end; |
| 254 | env->nip = bi->entry; |
| 255 | } |
| 256 | cpu_ppc_tb_reset(env); |
| 257 | } |
| 258 | |
| 259 | static void fix_spd_data(uint8_t *spd) |
| 260 | { |
| 261 | uint32_t bank_size = 4 * MiB * spd[31]; |
| 262 | uint32_t rows = bank_size / spd[13] / spd[17]; |
| 263 | spd[3] = ctz32(rows) - spd[4]; |
| 264 | } |
| 265 | |
| 266 | static void amigaone_init(MachineState *machine) |
| 267 | { |
| 268 | PowerPCCPU *cpu; |
| 269 | CPUPPCState *env; |
| 270 | MemoryRegion *rom, *pci_mem, *mr; |
| 271 | ssize_t sz; |
| 272 | PCIBus *pci_bus; |
| 273 | Object *via; |
| 274 | DeviceState *dev; |
| 275 | I2CBus *i2c_bus; |
| 276 | uint8_t *spd_data; |
| 277 | DriveInfo *di; |
| 278 | hwaddr loadaddr; |
| 279 | struct boot_info *bi = NULL; |
| 280 | |
| 281 | /* init CPU */ |
| 282 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
| 283 | env = &cpu->env; |
| 284 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
| 285 | error_report("Incompatible CPU, only 6xx bus supported"); |
| 286 | exit(1); |
| 287 | } |
| 288 | cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); |
| 289 | qemu_register_reset(amigaone_cpu_reset, cpu); |
| 290 | |
| 291 | /* RAM */ |
| 292 | if (machine->ram_size > 2 * GiB) { |
| 293 | error_report("RAM size more than 2 GiB is not supported"); |
| 294 | exit(1); |
| 295 | } |
| 296 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
| 297 | if (machine->ram_size < 1 * GiB + 32 * KiB) { |
| 298 | /* Firmware uses this area for startup */ |
| 299 | mr = g_new(MemoryRegion, 1); |
| 300 | memory_region_init_ram(mr, NULL, "init-cache", 32 * KiB, &error_fatal); |
| 301 | memory_region_add_subregion(get_system_memory(), INIT_RAM_ADDR, mr); |
| 302 | } |
| 303 | |
| 304 | /* nvram */ |
| 305 | dev = qdev_new(TYPE_A1_NVRAM); |
| 306 | di = drive_get(IF_MTD, 0, 0); |
| 307 | if (di) { |
| 308 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); |
| 309 | } |
| 310 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 311 | memory_region_add_subregion(get_system_memory(), NVRAM_ADDR, |
| 312 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); |
| 313 | |
| 314 | /* allocate and load firmware */ |
| 315 | rom = g_new(MemoryRegion, 1); |
| 316 | memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal); |
| 317 | memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); |
| 318 | if (!machine->firmware) { |
| 319 | rom_add_blob_fixed("dummy-fw", dummy_fw, sizeof(dummy_fw), |
| 320 | PROM_ADDR + PROM_SIZE - 0x80); |
| 321 | } else { |
| 322 | g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, |
| 323 | machine->firmware); |
| 324 | if (!filename) { |
| 325 | error_report("Could not find firmware '%s'", machine->firmware); |
| 326 | exit(1); |
| 327 | } |
| 328 | sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE, &error_fatal); |
| 329 | } |
| 330 | |
| 331 | /* Articia S */ |
| 332 | dev = sysbus_create_simple(TYPE_ARTICIA, ARTICIA_ADDR, NULL); |
| 333 | |
| 334 | i2c_bus = I2C_BUS(qdev_get_child_bus(dev, "smbus")); |
| 335 | if (machine->ram_size > 512 * MiB) { |
| 336 | spd_data = spd_data_generate(SDR, machine->ram_size / 2); |
| 337 | } else { |
| 338 | spd_data = spd_data_generate(SDR, machine->ram_size); |
| 339 | } |
| 340 | fix_spd_data(spd_data); |
| 341 | smbus_eeprom_init_one(i2c_bus, 0x51, spd_data); |
| 342 | if (machine->ram_size > 512 * MiB) { |
| 343 | smbus_eeprom_init_one(i2c_bus, 0x52, spd_data); |
| 344 | } |
| 345 | |
| 346 | pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); |
| 347 | mr = g_new(MemoryRegion, 1); |
| 348 | memory_region_init_alias(mr, OBJECT(dev), "pci-mem-low", pci_mem, |
| 349 | 0, PCI_LOW_SIZE); |
| 350 | memory_region_add_subregion(get_system_memory(), PCI_LOW_ADDR, mr); |
| 351 | mr = g_new(MemoryRegion, 1); |
| 352 | memory_region_init_alias(mr, OBJECT(dev), "pci-mem-high", pci_mem, |
| 353 | PCI_HIGH_ADDR, PCI_HIGH_SIZE); |
| 354 | memory_region_add_subregion(get_system_memory(), PCI_HIGH_ADDR, mr); |
| 355 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
| 356 | |
| 357 | /* VIA VT82c686B South Bridge (multifunction PCI device) */ |
| 358 | via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(7, 0), |
| 359 | TYPE_VT82C686B_ISA)); |
| 360 | object_property_add_alias(OBJECT(machine), "rtc-time", |
| 361 | object_resolve_path_component(via, "rtc"), |
| 362 | "date"); |
| 363 | qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, |
| 364 | qdev_get_gpio_in(DEVICE(cpu), |
| 365 | PPC6xx_INPUT_INT)); |
| 366 | for (int i = 0; i < PCI_NUM_PINS; i++) { |
| 367 | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via), |
| 368 | "pirq", i)); |
| 369 | } |
| 370 | pci_ide_create_devs(PCI_DEVICE(object_resolve_path_component(via, "ide"))); |
| 371 | pci_vga_init(pci_bus); |
| 372 | |
| 373 | if (!machine->kernel_filename) { |
| 374 | return; |
| 375 | } |
| 376 | |
| 377 | /* handle -kernel, -initrd, -append options and emulate U-Boot */ |
| 378 | bi = g_new0(struct boot_info, 1); |
| 379 | cpu->env.load_info = bi; |
| 380 | |
| 381 | loadaddr = MIN(machine->ram_size, 256 * MiB); |
| 382 | bi->bd_info = loadaddr - 8 * MiB; |
| 383 | create_bd_info(bi->bd_info, machine->ram_size); |
| 384 | bi->stack = bi->bd_info - 64 * KiB - 8; |
| 385 | |
| 386 | if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { |
| 387 | size_t len = strlen(machine->kernel_cmdline); |
| 388 | |
| 389 | loadaddr = bi->bd_info + 1 * MiB; |
| 390 | physical_memory_write(loadaddr, machine->kernel_cmdline, len + 1); |
| 391 | bi->cmdline_start = loadaddr; |
| 392 | bi->cmdline_end = loadaddr + len + 1; /* including terminating '\0' */ |
| 393 | } |
| 394 | |
| 395 | sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, |
| 396 | &bi->entry, &loadaddr, NULL, NULL, |
| 397 | ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 398 | if (sz <= 0) { |
| 399 | sz = load_uimage(machine->kernel_filename, &bi->entry, &loadaddr, |
| 400 | NULL, NULL, NULL); |
| 401 | } |
| 402 | if (sz <= 0) { |
| 403 | error_report("Could not load kernel '%s'", |
| 404 | machine->kernel_filename); |
| 405 | exit(1); |
| 406 | } |
| 407 | loadaddr += sz; |
| 408 | |
| 409 | if (machine->initrd_filename) { |
| 410 | loadaddr = ROUND_UP(loadaddr + 4 * MiB, 4 * KiB); |
| 411 | loadaddr = MAX(loadaddr, INITRD_MIN_ADDR); |
| 412 | sz = load_image_targphys(machine->initrd_filename, loadaddr, |
| 413 | bi->bd_info - loadaddr, &error_fatal); |
| 414 | bi->initrd_start = loadaddr; |
| 415 | bi->initrd_end = loadaddr + sz; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static void amigaone_machine_init(MachineClass *mc) |
| 420 | { |
| 421 | mc->desc = "Eyetech AmigaOne/Mai Logic Teron"; |
| 422 | mc->init = amigaone_init; |
| 423 | mc->block_default_type = IF_IDE; |
| 424 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2"); |
| 425 | mc->default_display = "std"; |
| 426 | mc->default_ram_id = "ram"; |
| 427 | mc->default_ram_size = 512 * MiB; |
| 428 | } |
| 429 | |
| 430 | DEFINE_MACHINE("amigaone", amigaone_machine_init) |