| 1 | /* |
| 2 | * QEMU PowerPC e500-based platforms |
| 3 | * |
| 4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. |
| 5 | * |
| 6 | * Author: Yu Liu, <yu.liu@freescale.com> |
| 7 | * |
| 8 | * This file is derived from hw/ppc440_bamboo.c, |
| 9 | * the copyright for that material belongs to the original owners. |
| 10 | * |
| 11 | * This is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "qemu/datadir.h" |
| 19 | #include "qemu/units.h" |
| 20 | #include "qemu/guest-random.h" |
| 21 | #include "exec/target_page.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "cpu-models.h" |
| 24 | #include "e500.h" |
| 25 | #include "e500-ccsr.h" |
| 26 | #include "net/net.h" |
| 27 | #include "qemu/config-file.h" |
| 28 | #include "hw/block/flash.h" |
| 29 | #include "hw/char/serial-mm.h" |
| 30 | #include "hw/pci/pci.h" |
| 31 | #include "system/block-backend-io.h" |
| 32 | #include "system/physmem.h" |
| 33 | #include "system/system.h" |
| 34 | #include "system/kvm.h" |
| 35 | #include "system/reset.h" |
| 36 | #include "system/runstate.h" |
| 37 | #include "kvm_ppc.h" |
| 38 | #include "system/device_tree.h" |
| 39 | #include "hw/ppc/openpic.h" |
| 40 | #include "hw/ppc/openpic_kvm.h" |
| 41 | #include "hw/ppc/ppc.h" |
| 42 | #include "hw/core/qdev-properties.h" |
| 43 | #include "hw/core/loader.h" |
| 44 | #include "elf.h" |
| 45 | #include "hw/core/sysbus.h" |
| 46 | #include "qemu/host-utils.h" |
| 47 | #include "qemu/option.h" |
| 48 | #include "hw/pci-host/ppce500.h" |
| 49 | #include "qemu/error-report.h" |
| 50 | #include "hw/core/platform-bus.h" |
| 51 | #include "hw/net/fsl_etsec/etsec.h" |
| 52 | #include "hw/i2c/i2c.h" |
| 53 | #include "hw/core/irq.h" |
| 54 | #include "hw/sd/sdhci.h" |
| 55 | #include "hw/misc/unimp.h" |
| 56 | #include "exec/cpu-common.h" |
| 57 | |
| 58 | #define EPAPR_MAGIC (0x45504150) |
| 59 | #define DTC_LOAD_PAD 0x1800000 |
| 60 | #define DTC_PAD_MASK 0xFFFFF |
| 61 | #define DTB_MAX_SIZE (8 * MiB) |
| 62 | #define INITRD_LOAD_PAD 0x2000000 |
| 63 | #define INITRD_PAD_MASK 0xFFFFFF |
| 64 | |
| 65 | #define RAM_SIZES_ALIGN (64 * MiB) |
| 66 | |
| 67 | /* TODO: parameterize */ |
| 68 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL |
| 69 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
| 70 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
| 71 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
| 72 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL |
| 73 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL |
| 74 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
| 75 | #define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL |
| 76 | #define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL |
| 77 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
| 78 | #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL |
| 79 | #define MPC8544_I2C_REGS_OFFSET 0x3000ULL |
| 80 | #define MPC8XXX_GPIO_IRQ 47 |
| 81 | #define MPC8544_I2C_IRQ 43 |
| 82 | #define MPC85XX_ESDHC_IRQ 72 |
| 83 | #define RTC_REGS_OFFSET 0x68 |
| 84 | |
| 85 | struct boot_info |
| 86 | { |
| 87 | uint32_t dt_base; |
| 88 | uint32_t dt_size; |
| 89 | uint32_t entry; |
| 90 | }; |
| 91 | |
| 92 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
| 93 | int nr_slots, int *len) |
| 94 | { |
| 95 | int i = 0; |
| 96 | int slot; |
| 97 | int pci_irq; |
| 98 | int host_irq; |
| 99 | int last_slot = first_slot + nr_slots; |
| 100 | uint32_t *pci_map; |
| 101 | |
| 102 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); |
| 103 | pci_map = g_malloc(*len); |
| 104 | |
| 105 | for (slot = first_slot; slot < last_slot; slot++) { |
| 106 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { |
| 107 | pci_map[i++] = cpu_to_be32(slot << 11); |
| 108 | pci_map[i++] = cpu_to_be32(0x0); |
| 109 | pci_map[i++] = cpu_to_be32(0x0); |
| 110 | pci_map[i++] = cpu_to_be32(pci_irq + 1); |
| 111 | pci_map[i++] = cpu_to_be32(mpic); |
| 112 | host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
| 113 | pci_map[i++] = cpu_to_be32(host_irq + 1); |
| 114 | pci_map[i++] = cpu_to_be32(0x1); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | assert((i * sizeof(uint32_t)) == *len); |
| 119 | |
| 120 | return pci_map; |
| 121 | } |
| 122 | |
| 123 | static void dt_serial_create(void *fdt, unsigned long long offset, |
| 124 | const char *soc, uint32_t freq, const char *mpic, |
| 125 | const char *alias, int idx, bool defcon) |
| 126 | { |
| 127 | char *ser; |
| 128 | |
| 129 | ser = g_strdup_printf("%s/serial@%llx", soc, offset); |
| 130 | qemu_fdt_add_subnode(fdt, ser); |
| 131 | qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); |
| 132 | qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); |
| 133 | qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); |
| 134 | qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); |
| 135 | qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq); |
| 136 | qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); |
| 137 | qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); |
| 138 | qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); |
| 139 | |
| 140 | if (defcon) { |
| 141 | /* |
| 142 | * "linux,stdout-path" and "stdout" properties are deprecated by linux |
| 143 | * kernel. New platforms should only use the "stdout-path" property. Set |
| 144 | * the new property and continue using older property to remain |
| 145 | * compatible with the existing firmware. |
| 146 | */ |
| 147 | qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); |
| 148 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); |
| 149 | } |
| 150 | g_free(ser); |
| 151 | } |
| 152 | |
| 153 | static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) |
| 154 | { |
| 155 | hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; |
| 156 | int irq0 = MPC8XXX_GPIO_IRQ; |
| 157 | gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); |
| 158 | gchar *poweroff = g_strdup_printf("%s/power-off", soc); |
| 159 | int gpio_ph; |
| 160 | |
| 161 | qemu_fdt_add_subnode(fdt, node); |
| 162 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); |
| 163 | qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); |
| 164 | qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); |
| 165 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); |
| 166 | qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); |
| 167 | qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); |
| 168 | gpio_ph = qemu_fdt_alloc_phandle(fdt); |
| 169 | qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); |
| 170 | qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); |
| 171 | |
| 172 | /* Power Off Pin */ |
| 173 | qemu_fdt_add_subnode(fdt, poweroff); |
| 174 | qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); |
| 175 | qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); |
| 176 | |
| 177 | g_free(node); |
| 178 | g_free(poweroff); |
| 179 | } |
| 180 | |
| 181 | static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) |
| 182 | { |
| 183 | int offset = RTC_REGS_OFFSET; |
| 184 | |
| 185 | gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); |
| 186 | qemu_fdt_add_subnode(fdt, rtc); |
| 187 | qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); |
| 188 | qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); |
| 189 | qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); |
| 190 | |
| 191 | g_free(rtc); |
| 192 | } |
| 193 | |
| 194 | static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, |
| 195 | const char *alias) |
| 196 | { |
| 197 | hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; |
| 198 | int irq0 = MPC8544_I2C_IRQ; |
| 199 | |
| 200 | gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); |
| 201 | qemu_fdt_add_subnode(fdt, i2c); |
| 202 | qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); |
| 203 | qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); |
| 204 | qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); |
| 205 | qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); |
| 206 | qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); |
| 207 | qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); |
| 208 | qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0); |
| 209 | qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1); |
| 210 | qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); |
| 211 | |
| 212 | g_free(i2c); |
| 213 | } |
| 214 | |
| 215 | static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) |
| 216 | { |
| 217 | hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET; |
| 218 | hwaddr size = MPC85XX_ESDHC_REGS_SIZE; |
| 219 | int irq = MPC85XX_ESDHC_IRQ; |
| 220 | g_autofree char *name = NULL; |
| 221 | |
| 222 | name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio); |
| 223 | qemu_fdt_add_subnode(fdt, name); |
| 224 | qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); |
| 225 | qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); |
| 226 | qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); |
| 227 | qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); |
| 228 | qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); |
| 229 | qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); |
| 230 | } |
| 231 | |
| 232 | typedef struct PlatformDevtreeData { |
| 233 | void *fdt; |
| 234 | const char *mpic; |
| 235 | int irq_start; |
| 236 | const char *node; |
| 237 | PlatformBusDevice *pbus; |
| 238 | } PlatformDevtreeData; |
| 239 | |
| 240 | static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) |
| 241 | { |
| 242 | eTSEC *etsec = ETSEC_COMMON(sbdev); |
| 243 | PlatformBusDevice *pbus = data->pbus; |
| 244 | hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); |
| 245 | int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); |
| 246 | int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); |
| 247 | int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); |
| 248 | gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0); |
| 249 | gchar *group = g_strdup_printf("%s/queue-group", node); |
| 250 | void *fdt = data->fdt; |
| 251 | |
| 252 | assert((int64_t)mmio0 >= 0); |
| 253 | assert(irq0 >= 0); |
| 254 | assert(irq1 >= 0); |
| 255 | assert(irq2 >= 0); |
| 256 | |
| 257 | qemu_fdt_add_subnode(fdt, node); |
| 258 | qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); |
| 259 | qemu_fdt_setprop_string(fdt, node, "device_type", "network"); |
| 260 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); |
| 261 | qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); |
| 262 | qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); |
| 263 | qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); |
| 264 | qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); |
| 265 | qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); |
| 266 | |
| 267 | qemu_fdt_add_subnode(fdt, group); |
| 268 | qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); |
| 269 | qemu_fdt_setprop_cells(fdt, group, "interrupts", |
| 270 | data->irq_start + irq0, 0x2, |
| 271 | data->irq_start + irq1, 0x2, |
| 272 | data->irq_start + irq2, 0x2); |
| 273 | |
| 274 | g_free(node); |
| 275 | g_free(group); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) |
| 281 | { |
| 282 | PlatformDevtreeData *data = opaque; |
| 283 | bool matched = false; |
| 284 | |
| 285 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { |
| 286 | create_devtree_etsec(sbdev, data); |
| 287 | matched = true; |
| 288 | } |
| 289 | |
| 290 | if (!matched) { |
| 291 | error_report("Device %s is not supported by this machine yet.", |
| 292 | qdev_fw_name(DEVICE(sbdev))); |
| 293 | exit(1); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | static void create_devtree_flash(SysBusDevice *sbdev, |
| 298 | PlatformDevtreeData *data) |
| 299 | { |
| 300 | g_autofree char *name = NULL; |
| 301 | uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev), |
| 302 | "num-blocks", |
| 303 | &error_fatal); |
| 304 | uint64_t sector_length = object_property_get_uint(OBJECT(sbdev), |
| 305 | "sector-length", |
| 306 | &error_fatal); |
| 307 | uint64_t bank_width = object_property_get_uint(OBJECT(sbdev), |
| 308 | "width", |
| 309 | &error_fatal); |
| 310 | hwaddr flashbase = 0; |
| 311 | hwaddr flashsize = num_blocks * sector_length; |
| 312 | void *fdt = data->fdt; |
| 313 | |
| 314 | name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase); |
| 315 | qemu_fdt_add_subnode(fdt, name); |
| 316 | qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); |
| 317 | qemu_fdt_setprop_sized_cells(fdt, name, "reg", |
| 318 | 1, flashbase, 1, flashsize); |
| 319 | qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width); |
| 320 | } |
| 321 | |
| 322 | static void platform_bus_create_devtree(PPCE500MachineState *pms, |
| 323 | void *fdt, const char *mpic) |
| 324 | { |
| 325 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
| 326 | gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); |
| 327 | const char platcomp[] = "qemu,platform\0simple-bus"; |
| 328 | uint64_t addr = pmc->platform_bus_base; |
| 329 | uint64_t size = pmc->platform_bus_size; |
| 330 | int irq_start = pmc->platform_bus_first_irq; |
| 331 | SysBusDevice *sbdev; |
| 332 | bool ambiguous; |
| 333 | |
| 334 | /* Create a /platform node that we can put all devices into */ |
| 335 | |
| 336 | qemu_fdt_add_subnode(fdt, node); |
| 337 | qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); |
| 338 | |
| 339 | /* Our platform bus region is less than 32bit big, so 1 cell is enough for |
| 340 | address and size */ |
| 341 | qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); |
| 342 | qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); |
| 343 | qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); |
| 344 | |
| 345 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); |
| 346 | |
| 347 | /* Create dt nodes for dynamic devices */ |
| 348 | PlatformDevtreeData data = { |
| 349 | .fdt = fdt, |
| 350 | .mpic = mpic, |
| 351 | .irq_start = irq_start, |
| 352 | .node = node, |
| 353 | .pbus = pms->pbus_dev, |
| 354 | }; |
| 355 | |
| 356 | /* Loop through all dynamic sysbus devices and create nodes for them */ |
| 357 | foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); |
| 358 | |
| 359 | sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01, |
| 360 | &ambiguous)); |
| 361 | if (sbdev) { |
| 362 | assert(!ambiguous); |
| 363 | create_devtree_flash(sbdev, &data); |
| 364 | } |
| 365 | |
| 366 | g_free(node); |
| 367 | } |
| 368 | |
| 369 | static int ppce500_load_device_tree(PPCE500MachineState *pms, |
| 370 | hwaddr addr, |
| 371 | hwaddr initrd_base, |
| 372 | hwaddr initrd_size, |
| 373 | hwaddr kernel_base, |
| 374 | hwaddr kernel_size, |
| 375 | bool dry_run) |
| 376 | { |
| 377 | MachineState *machine = MACHINE(pms); |
| 378 | unsigned int smp_cpus = machine->smp.cpus; |
| 379 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
| 380 | CPUPPCState *env = cpu_env(first_cpu); |
| 381 | int ret = -1; |
| 382 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; |
| 383 | int fdt_size; |
| 384 | void *fdt; |
| 385 | uint8_t hypercall[16]; |
| 386 | uint32_t clock_freq, tb_freq; |
| 387 | int i; |
| 388 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
| 389 | char *soc; |
| 390 | char *mpic; |
| 391 | uint32_t mpic_ph; |
| 392 | uint32_t msi_ph; |
| 393 | char *gutil; |
| 394 | char *pci; |
| 395 | char *msi; |
| 396 | uint32_t *pci_map = NULL; |
| 397 | int len; |
| 398 | uint32_t pci_ranges[14] = |
| 399 | { |
| 400 | 0x2000000, 0x0, pmc->pci_mmio_bus_base, |
| 401 | pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, |
| 402 | 0x0, 0x20000000, |
| 403 | |
| 404 | 0x1000000, 0x0, 0x0, |
| 405 | pmc->pci_pio_base >> 32, pmc->pci_pio_base, |
| 406 | 0x0, 0x10000, |
| 407 | }; |
| 408 | const char *dtb_file = machine->dtb; |
| 409 | const char *toplevel_compat = machine->dt_compatible; |
| 410 | uint8_t rng_seed[32]; |
| 411 | |
| 412 | if (dtb_file) { |
| 413 | char *filename; |
| 414 | filename = qemu_find_file(QEMU_FILE_TYPE_DTB, dtb_file); |
| 415 | if (!filename) { |
| 416 | goto out; |
| 417 | } |
| 418 | |
| 419 | fdt = load_device_tree(filename, &fdt_size); |
| 420 | g_free(filename); |
| 421 | if (!fdt) { |
| 422 | goto out; |
| 423 | } |
| 424 | goto done; |
| 425 | } |
| 426 | |
| 427 | fdt = create_device_tree(&fdt_size); |
| 428 | if (fdt == NULL) { |
| 429 | goto out; |
| 430 | } |
| 431 | |
| 432 | /* Manipulate device tree in memory. */ |
| 433 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); |
| 434 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); |
| 435 | |
| 436 | qemu_fdt_add_subnode(fdt, "/memory"); |
| 437 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); |
| 438 | qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, |
| 439 | sizeof(mem_reg_property)); |
| 440 | |
| 441 | qemu_fdt_add_subnode(fdt, "/chosen"); |
| 442 | if (initrd_size) { |
| 443 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
| 444 | initrd_base); |
| 445 | if (ret < 0) { |
| 446 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); |
| 447 | } |
| 448 | |
| 449 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
| 450 | (initrd_base + initrd_size)); |
| 451 | if (ret < 0) { |
| 452 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); |
| 453 | } |
| 454 | |
| 455 | } |
| 456 | |
| 457 | if (kernel_base != -1ULL) { |
| 458 | qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", |
| 459 | kernel_base >> 32, kernel_base, |
| 460 | kernel_size >> 32, kernel_size); |
| 461 | } |
| 462 | |
| 463 | ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
| 464 | machine->kernel_cmdline); |
| 465 | if (ret < 0) |
| 466 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); |
| 467 | |
| 468 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); |
| 469 | qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); |
| 470 | |
| 471 | if (kvm_enabled()) { |
| 472 | /* Read out host's frequencies */ |
| 473 | clock_freq = kvmppc_get_clockfreq(); |
| 474 | tb_freq = kvmppc_get_tbfreq(); |
| 475 | |
| 476 | /* indicate KVM hypercall interface */ |
| 477 | qemu_fdt_add_subnode(fdt, "/hypervisor"); |
| 478 | qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", |
| 479 | "linux,kvm"); |
| 480 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); |
| 481 | qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", |
| 482 | hypercall, sizeof(hypercall)); |
| 483 | /* if KVM supports the idle hcall, set property indicating this */ |
| 484 | if (kvmppc_get_hasidle(env)) { |
| 485 | qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); |
| 486 | } |
| 487 | } else { |
| 488 | clock_freq = pmc->clock_freq; |
| 489 | tb_freq = pmc->tb_freq; |
| 490 | } |
| 491 | |
| 492 | /* Create CPU nodes */ |
| 493 | qemu_fdt_add_subnode(fdt, "/cpus"); |
| 494 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); |
| 495 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); |
| 496 | |
| 497 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
| 498 | the first node as boot node and be happy */ |
| 499 | for (i = smp_cpus - 1; i >= 0; i--) { |
| 500 | CPUState *cpu; |
| 501 | char *cpu_name; |
| 502 | uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); |
| 503 | |
| 504 | cpu = qemu_get_cpu(i); |
| 505 | if (cpu == NULL) { |
| 506 | continue; |
| 507 | } |
| 508 | env = cpu_env(cpu); |
| 509 | |
| 510 | cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); |
| 511 | qemu_fdt_add_subnode(fdt, cpu_name); |
| 512 | qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
| 513 | qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); |
| 514 | qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
| 515 | qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); |
| 516 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", |
| 517 | env->dcache_line_size); |
| 518 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", |
| 519 | env->icache_line_size); |
| 520 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); |
| 521 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); |
| 522 | qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", pmc->bus_freq); |
| 523 | if (cpu->cpu_index) { |
| 524 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); |
| 525 | qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", |
| 526 | "spin-table"); |
| 527 | qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", |
| 528 | cpu_release_addr); |
| 529 | } else { |
| 530 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); |
| 531 | } |
| 532 | g_free(cpu_name); |
| 533 | } |
| 534 | |
| 535 | qemu_fdt_add_subnode(fdt, "/aliases"); |
| 536 | /* XXX These should go into their respective devices' code */ |
| 537 | soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); |
| 538 | qemu_fdt_add_subnode(fdt, soc); |
| 539 | qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); |
| 540 | qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, |
| 541 | sizeof(compatible_sb)); |
| 542 | qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); |
| 543 | qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); |
| 544 | qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, |
| 545 | pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, |
| 546 | MPC8544_CCSRBAR_SIZE); |
| 547 | /* XXX should contain a reasonable value */ |
| 548 | qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); |
| 549 | |
| 550 | mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
| 551 | qemu_fdt_add_subnode(fdt, mpic); |
| 552 | qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); |
| 553 | qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); |
| 554 | qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, |
| 555 | 0x40000); |
| 556 | qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); |
| 557 | qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); |
| 558 | mpic_ph = qemu_fdt_alloc_phandle(fdt); |
| 559 | qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); |
| 560 | qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); |
| 561 | qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); |
| 562 | |
| 563 | /* |
| 564 | * We have to generate ser1 first, because Linux takes the first |
| 565 | * device it finds in the dt as serial output device. And we generate |
| 566 | * devices in reverse order to the dt. |
| 567 | */ |
| 568 | if (serial_hd(1)) { |
| 569 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
| 570 | soc, pmc->clock_freq, mpic, "serial1", 1, false); |
| 571 | } |
| 572 | |
| 573 | if (serial_hd(0)) { |
| 574 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
| 575 | soc, pmc->clock_freq, mpic, "serial0", 0, true); |
| 576 | } |
| 577 | |
| 578 | /* i2c */ |
| 579 | dt_i2c_create(fdt, soc, mpic, "i2c"); |
| 580 | |
| 581 | dt_rtc_create(fdt, "i2c", "rtc"); |
| 582 | |
| 583 | /* sdhc */ |
| 584 | if (pmc->has_esdhc) { |
| 585 | dt_sdhc_create(fdt, soc, mpic); |
| 586 | } |
| 587 | |
| 588 | gutil = g_strdup_printf("%s/global-utilities@%llx", soc, |
| 589 | MPC8544_UTIL_OFFSET); |
| 590 | qemu_fdt_add_subnode(fdt, gutil); |
| 591 | qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); |
| 592 | qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); |
| 593 | qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); |
| 594 | g_free(gutil); |
| 595 | |
| 596 | msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
| 597 | qemu_fdt_add_subnode(fdt, msi); |
| 598 | qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); |
| 599 | qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); |
| 600 | msi_ph = qemu_fdt_alloc_phandle(fdt); |
| 601 | qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); |
| 602 | qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); |
| 603 | qemu_fdt_setprop_cells(fdt, msi, "interrupts", |
| 604 | 0xe0, 0x0, |
| 605 | 0xe1, 0x0, |
| 606 | 0xe2, 0x0, |
| 607 | 0xe3, 0x0, |
| 608 | 0xe4, 0x0, |
| 609 | 0xe5, 0x0, |
| 610 | 0xe6, 0x0, |
| 611 | 0xe7, 0x0); |
| 612 | qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); |
| 613 | qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); |
| 614 | g_free(msi); |
| 615 | |
| 616 | pci = g_strdup_printf("/pci@%llx", |
| 617 | pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); |
| 618 | qemu_fdt_add_subnode(fdt, pci); |
| 619 | qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); |
| 620 | qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); |
| 621 | qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); |
| 622 | qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, |
| 623 | 0x0, 0x7); |
| 624 | pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), |
| 625 | pmc->pci_first_slot, pmc->pci_nr_slots, |
| 626 | &len); |
| 627 | qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); |
| 628 | qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); |
| 629 | qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); |
| 630 | qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); |
| 631 | for (i = 0; i < 14; i++) { |
| 632 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
| 633 | } |
| 634 | qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
| 635 | qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); |
| 636 | qemu_fdt_setprop_cells(fdt, pci, "reg", |
| 637 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, |
| 638 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), |
| 639 | 0, 0x1000); |
| 640 | qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
| 641 | qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); |
| 642 | qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); |
| 643 | qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); |
| 644 | qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); |
| 645 | g_free(pci); |
| 646 | |
| 647 | if (pmc->has_mpc8xxx_gpio) { |
| 648 | create_dt_mpc8xxx_gpio(fdt, soc, mpic); |
| 649 | } |
| 650 | g_free(soc); |
| 651 | |
| 652 | platform_bus_create_devtree(pms, fdt, mpic); |
| 653 | |
| 654 | g_free(mpic); |
| 655 | |
| 656 | pmc->fixup_devtree(fdt); |
| 657 | |
| 658 | if (toplevel_compat) { |
| 659 | qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, |
| 660 | strlen(toplevel_compat) + 1); |
| 661 | } |
| 662 | |
| 663 | done: |
| 664 | if (!dry_run) { |
| 665 | physical_memory_write(addr, fdt, fdt_size); |
| 666 | |
| 667 | /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ |
| 668 | g_free(machine->fdt); |
| 669 | machine->fdt = fdt; |
| 670 | } else { |
| 671 | g_free(fdt); |
| 672 | } |
| 673 | ret = fdt_size; |
| 674 | |
| 675 | out: |
| 676 | g_free(pci_map); |
| 677 | |
| 678 | return ret; |
| 679 | } |
| 680 | |
| 681 | typedef struct DeviceTreeParams { |
| 682 | PPCE500MachineState *machine; |
| 683 | hwaddr addr; |
| 684 | hwaddr initrd_base; |
| 685 | hwaddr initrd_size; |
| 686 | hwaddr kernel_base; |
| 687 | hwaddr kernel_size; |
| 688 | Notifier notifier; |
| 689 | } DeviceTreeParams; |
| 690 | |
| 691 | static void ppce500_reset_device_tree(void *opaque) |
| 692 | { |
| 693 | DeviceTreeParams *p = opaque; |
| 694 | ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, |
| 695 | p->initrd_size, p->kernel_base, p->kernel_size, |
| 696 | false); |
| 697 | } |
| 698 | |
| 699 | static void ppce500_init_notify(Notifier *notifier, void *data) |
| 700 | { |
| 701 | DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); |
| 702 | ppce500_reset_device_tree(p); |
| 703 | } |
| 704 | |
| 705 | static int ppce500_prep_device_tree(PPCE500MachineState *machine, |
| 706 | hwaddr addr, |
| 707 | hwaddr initrd_base, |
| 708 | hwaddr initrd_size, |
| 709 | hwaddr kernel_base, |
| 710 | hwaddr kernel_size) |
| 711 | { |
| 712 | DeviceTreeParams *p = g_new(DeviceTreeParams, 1); |
| 713 | p->machine = machine; |
| 714 | p->addr = addr; |
| 715 | p->initrd_base = initrd_base; |
| 716 | p->initrd_size = initrd_size; |
| 717 | p->kernel_base = kernel_base; |
| 718 | p->kernel_size = kernel_size; |
| 719 | |
| 720 | qemu_register_reset_nosnapshotload(ppce500_reset_device_tree, p); |
| 721 | p->notifier.notify = ppce500_init_notify; |
| 722 | qemu_add_machine_init_done_notifier(&p->notifier); |
| 723 | |
| 724 | /* Issue the device tree loader once, so that we get the size of the blob */ |
| 725 | return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, |
| 726 | kernel_base, kernel_size, true); |
| 727 | } |
| 728 | |
| 729 | static hwaddr booke206_page_size_to_tlb(uint64_t size) |
| 730 | { |
| 731 | return 63 - clz64(size / KiB); |
| 732 | } |
| 733 | |
| 734 | void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa, |
| 735 | hwaddr len) |
| 736 | { |
| 737 | tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT; |
| 738 | tlb->mas1 |= MAS1_VALID; |
| 739 | tlb->mas2 = va & TARGET_PAGE_MASK; |
| 740 | tlb->mas7_3 = pa & TARGET_PAGE_MASK; |
| 741 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
| 742 | } |
| 743 | |
| 744 | static int booke206_initial_map_tsize(CPUPPCState *env) |
| 745 | { |
| 746 | struct boot_info *bi = env->load_info; |
| 747 | hwaddr dt_end; |
| 748 | int ps; |
| 749 | |
| 750 | /* Our initial TLB entry needs to cover everything from 0 to |
| 751 | the device tree top */ |
| 752 | dt_end = bi->dt_base + bi->dt_size; |
| 753 | ps = booke206_page_size_to_tlb(dt_end) + 1; |
| 754 | if (ps & 1) { |
| 755 | /* e500v2 can only do even TLB size bits */ |
| 756 | ps++; |
| 757 | } |
| 758 | return ps; |
| 759 | } |
| 760 | |
| 761 | static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) |
| 762 | { |
| 763 | int tsize; |
| 764 | |
| 765 | tsize = booke206_initial_map_tsize(env); |
| 766 | return (1ULL << 10 << tsize); |
| 767 | } |
| 768 | |
| 769 | static void ppce500_cpu_reset_sec(void *opaque) |
| 770 | { |
| 771 | PowerPCCPU *cpu = opaque; |
| 772 | CPUState *cs = CPU(cpu); |
| 773 | |
| 774 | cpu_reset(cs); |
| 775 | |
| 776 | cs->exception_index = EXCP_HLT; |
| 777 | } |
| 778 | |
| 779 | static void ppce500_cpu_reset(void *opaque) |
| 780 | { |
| 781 | PowerPCCPU *cpu = opaque; |
| 782 | CPUState *cs = CPU(cpu); |
| 783 | CPUPPCState *env = &cpu->env; |
| 784 | struct boot_info *bi = env->load_info; |
| 785 | uint64_t map_size = mmubooke_initial_mapsize(env); |
| 786 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
| 787 | |
| 788 | cpu_reset(cs); |
| 789 | |
| 790 | /* Set initial guest state. */ |
| 791 | cs->halted = 0; |
| 792 | env->gpr[1] = (16 * MiB) - 8; |
| 793 | env->gpr[3] = bi->dt_base; |
| 794 | env->gpr[4] = 0; |
| 795 | env->gpr[5] = 0; |
| 796 | env->gpr[6] = EPAPR_MAGIC; |
| 797 | env->gpr[7] = map_size; |
| 798 | env->gpr[8] = 0; |
| 799 | env->gpr[9] = 0; |
| 800 | env->nip = bi->entry; |
| 801 | /* create initial mapping */ |
| 802 | booke206_set_tlb(tlb, 0, 0, map_size); |
| 803 | #ifdef CONFIG_KVM |
| 804 | env->tlb_dirty = true; |
| 805 | #endif |
| 806 | } |
| 807 | |
| 808 | static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, |
| 809 | IrqLines *irqs) |
| 810 | { |
| 811 | DeviceState *dev; |
| 812 | SysBusDevice *s; |
| 813 | int i, j, k; |
| 814 | MachineState *machine = MACHINE(pms); |
| 815 | unsigned int smp_cpus = machine->smp.cpus; |
| 816 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
| 817 | |
| 818 | dev = qdev_new(TYPE_OPENPIC); |
| 819 | object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); |
| 820 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
| 821 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); |
| 822 | |
| 823 | s = SYS_BUS_DEVICE(dev); |
| 824 | sysbus_realize_and_unref(s, &error_fatal); |
| 825 | |
| 826 | k = 0; |
| 827 | for (i = 0; i < smp_cpus; i++) { |
| 828 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { |
| 829 | sysbus_connect_irq(s, k++, irqs[i].irq[j]); |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | return dev; |
| 834 | } |
| 835 | |
| 836 | static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, |
| 837 | Error **errp) |
| 838 | { |
| 839 | #ifdef CONFIG_KVM |
| 840 | DeviceState *dev; |
| 841 | CPUState *cs; |
| 842 | |
| 843 | dev = qdev_new(TYPE_KVM_OPENPIC); |
| 844 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
| 845 | |
| 846 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { |
| 847 | object_unparent(OBJECT(dev)); |
| 848 | return NULL; |
| 849 | } |
| 850 | |
| 851 | CPU_FOREACH(cs) { |
| 852 | if (kvm_openpic_connect_vcpu(dev, cs)) { |
| 853 | fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", |
| 854 | __func__); |
| 855 | abort(); |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | return dev; |
| 860 | #else |
| 861 | g_assert_not_reached(); |
| 862 | #endif |
| 863 | } |
| 864 | |
| 865 | static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, |
| 866 | MemoryRegion *ccsr, |
| 867 | IrqLines *irqs) |
| 868 | { |
| 869 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
| 870 | DeviceState *dev = NULL; |
| 871 | SysBusDevice *s; |
| 872 | |
| 873 | if (kvm_enabled()) { |
| 874 | Error *err = NULL; |
| 875 | |
| 876 | if (kvm_kernel_irqchip_allowed()) { |
| 877 | dev = ppce500_init_mpic_kvm(pmc, &err); |
| 878 | } |
| 879 | if (kvm_kernel_irqchip_required() && !dev) { |
| 880 | error_reportf_err(err, |
| 881 | "kernel_irqchip requested but unavailable: "); |
| 882 | exit(1); |
| 883 | } |
| 884 | } |
| 885 | |
| 886 | if (!dev) { |
| 887 | dev = ppce500_init_mpic_qemu(pms, irqs); |
| 888 | } |
| 889 | |
| 890 | s = SYS_BUS_DEVICE(dev); |
| 891 | memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, |
| 892 | s->mmio[0].memory); |
| 893 | |
| 894 | return dev; |
| 895 | } |
| 896 | |
| 897 | static void ppce500_power_off(void *opaque, int line, int on) |
| 898 | { |
| 899 | if (on) { |
| 900 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | void ppce500_init(MachineState *machine) |
| 905 | { |
| 906 | MemoryRegion *address_space_mem = get_system_memory(); |
| 907 | PPCE500MachineState *pms = PPCE500_MACHINE(machine); |
| 908 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); |
| 909 | MachineClass *mc = MACHINE_CLASS(pmc); |
| 910 | PCIBus *pci_bus; |
| 911 | CPUPPCState *env = NULL; |
| 912 | uint64_t loadaddr; |
| 913 | hwaddr kernel_base = -1LL; |
| 914 | int kernel_size = 0; |
| 915 | hwaddr dt_base = 0; |
| 916 | hwaddr initrd_base = 0; |
| 917 | int initrd_size = 0; |
| 918 | hwaddr cur_base = 0; |
| 919 | char *filename; |
| 920 | const char *payload_name; |
| 921 | bool kernel_as_payload; |
| 922 | hwaddr bios_entry = 0; |
| 923 | target_long payload_size; |
| 924 | struct boot_info *boot_info = NULL; |
| 925 | int dt_size; |
| 926 | int i; |
| 927 | unsigned int smp_cpus = machine->smp.cpus; |
| 928 | /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and |
| 929 | * 4 respectively */ |
| 930 | unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; |
| 931 | IrqLines *irqs; |
| 932 | DeviceState *dev, *mpicdev; |
| 933 | DriveInfo *dinfo; |
| 934 | CPUPPCState *firstenv = NULL; |
| 935 | MemoryRegion *ccsr_addr_space; |
| 936 | SysBusDevice *s; |
| 937 | I2CBus *i2c; |
| 938 | |
| 939 | irqs = g_new0(IrqLines, smp_cpus); |
| 940 | for (i = 0; i < smp_cpus; i++) { |
| 941 | PowerPCCPU *cpu; |
| 942 | CPUState *cs; |
| 943 | |
| 944 | cpu = POWERPC_CPU(object_new(machine->cpu_type)); |
| 945 | env = &cpu->env; |
| 946 | cs = CPU(cpu); |
| 947 | |
| 948 | if (!(POWERPC_CPU_GET_CLASS(cpu)->svr & POWERPC_SVR_E500)) { |
| 949 | error_report("This machine needs a CPU from the e500 family"); |
| 950 | exit(1); |
| 951 | } |
| 952 | |
| 953 | /* |
| 954 | * Secondary CPU starts in halted state for now. Needs to change |
| 955 | * when implementing non-kernel boot. |
| 956 | */ |
| 957 | object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, |
| 958 | &error_abort); |
| 959 | qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); |
| 960 | |
| 961 | if (!firstenv) { |
| 962 | firstenv = env; |
| 963 | } |
| 964 | |
| 965 | irqs[i].irq[OPENPIC_OUTPUT_INT] = |
| 966 | qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT); |
| 967 | irqs[i].irq[OPENPIC_OUTPUT_CINT] = |
| 968 | qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT); |
| 969 | env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; |
| 970 | env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; |
| 971 | |
| 972 | ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500); |
| 973 | |
| 974 | /* Register reset handler */ |
| 975 | if (!i) { |
| 976 | /* Primary CPU */ |
| 977 | boot_info = g_new0(struct boot_info, 1); |
| 978 | qemu_register_reset(ppce500_cpu_reset, cpu); |
| 979 | env->load_info = boot_info; |
| 980 | } else { |
| 981 | /* Secondary CPUs */ |
| 982 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
| 983 | } |
| 984 | } |
| 985 | |
| 986 | env = firstenv; |
| 987 | |
| 988 | if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { |
| 989 | error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); |
| 990 | exit(EXIT_FAILURE); |
| 991 | } |
| 992 | |
| 993 | /* Register Memory */ |
| 994 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
| 995 | |
| 996 | dev = qdev_new("e500-ccsr"); |
| 997 | s = SYS_BUS_DEVICE(dev); |
| 998 | object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev)); |
| 999 | sysbus_realize_and_unref(s, &error_fatal); |
| 1000 | ccsr_addr_space = sysbus_mmio_get_region(s, 0); |
| 1001 | memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, |
| 1002 | ccsr_addr_space); |
| 1003 | |
| 1004 | mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); |
| 1005 | g_free(irqs); |
| 1006 | |
| 1007 | /* Serial */ |
| 1008 | if (serial_hd(0)) { |
| 1009 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
| 1010 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
| 1011 | serial_hd(0), DEVICE_BIG_ENDIAN); |
| 1012 | } |
| 1013 | |
| 1014 | if (serial_hd(1)) { |
| 1015 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
| 1016 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
| 1017 | serial_hd(1), DEVICE_BIG_ENDIAN); |
| 1018 | } |
| 1019 | |
| 1020 | /* I2C */ |
| 1021 | dev = qdev_new("mpc-i2c"); |
| 1022 | s = SYS_BUS_DEVICE(dev); |
| 1023 | sysbus_realize_and_unref(s, &error_fatal); |
| 1024 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); |
| 1025 | memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, |
| 1026 | sysbus_mmio_get_region(s, 0)); |
| 1027 | i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c")); |
| 1028 | i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); |
| 1029 | |
| 1030 | /* eSDHC */ |
| 1031 | if (pmc->has_esdhc) { |
| 1032 | dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); |
| 1033 | qdev_prop_set_string(dev, "name", "esdhc"); |
| 1034 | qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE); |
| 1035 | s = SYS_BUS_DEVICE(dev); |
| 1036 | sysbus_realize_and_unref(s, &error_fatal); |
| 1037 | memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, |
| 1038 | sysbus_mmio_get_region(s, 0)); |
| 1039 | |
| 1040 | dev = qdev_new(TYPE_FSL_ESDHC_BE); |
| 1041 | s = SYS_BUS_DEVICE(dev); |
| 1042 | sysbus_realize_and_unref(s, &error_fatal); |
| 1043 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ)); |
| 1044 | memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, |
| 1045 | sysbus_mmio_get_region(s, 0)); |
| 1046 | } |
| 1047 | |
| 1048 | /* General Utility device */ |
| 1049 | dev = qdev_new("mpc8544-guts"); |
| 1050 | s = SYS_BUS_DEVICE(dev); |
| 1051 | sysbus_realize_and_unref(s, &error_fatal); |
| 1052 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
| 1053 | sysbus_mmio_get_region(s, 0)); |
| 1054 | |
| 1055 | /* PCI */ |
| 1056 | dev = qdev_new("e500-pcihost"); |
| 1057 | object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev)); |
| 1058 | qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); |
| 1059 | qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); |
| 1060 | s = SYS_BUS_DEVICE(dev); |
| 1061 | sysbus_realize_and_unref(s, &error_fatal); |
| 1062 | for (i = 0; i < PCI_NUM_PINS; i++) { |
| 1063 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); |
| 1064 | } |
| 1065 | |
| 1066 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
| 1067 | sysbus_mmio_get_region(s, 0)); |
| 1068 | |
| 1069 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
| 1070 | if (!pci_bus) |
| 1071 | printf("couldn't create PCI controller!\n"); |
| 1072 | |
| 1073 | if (pci_bus) { |
| 1074 | /* Register network interfaces. */ |
| 1075 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 1076 | } |
| 1077 | |
| 1078 | /* Register spinning region */ |
| 1079 | sysbus_create_simple("e500-spin", pmc->spin_base, NULL); |
| 1080 | |
| 1081 | if (pmc->has_mpc8xxx_gpio) { |
| 1082 | qemu_irq poweroff_irq; |
| 1083 | |
| 1084 | dev = qdev_new("mpc8xxx_gpio"); |
| 1085 | s = SYS_BUS_DEVICE(dev); |
| 1086 | sysbus_realize_and_unref(s, &error_fatal); |
| 1087 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); |
| 1088 | memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, |
| 1089 | sysbus_mmio_get_region(s, 0)); |
| 1090 | |
| 1091 | /* Power Off GPIO at Pin 0 */ |
| 1092 | poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); |
| 1093 | qdev_connect_gpio_out(dev, 0, poweroff_irq); |
| 1094 | } |
| 1095 | |
| 1096 | /* Platform Bus Device */ |
| 1097 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
| 1098 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); |
| 1099 | qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); |
| 1100 | qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); |
| 1101 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 1102 | pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); |
| 1103 | |
| 1104 | s = SYS_BUS_DEVICE(pms->pbus_dev); |
| 1105 | for (i = 0; i < pmc->platform_bus_num_irqs; i++) { |
| 1106 | int irqn = pmc->platform_bus_first_irq + i; |
| 1107 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); |
| 1108 | } |
| 1109 | |
| 1110 | memory_region_add_subregion(address_space_mem, |
| 1111 | pmc->platform_bus_base, |
| 1112 | &pms->pbus_dev->mmio); |
| 1113 | |
| 1114 | dinfo = drive_get(IF_PFLASH, 0, 0); |
| 1115 | if (dinfo) { |
| 1116 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); |
| 1117 | BlockDriverState *bs = blk_bs(blk); |
| 1118 | uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio); |
| 1119 | uint64_t size = bdrv_getlength(bs); |
| 1120 | uint32_t sector_len = 64 * KiB; |
| 1121 | |
| 1122 | if (!is_power_of_2(size)) { |
| 1123 | error_report("Size of pflash file must be a power of two."); |
| 1124 | exit(1); |
| 1125 | } |
| 1126 | |
| 1127 | if (size > mmio_size) { |
| 1128 | error_report("Size of pflash file must not be bigger than %" PRIu64 |
| 1129 | " bytes.", mmio_size); |
| 1130 | exit(1); |
| 1131 | } |
| 1132 | |
| 1133 | if (!QEMU_IS_ALIGNED(size, sector_len)) { |
| 1134 | error_report("Size of pflash file must be a multiple of %" PRIu32 |
| 1135 | ".", sector_len); |
| 1136 | exit(1); |
| 1137 | } |
| 1138 | |
| 1139 | dev = qdev_new(TYPE_PFLASH_CFI01); |
| 1140 | qdev_prop_set_drive(dev, "drive", blk); |
| 1141 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); |
| 1142 | qdev_prop_set_uint64(dev, "sector-length", sector_len); |
| 1143 | qdev_prop_set_uint8(dev, "width", 2); |
| 1144 | qdev_prop_set_bit(dev, "big-endian", true); |
| 1145 | qdev_prop_set_uint16(dev, "id0", 0x89); |
| 1146 | qdev_prop_set_uint16(dev, "id1", 0x18); |
| 1147 | qdev_prop_set_uint16(dev, "id2", 0x0000); |
| 1148 | qdev_prop_set_uint16(dev, "id3", 0x0); |
| 1149 | qdev_prop_set_string(dev, "name", "e500.flash"); |
| 1150 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 1151 | |
| 1152 | memory_region_add_subregion(&pms->pbus_dev->mmio, 0, |
| 1153 | pflash_cfi01_get_memory(PFLASH_CFI01(dev))); |
| 1154 | } |
| 1155 | |
| 1156 | /* |
| 1157 | * Smart firmware defaults ahead! |
| 1158 | * |
| 1159 | * We follow the following table to select which payload we execute. |
| 1160 | * |
| 1161 | * -kernel | -bios | payload |
| 1162 | * ---------+-------+--------- |
| 1163 | * N | Y | u-boot |
| 1164 | * N | N | u-boot |
| 1165 | * Y | Y | u-boot |
| 1166 | * Y | N | kernel |
| 1167 | * |
| 1168 | * This ensures backwards compatibility with how we used to expose |
| 1169 | * -kernel to users but allows them to run through u-boot as well. |
| 1170 | */ |
| 1171 | kernel_as_payload = false; |
| 1172 | if (machine->firmware == NULL) { |
| 1173 | if (machine->kernel_filename) { |
| 1174 | payload_name = machine->kernel_filename; |
| 1175 | kernel_as_payload = true; |
| 1176 | } else { |
| 1177 | payload_name = "u-boot.e500"; |
| 1178 | } |
| 1179 | } else { |
| 1180 | payload_name = machine->firmware; |
| 1181 | } |
| 1182 | |
| 1183 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); |
| 1184 | if (!filename) { |
| 1185 | error_report("could not find firmware/kernel file '%s'", payload_name); |
| 1186 | exit(1); |
| 1187 | } |
| 1188 | |
| 1189 | payload_size = load_elf(filename, NULL, NULL, NULL, |
| 1190 | &bios_entry, &loadaddr, NULL, NULL, |
| 1191 | ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 1192 | if (payload_size < 0) { |
| 1193 | /* |
| 1194 | * Hrm. No ELF image? Try a uImage, maybe someone is giving us an |
| 1195 | * ePAPR compliant kernel |
| 1196 | */ |
| 1197 | loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
| 1198 | payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, |
| 1199 | NULL, NULL); |
| 1200 | if (payload_size < 0) { |
| 1201 | error_report("could not load firmware '%s'", filename); |
| 1202 | exit(1); |
| 1203 | } |
| 1204 | } |
| 1205 | |
| 1206 | g_free(filename); |
| 1207 | |
| 1208 | if (kernel_as_payload) { |
| 1209 | kernel_base = loadaddr; |
| 1210 | kernel_size = payload_size; |
| 1211 | } |
| 1212 | |
| 1213 | cur_base = loadaddr + payload_size; |
| 1214 | if (cur_base < 32 * MiB) { |
| 1215 | /* u-boot occupies memory up to 32MB, so load blobs above */ |
| 1216 | cur_base = 32 * MiB; |
| 1217 | } |
| 1218 | |
| 1219 | /* Load bare kernel only if no bios/u-boot has been provided */ |
| 1220 | if (machine->kernel_filename && !kernel_as_payload) { |
| 1221 | kernel_base = cur_base; |
| 1222 | kernel_size = load_image_targphys(machine->kernel_filename, |
| 1223 | cur_base, machine->ram_size - cur_base, |
| 1224 | &error_fatal); |
| 1225 | cur_base += kernel_size; |
| 1226 | } |
| 1227 | |
| 1228 | /* Load initrd. */ |
| 1229 | if (machine->initrd_filename) { |
| 1230 | initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
| 1231 | initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, |
| 1232 | machine->ram_size - initrd_base, |
| 1233 | &error_fatal); |
| 1234 | cur_base = initrd_base + initrd_size; |
| 1235 | } |
| 1236 | |
| 1237 | /* |
| 1238 | * Reserve space for dtb behind the kernel image because Linux has a bug |
| 1239 | * where it can only handle the dtb if it's within the first 64MB of where |
| 1240 | * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD |
| 1241 | * ensures enough space between kernel and initrd. |
| 1242 | */ |
| 1243 | dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
| 1244 | if (dt_base + DTB_MAX_SIZE > machine->ram_size) { |
| 1245 | error_report("not enough memory for device tree"); |
| 1246 | exit(1); |
| 1247 | } |
| 1248 | |
| 1249 | dt_size = ppce500_prep_device_tree(pms, dt_base, |
| 1250 | initrd_base, initrd_size, |
| 1251 | kernel_base, kernel_size); |
| 1252 | if (dt_size < 0) { |
| 1253 | error_report("couldn't load device tree"); |
| 1254 | exit(1); |
| 1255 | } |
| 1256 | assert(dt_size < DTB_MAX_SIZE); |
| 1257 | |
| 1258 | boot_info->entry = bios_entry; |
| 1259 | boot_info->dt_base = dt_base; |
| 1260 | boot_info->dt_size = dt_size; |
| 1261 | } |
| 1262 | |
| 1263 | static void e500_ccsr_initfn(Object *obj) |
| 1264 | { |
| 1265 | PPCE500CCSRState *ccsr = CCSR(obj); |
| 1266 | memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", |
| 1267 | MPC8544_CCSRBAR_SIZE); |
| 1268 | sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); |
| 1269 | } |
| 1270 | |
| 1271 | static const TypeInfo e500_ccsr_info = { |
| 1272 | .name = TYPE_CCSR, |
| 1273 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1274 | .instance_size = sizeof(PPCE500CCSRState), |
| 1275 | .instance_init = e500_ccsr_initfn, |
| 1276 | }; |
| 1277 | |
| 1278 | static const TypeInfo ppce500_info = { |
| 1279 | .name = TYPE_PPCE500_MACHINE, |
| 1280 | .parent = TYPE_MACHINE, |
| 1281 | .abstract = true, |
| 1282 | .instance_size = sizeof(PPCE500MachineState), |
| 1283 | .class_size = sizeof(PPCE500MachineClass), |
| 1284 | }; |
| 1285 | |
| 1286 | static void e500_register_types(void) |
| 1287 | { |
| 1288 | type_register_static(&e500_ccsr_info); |
| 1289 | type_register_static(&ppce500_info); |
| 1290 | } |
| 1291 | |
| 1292 | type_init(e500_register_types) |