| 1 | /* |
| 2 | * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2004-2007 Fabrice Bellard |
| 5 | * Copyright (c) 2007 Jocelyn Mayer |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | * |
| 25 | * PCI bus layout on a real G5 (U3 based): |
| 26 | * |
| 27 | * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] |
| 28 | * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] |
| 29 | * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] |
| 30 | * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) |
| 31 | * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) |
| 32 | * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] |
| 33 | * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] |
| 34 | * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] |
| 35 | * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] |
| 36 | * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] |
| 37 | * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) |
| 38 | * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] |
| 39 | * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] |
| 40 | * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) |
| 41 | * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) |
| 42 | * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) |
| 43 | * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] |
| 44 | * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] |
| 45 | * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] |
| 46 | * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] |
| 47 | */ |
| 48 | |
| 49 | #include "qemu/osdep.h" |
| 50 | #include "qemu/datadir.h" |
| 51 | #include "qemu/units.h" |
| 52 | #include "qapi/error.h" |
| 53 | #include "exec/target_page.h" |
| 54 | #include "hw/ppc/ppc.h" |
| 55 | #include "hw/core/qdev-properties.h" |
| 56 | #include "hw/nvram/mac_nvram.h" |
| 57 | #include "hw/core/boards.h" |
| 58 | #include "hw/pci-host/uninorth.h" |
| 59 | #include "hw/input/adb.h" |
| 60 | #include "hw/ppc/mac_dbdma.h" |
| 61 | #include "hw/pci/pci.h" |
| 62 | #include "net/net.h" |
| 63 | #include "system/system.h" |
| 64 | #include "hw/nvram/fw_cfg.h" |
| 65 | #include "hw/char/escc.h" |
| 66 | #include "hw/misc/macio/macio.h" |
| 67 | #include "hw/ppc/openpic.h" |
| 68 | #include "hw/core/loader.h" |
| 69 | #include "hw/core/fw-path-provider.h" |
| 70 | #include "elf.h" |
| 71 | #include "qemu/error-report.h" |
| 72 | #include "system/kvm.h" |
| 73 | #include "system/reset.h" |
| 74 | #include "kvm_ppc.h" |
| 75 | #include "hw/usb/usb.h" |
| 76 | #include "hw/core/sysbus.h" |
| 77 | #include "trace.h" |
| 78 | |
| 79 | #define MAX_IDE_BUS 2 |
| 80 | #define CFG_ADDR 0xf0000510 |
| 81 | #define TBFREQ (25UL * 1000UL * 1000UL) |
| 82 | #define CLOCKFREQ (900UL * 1000UL * 1000UL) |
| 83 | #define BUSFREQ (100UL * 1000UL * 1000UL) |
| 84 | |
| 85 | #define NDRV_VGA_FILENAME "qemu_vga.ndrv" |
| 86 | |
| 87 | #define PROM_FILENAME "openbios-ppc" |
| 88 | #define PROM_BASE 0xfff00000 |
| 89 | #define PROM_SIZE (1 * MiB) |
| 90 | |
| 91 | #define KERNEL_LOAD_ADDR 0x01000000 |
| 92 | #define KERNEL_GAP 0x00100000 |
| 93 | |
| 94 | #define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99") |
| 95 | typedef struct Core99MachineState Core99MachineState; |
| 96 | DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE, |
| 97 | TYPE_CORE99_MACHINE) |
| 98 | |
| 99 | typedef enum { |
| 100 | CORE99_VIA_CONFIG_CUDA = 0, |
| 101 | CORE99_VIA_CONFIG_PMU, |
| 102 | CORE99_VIA_CONFIG_PMU_ADB |
| 103 | } Core99ViaConfig; |
| 104 | |
| 105 | struct Core99MachineState { |
| 106 | /*< private >*/ |
| 107 | MachineState parent; |
| 108 | |
| 109 | Core99ViaConfig via_config; |
| 110 | }; |
| 111 | |
| 112 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 113 | Error **errp) |
| 114 | { |
| 115 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 116 | } |
| 117 | |
| 118 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
| 119 | { |
| 120 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
| 121 | } |
| 122 | |
| 123 | static void ppc_core99_reset(void *opaque) |
| 124 | { |
| 125 | PowerPCCPU *cpu = opaque; |
| 126 | |
| 127 | cpu_reset(CPU(cpu)); |
| 128 | /* 970 CPUs want to get their initial IP as part of their boot protocol */ |
| 129 | cpu->env.nip = PROM_BASE + 0x100; |
| 130 | } |
| 131 | |
| 132 | /* PowerPC Mac99 hardware initialisation */ |
| 133 | static void ppc_core99_init(MachineState *machine) |
| 134 | { |
| 135 | Core99MachineState *core99_machine = CORE99_MACHINE(machine); |
| 136 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 137 | PowerPCCPU *cpu = NULL; |
| 138 | CPUPPCState *env = NULL; |
| 139 | char *filename; |
| 140 | IrqLines *openpic_irqs; |
| 141 | int i, j, k, ppc_boot_device, machine_arch, bios_size = -1; |
| 142 | const char *bios_name = machine->firmware ?: PROM_FILENAME; |
| 143 | MemoryRegion *bios = g_new(MemoryRegion, 1); |
| 144 | hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0; |
| 145 | long kernel_size = 0, initrd_size = 0; |
| 146 | PCIBus *pci_bus; |
| 147 | bool has_pmu, has_adb; |
| 148 | Object *macio; |
| 149 | MACIOIDEState *macio_ide; |
| 150 | BusState *adb_bus; |
| 151 | MacIONVRAMState *nvr; |
| 152 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 153 | void *fw_cfg; |
| 154 | SysBusDevice *s; |
| 155 | DeviceState *dev, *pic_dev, *uninorth_pci_dev; |
| 156 | DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; |
| 157 | hwaddr nvram_addr = 0xFFF04000; |
| 158 | uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; |
| 159 | |
| 160 | /* init CPUs */ |
| 161 | for (i = 0; i < machine->smp.cpus; i++) { |
| 162 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
| 163 | env = &cpu->env; |
| 164 | |
| 165 | /* Set time-base frequency to 100 Mhz */ |
| 166 | cpu_ppc_tb_init(env, TBFREQ); |
| 167 | qemu_register_reset(ppc_core99_reset, cpu); |
| 168 | } |
| 169 | |
| 170 | /* allocate RAM */ |
| 171 | if (machine->ram_size > 2 * GiB) { |
| 172 | error_report("RAM size more than 2 GiB is not supported"); |
| 173 | exit(1); |
| 174 | } |
| 175 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
| 176 | |
| 177 | /* allocate and load firmware ROM */ |
| 178 | memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, |
| 179 | &error_fatal); |
| 180 | memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); |
| 181 | |
| 182 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 183 | if (filename) { |
| 184 | /* Load OpenBIOS (ELF) */ |
| 185 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, |
| 186 | NULL, NULL, NULL, |
| 187 | ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 188 | |
| 189 | if (bios_size <= 0) { |
| 190 | /* or load binary ROM image */ |
| 191 | bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE, |
| 192 | &error_fatal); |
| 193 | } |
| 194 | g_free(filename); |
| 195 | } |
| 196 | if (bios_size < 0 || bios_size > PROM_SIZE) { |
| 197 | error_report("could not load PowerPC bios '%s'", bios_name); |
| 198 | exit(1); |
| 199 | } |
| 200 | |
| 201 | if (machine->kernel_filename) { |
| 202 | kernel_base = KERNEL_LOAD_ADDR; |
| 203 | kernel_size = load_elf(machine->kernel_filename, NULL, |
| 204 | translate_kernel_address, NULL, NULL, NULL, |
| 205 | NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 206 | if (kernel_size < 0) { |
| 207 | kernel_size = load_aout(machine->kernel_filename, kernel_base, |
| 208 | machine->ram_size - kernel_base, |
| 209 | true, TARGET_PAGE_SIZE); |
| 210 | } |
| 211 | if (kernel_size < 0) { |
| 212 | kernel_size = load_image_targphys(machine->kernel_filename, |
| 213 | kernel_base, |
| 214 | machine->ram_size - kernel_base, |
| 215 | &error_fatal); |
| 216 | } |
| 217 | /* load initrd */ |
| 218 | if (machine->initrd_filename) { |
| 219 | initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); |
| 220 | initrd_size = load_image_targphys(machine->initrd_filename, |
| 221 | initrd_base, |
| 222 | machine->ram_size - initrd_base, |
| 223 | &error_fatal); |
| 224 | cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); |
| 225 | } else { |
| 226 | cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); |
| 227 | } |
| 228 | ppc_boot_device = 'm'; |
| 229 | } else { |
| 230 | ppc_boot_device = '\0'; |
| 231 | /* We consider that NewWorld PowerMac never have any floppy drive |
| 232 | * For now, OHW cannot boot from the network. |
| 233 | */ |
| 234 | for (i = 0; machine->boot_config.order[i] != '\0'; i++) { |
| 235 | if (machine->boot_config.order[i] >= 'c' && |
| 236 | machine->boot_config.order[i] <= 'f') { |
| 237 | ppc_boot_device = machine->boot_config.order[i]; |
| 238 | break; |
| 239 | } |
| 240 | } |
| 241 | if (ppc_boot_device == '\0') { |
| 242 | error_report("No valid boot device for Mac99 machine"); |
| 243 | exit(1); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | openpic_irqs = g_new0(IrqLines, machine->smp.cpus); |
| 248 | dev = DEVICE(cpu); |
| 249 | for (i = 0; i < machine->smp.cpus; i++) { |
| 250 | /* Mac99 IRQ connection between OpenPIC outputs pins |
| 251 | * and PowerPC input pins |
| 252 | */ |
| 253 | switch (PPC_INPUT(env)) { |
| 254 | case PPC_FLAGS_INPUT_6xx: |
| 255 | openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = |
| 256 | qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); |
| 257 | openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = |
| 258 | qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); |
| 259 | openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = |
| 260 | qdev_get_gpio_in(dev, PPC6xx_INPUT_MCP); |
| 261 | /* Not connected ? */ |
| 262 | openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; |
| 263 | /* Check this */ |
| 264 | openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = |
| 265 | qdev_get_gpio_in(dev, PPC6xx_INPUT_HRESET); |
| 266 | break; |
| 267 | #if defined(TARGET_PPC64) |
| 268 | case PPC_FLAGS_INPUT_970: |
| 269 | openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = |
| 270 | qdev_get_gpio_in(dev, PPC970_INPUT_INT); |
| 271 | openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = |
| 272 | qdev_get_gpio_in(dev, PPC970_INPUT_INT); |
| 273 | openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = |
| 274 | qdev_get_gpio_in(dev, PPC970_INPUT_MCP); |
| 275 | /* Not connected ? */ |
| 276 | openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; |
| 277 | /* Check this */ |
| 278 | openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = |
| 279 | qdev_get_gpio_in(dev, PPC970_INPUT_HRESET); |
| 280 | break; |
| 281 | #endif /* defined(TARGET_PPC64) */ |
| 282 | default: |
| 283 | error_report("Bus model not supported on mac99 machine"); |
| 284 | exit(1); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /* UniN init */ |
| 289 | s = SYS_BUS_DEVICE(qdev_new(TYPE_UNI_NORTH)); |
| 290 | sysbus_realize_and_unref(s, &error_fatal); |
| 291 | memory_region_add_subregion(get_system_memory(), 0xf8000000, |
| 292 | sysbus_mmio_get_region(s, 0)); |
| 293 | |
| 294 | if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { |
| 295 | machine_arch = ARCH_MAC99_U3; |
| 296 | /* 970 gets a U3 bus */ |
| 297 | /* Uninorth AGP bus */ |
| 298 | uninorth_pci_dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); |
| 299 | s = SYS_BUS_DEVICE(uninorth_pci_dev); |
| 300 | sysbus_realize_and_unref(s, &error_fatal); |
| 301 | sysbus_mmio_map(s, 0, 0xf0800000); |
| 302 | sysbus_mmio_map(s, 1, 0xf0c00000); |
| 303 | /* PCI hole */ |
| 304 | memory_region_add_subregion(get_system_memory(), 0x80000000, |
| 305 | sysbus_mmio_get_region(s, 2)); |
| 306 | /* Register 8 MB of ISA IO space */ |
| 307 | memory_region_add_subregion(get_system_memory(), 0xf2000000, |
| 308 | sysbus_mmio_get_region(s, 3)); |
| 309 | } else { |
| 310 | machine_arch = ARCH_MAC99; |
| 311 | /* Use values found on a real PowerMac */ |
| 312 | /* Uninorth AGP bus */ |
| 313 | uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); |
| 314 | s = SYS_BUS_DEVICE(uninorth_agp_dev); |
| 315 | sysbus_realize_and_unref(s, &error_fatal); |
| 316 | sysbus_mmio_map(s, 0, 0xf0800000); |
| 317 | sysbus_mmio_map(s, 1, 0xf0c00000); |
| 318 | |
| 319 | /* Uninorth internal bus */ |
| 320 | uninorth_internal_dev = qdev_new( |
| 321 | TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); |
| 322 | s = SYS_BUS_DEVICE(uninorth_internal_dev); |
| 323 | sysbus_realize_and_unref(s, &error_fatal); |
| 324 | sysbus_mmio_map(s, 0, 0xf4800000); |
| 325 | sysbus_mmio_map(s, 1, 0xf4c00000); |
| 326 | |
| 327 | /* Uninorth main bus - this must be last to make it the default */ |
| 328 | uninorth_pci_dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); |
| 329 | qdev_prop_set_uint32(uninorth_pci_dev, "ofw-addr", 0xf2000000); |
| 330 | s = SYS_BUS_DEVICE(uninorth_pci_dev); |
| 331 | sysbus_realize_and_unref(s, &error_fatal); |
| 332 | sysbus_mmio_map(s, 0, 0xf2800000); |
| 333 | sysbus_mmio_map(s, 1, 0xf2c00000); |
| 334 | /* PCI hole */ |
| 335 | memory_region_add_subregion(get_system_memory(), 0x80000000, |
| 336 | sysbus_mmio_get_region(s, 2)); |
| 337 | /* Register 8 MB of ISA IO space */ |
| 338 | memory_region_add_subregion(get_system_memory(), 0xf2000000, |
| 339 | sysbus_mmio_get_region(s, 3)); |
| 340 | } |
| 341 | |
| 342 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
| 343 | has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); |
| 344 | has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || |
| 345 | core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); |
| 346 | |
| 347 | /* init basic PC hardware */ |
| 348 | pci_bus = PCI_HOST_BRIDGE(uninorth_pci_dev)->bus; |
| 349 | |
| 350 | /* MacIO */ |
| 351 | macio = OBJECT(pci_new(-1, TYPE_NEWWORLD_MACIO)); |
| 352 | dev = DEVICE(macio); |
| 353 | qdev_prop_set_uint64(dev, "frequency", tbfreq); |
| 354 | qdev_prop_set_bit(dev, "has-pmu", has_pmu); |
| 355 | qdev_prop_set_bit(dev, "has-adb", has_adb); |
| 356 | |
| 357 | dev = DEVICE(object_resolve_path_component(macio, "escc")); |
| 358 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); |
| 359 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
| 360 | |
| 361 | pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); |
| 362 | |
| 363 | pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); |
| 364 | for (i = 0; i < 4; i++) { |
| 365 | qdev_connect_gpio_out(uninorth_pci_dev, i, |
| 366 | qdev_get_gpio_in(pic_dev, 0x1b + i)); |
| 367 | } |
| 368 | |
| 369 | /* TODO: additional PCI buses only wired up for 32-bit machines */ |
| 370 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { |
| 371 | /* Uninorth AGP bus */ |
| 372 | for (i = 0; i < 4; i++) { |
| 373 | qdev_connect_gpio_out(uninorth_agp_dev, i, |
| 374 | qdev_get_gpio_in(pic_dev, 0x1b + i)); |
| 375 | } |
| 376 | |
| 377 | /* Uninorth internal bus */ |
| 378 | for (i = 0; i < 4; i++) { |
| 379 | qdev_connect_gpio_out(uninorth_internal_dev, i, |
| 380 | qdev_get_gpio_in(pic_dev, 0x1b + i)); |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | /* OpenPIC */ |
| 385 | s = SYS_BUS_DEVICE(pic_dev); |
| 386 | k = 0; |
| 387 | for (i = 0; i < machine->smp.cpus; i++) { |
| 388 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { |
| 389 | sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); |
| 390 | } |
| 391 | } |
| 392 | g_free(openpic_irqs); |
| 393 | |
| 394 | /* We only emulate 2 out of 3 IDE controllers for now */ |
| 395 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
| 396 | |
| 397 | macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); |
| 398 | macio_ide_init_drives(macio_ide, hd); |
| 399 | |
| 400 | macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); |
| 401 | macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); |
| 402 | |
| 403 | if (has_adb) { |
| 404 | if (has_pmu) { |
| 405 | dev = DEVICE(object_resolve_path_component(macio, "pmu")); |
| 406 | } else { |
| 407 | dev = DEVICE(object_resolve_path_component(macio, "cuda")); |
| 408 | } |
| 409 | |
| 410 | adb_bus = qdev_get_child_bus(dev, "adb.0"); |
| 411 | dev = qdev_new(TYPE_ADB_KEYBOARD); |
| 412 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); |
| 413 | |
| 414 | dev = qdev_new(TYPE_ADB_MOUSE); |
| 415 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); |
| 416 | } |
| 417 | |
| 418 | if (machine->usb) { |
| 419 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
| 420 | |
| 421 | /* U3 needs to use USB for input because Linux doesn't support via-cuda |
| 422 | on PPC64 */ |
| 423 | if (!has_adb || machine_arch == ARCH_MAC99_U3) { |
| 424 | USBBus *usb_bus; |
| 425 | |
| 426 | usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, |
| 427 | &error_abort)); |
| 428 | usb_create_simple(usb_bus, "usb-kbd"); |
| 429 | usb_create_simple(usb_bus, "usb-mouse"); |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | pci_vga_init(pci_bus); |
| 434 | |
| 435 | if (!graphic_width) { |
| 436 | graphic_width = 800; |
| 437 | } |
| 438 | if (!graphic_height) { |
| 439 | graphic_height = 600; |
| 440 | } |
| 441 | if (!graphic_depth) { |
| 442 | graphic_depth = 32; |
| 443 | } |
| 444 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { |
| 445 | graphic_depth = 15; |
| 446 | } |
| 447 | |
| 448 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 449 | |
| 450 | /* The NewWorld NVRAM is not located in the MacIO device */ |
| 451 | if (kvm_enabled() && qemu_real_host_page_size() > 4096) { |
| 452 | /* We can't combine read-write and read-only in a single page, so |
| 453 | move the NVRAM out of ROM again for KVM */ |
| 454 | nvram_addr = 0xFFE00000; |
| 455 | } |
| 456 | dev = qdev_new(TYPE_MACIO_NVRAM); |
| 457 | qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE); |
| 458 | qdev_prop_set_uint32(dev, "it_shift", 1); |
| 459 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 460 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); |
| 461 | nvr = MACIO_NVRAM(dev); |
| 462 | pmac_format_nvram_partition(nvr, MACIO_NVRAM_SIZE); |
| 463 | /* No PCI init: the BIOS will do it */ |
| 464 | |
| 465 | dev = qdev_new(TYPE_FW_CFG_MEM); |
| 466 | fw_cfg = FW_CFG(dev); |
| 467 | qdev_prop_set_uint32(dev, "data_width", 1); |
| 468 | qdev_prop_set_bit(dev, "dma_enabled", false); |
| 469 | object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); |
| 470 | s = SYS_BUS_DEVICE(dev); |
| 471 | sysbus_realize_and_unref(s, &error_fatal); |
| 472 | sysbus_mmio_map(s, 0, CFG_ADDR); |
| 473 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); |
| 474 | |
| 475 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); |
| 476 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
| 477 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
| 478 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); |
| 479 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
| 480 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 481 | if (machine->kernel_cmdline) { |
| 482 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); |
| 483 | pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, |
| 484 | machine->kernel_cmdline); |
| 485 | } else { |
| 486 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); |
| 487 | } |
| 488 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); |
| 489 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 490 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); |
| 491 | |
| 492 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); |
| 493 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); |
| 494 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); |
| 495 | |
| 496 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); |
| 497 | |
| 498 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); |
| 499 | if (kvm_enabled()) { |
| 500 | uint8_t *hypercall; |
| 501 | |
| 502 | hypercall = g_malloc(16); |
| 503 | kvmppc_get_hypercall(env, hypercall, 16); |
| 504 | fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); |
| 505 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); |
| 506 | } |
| 507 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); |
| 508 | /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ |
| 509 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); |
| 510 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); |
| 511 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); |
| 512 | |
| 513 | /* MacOS NDRV VGA driver */ |
| 514 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); |
| 515 | if (filename) { |
| 516 | gchar *ndrv_file; |
| 517 | gsize ndrv_size; |
| 518 | |
| 519 | if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { |
| 520 | fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); |
| 521 | } |
| 522 | g_free(filename); |
| 523 | } |
| 524 | |
| 525 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 526 | } |
| 527 | |
| 528 | /* |
| 529 | * Implementation of an interface to adjust firmware path |
| 530 | * for the bootindex property handling. |
| 531 | */ |
| 532 | static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, |
| 533 | DeviceState *dev) |
| 534 | { |
| 535 | PCIDevice *pci; |
| 536 | MACIOIDEState *macio_ide; |
| 537 | |
| 538 | if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { |
| 539 | pci = PCI_DEVICE(dev); |
| 540 | return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); |
| 541 | } |
| 542 | |
| 543 | if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { |
| 544 | macio_ide = MACIO_IDE(dev); |
| 545 | return g_strdup_printf("ata-3@%x", macio_ide->addr); |
| 546 | } |
| 547 | |
| 548 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { |
| 549 | return g_strdup("disk"); |
| 550 | } |
| 551 | |
| 552 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { |
| 553 | return g_strdup("cdrom"); |
| 554 | } |
| 555 | |
| 556 | if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { |
| 557 | return g_strdup("disk"); |
| 558 | } |
| 559 | |
| 560 | return NULL; |
| 561 | } |
| 562 | static int core99_kvm_type(MachineState *machine, const char *arg) |
| 563 | { |
| 564 | /* Always force PR KVM */ |
| 565 | return 2; |
| 566 | } |
| 567 | |
| 568 | static void core99_machine_class_init(ObjectClass *oc, const void *data) |
| 569 | { |
| 570 | MachineClass *mc = MACHINE_CLASS(oc); |
| 571 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
| 572 | |
| 573 | mc->desc = "Mac99 based PowerMac"; |
| 574 | mc->init = ppc_core99_init; |
| 575 | mc->block_default_type = IF_IDE; |
| 576 | /* SMP is not supported currently */ |
| 577 | mc->max_cpus = 1; |
| 578 | mc->default_boot_order = "cd"; |
| 579 | mc->default_display = "std"; |
| 580 | mc->default_nic = "sungem"; |
| 581 | mc->kvm_type = core99_kvm_type; |
| 582 | #ifdef TARGET_PPC64 |
| 583 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); |
| 584 | #else |
| 585 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); |
| 586 | #endif |
| 587 | mc->default_ram_id = "ppc_core99.ram"; |
| 588 | mc->ignore_boot_device_suffixes = true; |
| 589 | fwc->get_dev_path = core99_fw_dev_path; |
| 590 | } |
| 591 | |
| 592 | static char *core99_get_via_config(Object *obj, Error **errp) |
| 593 | { |
| 594 | Core99MachineState *cms = CORE99_MACHINE(obj); |
| 595 | |
| 596 | switch (cms->via_config) { |
| 597 | default: |
| 598 | case CORE99_VIA_CONFIG_CUDA: |
| 599 | return g_strdup("cuda"); |
| 600 | |
| 601 | case CORE99_VIA_CONFIG_PMU: |
| 602 | return g_strdup("pmu"); |
| 603 | |
| 604 | case CORE99_VIA_CONFIG_PMU_ADB: |
| 605 | return g_strdup("pmu-adb"); |
| 606 | } |
| 607 | } |
| 608 | |
| 609 | static void core99_set_via_config(Object *obj, const char *value, Error **errp) |
| 610 | { |
| 611 | Core99MachineState *cms = CORE99_MACHINE(obj); |
| 612 | |
| 613 | if (!strcmp(value, "cuda")) { |
| 614 | cms->via_config = CORE99_VIA_CONFIG_CUDA; |
| 615 | } else if (!strcmp(value, "pmu")) { |
| 616 | cms->via_config = CORE99_VIA_CONFIG_PMU; |
| 617 | } else if (!strcmp(value, "pmu-adb")) { |
| 618 | cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; |
| 619 | } else { |
| 620 | error_setg(errp, "Invalid via value"); |
| 621 | error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | static void core99_instance_init(Object *obj) |
| 626 | { |
| 627 | Core99MachineState *cms = CORE99_MACHINE(obj); |
| 628 | |
| 629 | /* Default via_config is CORE99_VIA_CONFIG_CUDA */ |
| 630 | cms->via_config = CORE99_VIA_CONFIG_CUDA; |
| 631 | object_property_add_str(obj, "via", core99_get_via_config, |
| 632 | core99_set_via_config); |
| 633 | object_property_set_description(obj, "via", |
| 634 | "Set VIA configuration. " |
| 635 | "Valid values are cuda, pmu and pmu-adb"); |
| 636 | } |
| 637 | |
| 638 | static const TypeInfo core99_machine_info = { |
| 639 | .name = MACHINE_TYPE_NAME("mac99"), |
| 640 | .parent = TYPE_MACHINE, |
| 641 | .class_init = core99_machine_class_init, |
| 642 | .instance_init = core99_instance_init, |
| 643 | .instance_size = sizeof(Core99MachineState), |
| 644 | .interfaces = (const InterfaceInfo[]) { |
| 645 | { TYPE_FW_PATH_PROVIDER }, |
| 646 | { } |
| 647 | }, |
| 648 | }; |
| 649 | |
| 650 | static void mac_machine_register_types(void) |
| 651 | { |
| 652 | type_register_static(&core99_machine_info); |
| 653 | } |
| 654 | |
| 655 | type_init(mac_machine_register_types) |