| 1 | |
| 2 | /* |
| 3 | * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator |
| 4 | * |
| 5 | * Copyright (c) 2004-2007 Fabrice Bellard |
| 6 | * Copyright (c) 2007 Jocelyn Mayer |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include "qemu/osdep.h" |
| 28 | #include "qemu/datadir.h" |
| 29 | #include "qemu/units.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "exec/target_page.h" |
| 32 | #include "hw/ppc/ppc.h" |
| 33 | #include "hw/core/qdev-properties.h" |
| 34 | #include "hw/core/boards.h" |
| 35 | #include "hw/input/adb.h" |
| 36 | #include "system/system.h" |
| 37 | #include "net/net.h" |
| 38 | #include "hw/isa/isa.h" |
| 39 | #include "hw/pci/pci.h" |
| 40 | #include "hw/pci/pci_host.h" |
| 41 | #include "hw/pci-host/grackle.h" |
| 42 | #include "hw/nvram/fw_cfg.h" |
| 43 | #include "hw/char/escc.h" |
| 44 | #include "hw/misc/macio/macio.h" |
| 45 | #include "hw/core/loader.h" |
| 46 | #include "hw/core/fw-path-provider.h" |
| 47 | #include "elf.h" |
| 48 | #include "qemu/error-report.h" |
| 49 | #include "system/kvm.h" |
| 50 | #include "system/reset.h" |
| 51 | #include "kvm_ppc.h" |
| 52 | |
| 53 | #define MAX_IDE_BUS 2 |
| 54 | #define CFG_ADDR 0xf0000510 |
| 55 | #define TBFREQ 16600000UL |
| 56 | #define CLOCKFREQ 266000000UL |
| 57 | #define BUSFREQ 66000000UL |
| 58 | |
| 59 | #define NDRV_VGA_FILENAME "qemu_vga.ndrv" |
| 60 | |
| 61 | #define PROM_FILENAME "openbios-ppc" |
| 62 | #define PROM_BASE 0xffc00000 |
| 63 | #define PROM_SIZE (4 * MiB) |
| 64 | |
| 65 | #define KERNEL_LOAD_ADDR 0x01000000 |
| 66 | #define KERNEL_GAP 0x00100000 |
| 67 | |
| 68 | #define GRACKLE_BASE 0xfec00000 |
| 69 | |
| 70 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 71 | Error **errp) |
| 72 | { |
| 73 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 74 | } |
| 75 | |
| 76 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
| 77 | { |
| 78 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
| 79 | } |
| 80 | |
| 81 | static void ppc_heathrow_reset(void *opaque) |
| 82 | { |
| 83 | PowerPCCPU *cpu = opaque; |
| 84 | |
| 85 | cpu_ppc_tb_reset(&cpu->env); |
| 86 | cpu_reset(CPU(cpu)); |
| 87 | } |
| 88 | |
| 89 | static void ppc_heathrow_init(MachineState *machine) |
| 90 | { |
| 91 | const char *bios_name = machine->firmware ?: PROM_FILENAME; |
| 92 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 93 | PowerPCCPU *cpu = NULL; |
| 94 | CPUPPCState *env = NULL; |
| 95 | char *filename; |
| 96 | int i, bios_size = -1; |
| 97 | MemoryRegion *bios = g_new(MemoryRegion, 1); |
| 98 | uint64_t bios_addr; |
| 99 | uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; |
| 100 | int32_t kernel_size = 0, initrd_size = 0; |
| 101 | PCIBus *pci_bus; |
| 102 | Object *macio; |
| 103 | MACIOIDEState *macio_ide; |
| 104 | SysBusDevice *s; |
| 105 | DeviceState *dev, *pic_dev, *grackle_dev; |
| 106 | BusState *adb_bus; |
| 107 | uint16_t ppc_boot_device; |
| 108 | DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 109 | void *fw_cfg; |
| 110 | uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; |
| 111 | |
| 112 | /* init CPUs */ |
| 113 | for (i = 0; i < machine->smp.cpus; i++) { |
| 114 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
| 115 | env = &cpu->env; |
| 116 | |
| 117 | /* Set time-base frequency to 16.6 Mhz */ |
| 118 | cpu_ppc_tb_init(env, TBFREQ); |
| 119 | qemu_register_reset(ppc_heathrow_reset, cpu); |
| 120 | } |
| 121 | |
| 122 | /* allocate RAM */ |
| 123 | if (machine->ram_size > 2047 * MiB) { |
| 124 | error_report("Too much memory for this machine: %" PRId64 " MB, " |
| 125 | "maximum 2047 MB", machine->ram_size / MiB); |
| 126 | exit(1); |
| 127 | } |
| 128 | |
| 129 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
| 130 | |
| 131 | /* allocate and load firmware ROM */ |
| 132 | memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, |
| 133 | &error_fatal); |
| 134 | memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); |
| 135 | |
| 136 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 137 | if (filename) { |
| 138 | /* Load OpenBIOS (ELF) */ |
| 139 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, |
| 140 | NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 141 | /* Unfortunately, load_elf sign-extends reading elf32 */ |
| 142 | bios_addr = (uint32_t)bios_addr; |
| 143 | |
| 144 | if (bios_size <= 0) { |
| 145 | /* or if could not load ELF try loading a binary ROM image */ |
| 146 | bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE, |
| 147 | &error_fatal); |
| 148 | bios_addr = PROM_BASE; |
| 149 | } |
| 150 | g_free(filename); |
| 151 | } |
| 152 | if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { |
| 153 | error_report("could not load PowerPC bios '%s'", bios_name); |
| 154 | exit(1); |
| 155 | } |
| 156 | |
| 157 | if (machine->kernel_filename) { |
| 158 | kernel_base = KERNEL_LOAD_ADDR; |
| 159 | kernel_size = load_elf(machine->kernel_filename, NULL, |
| 160 | translate_kernel_address, NULL, NULL, NULL, |
| 161 | NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 162 | if (kernel_size < 0) { |
| 163 | kernel_size = load_aout(machine->kernel_filename, kernel_base, |
| 164 | machine->ram_size - kernel_base, |
| 165 | true, TARGET_PAGE_SIZE); |
| 166 | } |
| 167 | if (kernel_size < 0) { |
| 168 | kernel_size = load_image_targphys(machine->kernel_filename, |
| 169 | kernel_base, |
| 170 | machine->ram_size - kernel_base, |
| 171 | &error_fatal); |
| 172 | } |
| 173 | /* load initrd */ |
| 174 | if (machine->initrd_filename) { |
| 175 | initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + |
| 176 | KERNEL_GAP); |
| 177 | initrd_size = load_image_targphys(machine->initrd_filename, |
| 178 | initrd_base, |
| 179 | machine->ram_size - initrd_base, |
| 180 | &error_fatal); |
| 181 | cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); |
| 182 | } else { |
| 183 | cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); |
| 184 | } |
| 185 | ppc_boot_device = 'm'; |
| 186 | } else { |
| 187 | ppc_boot_device = '\0'; |
| 188 | for (i = 0; machine->boot_config.order[i] != '\0'; i++) { |
| 189 | /* |
| 190 | * TOFIX: for now, the second IDE channel is not properly |
| 191 | * used by OHW. The Mac floppy disk are not emulated. |
| 192 | * For now, OHW cannot boot from the network. |
| 193 | */ |
| 194 | #if 0 |
| 195 | if (machine->boot_config.order[i] >= 'a' && |
| 196 | machine->boot_config.order[i] <= 'f') { |
| 197 | ppc_boot_device = machine->boot_config.order[i]; |
| 198 | break; |
| 199 | } |
| 200 | #else |
| 201 | if (machine->boot_config.order[i] >= 'c' && |
| 202 | machine->boot_config.order[i] <= 'd') { |
| 203 | ppc_boot_device = machine->boot_config.order[i]; |
| 204 | break; |
| 205 | } |
| 206 | #endif |
| 207 | } |
| 208 | if (ppc_boot_device == '\0') { |
| 209 | error_report("No valid boot device for G3 Beige machine"); |
| 210 | exit(1); |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | /* Grackle PCI host bridge */ |
| 215 | grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); |
| 216 | qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); |
| 217 | s = SYS_BUS_DEVICE(grackle_dev); |
| 218 | sysbus_realize_and_unref(s, &error_fatal); |
| 219 | |
| 220 | sysbus_mmio_map(s, 0, GRACKLE_BASE); |
| 221 | sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); |
| 222 | /* PCI hole */ |
| 223 | memory_region_add_subregion(get_system_memory(), 0x80000000ULL, |
| 224 | sysbus_mmio_get_region(s, 2)); |
| 225 | /* Register 2 MB of ISA IO space */ |
| 226 | memory_region_add_subregion(get_system_memory(), 0xfe000000, |
| 227 | sysbus_mmio_get_region(s, 3)); |
| 228 | |
| 229 | pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; |
| 230 | |
| 231 | /* MacIO */ |
| 232 | macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); |
| 233 | qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); |
| 234 | |
| 235 | dev = DEVICE(object_resolve_path_component(macio, "escc")); |
| 236 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); |
| 237 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
| 238 | |
| 239 | dinfo = drive_get(IF_MTD, 0, 0); |
| 240 | if (dinfo) { |
| 241 | dev = DEVICE(object_resolve_path_component(macio, "nvram")); |
| 242 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
| 243 | } |
| 244 | |
| 245 | pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); |
| 246 | |
| 247 | pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); |
| 248 | for (i = 0; i < 4; i++) { |
| 249 | qdev_connect_gpio_out(grackle_dev, i, |
| 250 | qdev_get_gpio_in(pic_dev, 0x15 + i)); |
| 251 | } |
| 252 | |
| 253 | /* Connect the heathrow PIC outputs to the 6xx bus */ |
| 254 | for (i = 0; i < machine->smp.cpus; i++) { |
| 255 | switch (PPC_INPUT(env)) { |
| 256 | case PPC_FLAGS_INPUT_6xx: |
| 257 | /* XXX: we register only 1 output pin for heathrow PIC */ |
| 258 | qdev_connect_gpio_out(pic_dev, 0, |
| 259 | qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); |
| 260 | break; |
| 261 | default: |
| 262 | error_report("Bus model not supported on OldWorld Mac machine"); |
| 263 | exit(1); |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | pci_vga_init(pci_bus); |
| 268 | |
| 269 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 270 | |
| 271 | /* MacIO IDE */ |
| 272 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
| 273 | macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); |
| 274 | macio_ide_init_drives(macio_ide, hd); |
| 275 | |
| 276 | macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); |
| 277 | macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); |
| 278 | |
| 279 | /* MacIO CUDA/ADB */ |
| 280 | dev = DEVICE(object_resolve_path_component(macio, "cuda")); |
| 281 | adb_bus = qdev_get_child_bus(dev, "adb.0"); |
| 282 | dev = qdev_new(TYPE_ADB_KEYBOARD); |
| 283 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); |
| 284 | dev = qdev_new(TYPE_ADB_MOUSE); |
| 285 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); |
| 286 | |
| 287 | if (machine_usb(machine)) { |
| 288 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
| 289 | } |
| 290 | |
| 291 | if (!graphic_width) { |
| 292 | graphic_width = 800; |
| 293 | } |
| 294 | if (!graphic_height) { |
| 295 | graphic_height = 600; |
| 296 | } |
| 297 | if (!graphic_depth) { |
| 298 | graphic_depth = 32; |
| 299 | } |
| 300 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { |
| 301 | graphic_depth = 15; |
| 302 | } |
| 303 | |
| 304 | /* No PCI init: the BIOS will do it */ |
| 305 | |
| 306 | dev = qdev_new(TYPE_FW_CFG_MEM); |
| 307 | fw_cfg = FW_CFG(dev); |
| 308 | qdev_prop_set_uint32(dev, "data_width", 1); |
| 309 | qdev_prop_set_bit(dev, "dma_enabled", false); |
| 310 | object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); |
| 311 | s = SYS_BUS_DEVICE(dev); |
| 312 | sysbus_realize_and_unref(s, &error_fatal); |
| 313 | sysbus_mmio_map(s, 0, CFG_ADDR); |
| 314 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); |
| 315 | |
| 316 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); |
| 317 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
| 318 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
| 319 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); |
| 320 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
| 321 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 322 | if (machine->kernel_cmdline) { |
| 323 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); |
| 324 | pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, |
| 325 | machine->kernel_cmdline); |
| 326 | } else { |
| 327 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); |
| 328 | } |
| 329 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); |
| 330 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 331 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); |
| 332 | |
| 333 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); |
| 334 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); |
| 335 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); |
| 336 | |
| 337 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); |
| 338 | if (kvm_enabled()) { |
| 339 | uint8_t *hypercall; |
| 340 | |
| 341 | hypercall = g_malloc(16); |
| 342 | kvmppc_get_hypercall(env, hypercall, 16); |
| 343 | fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); |
| 344 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); |
| 345 | } |
| 346 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); |
| 347 | /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ |
| 348 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); |
| 349 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); |
| 350 | |
| 351 | /* MacOS NDRV VGA driver */ |
| 352 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); |
| 353 | if (filename) { |
| 354 | gchar *ndrv_file; |
| 355 | gsize ndrv_size; |
| 356 | |
| 357 | if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { |
| 358 | fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); |
| 359 | } |
| 360 | g_free(filename); |
| 361 | } |
| 362 | |
| 363 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * Implementation of an interface to adjust firmware path |
| 368 | * for the bootindex property handling. |
| 369 | */ |
| 370 | static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, |
| 371 | DeviceState *dev) |
| 372 | { |
| 373 | PCIDevice *pci; |
| 374 | MACIOIDEState *macio_ide; |
| 375 | |
| 376 | if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { |
| 377 | pci = PCI_DEVICE(dev); |
| 378 | return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); |
| 379 | } |
| 380 | |
| 381 | if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { |
| 382 | macio_ide = MACIO_IDE(dev); |
| 383 | return g_strdup_printf("ata-3@%x", macio_ide->addr); |
| 384 | } |
| 385 | |
| 386 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { |
| 387 | return g_strdup("disk"); |
| 388 | } |
| 389 | |
| 390 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { |
| 391 | return g_strdup("cdrom"); |
| 392 | } |
| 393 | |
| 394 | if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { |
| 395 | return g_strdup("disk"); |
| 396 | } |
| 397 | |
| 398 | return NULL; |
| 399 | } |
| 400 | |
| 401 | static int heathrow_kvm_type(MachineState *machine, const char *arg) |
| 402 | { |
| 403 | /* Always force PR KVM */ |
| 404 | return 2; |
| 405 | } |
| 406 | |
| 407 | static void heathrow_class_init(ObjectClass *oc, const void *data) |
| 408 | { |
| 409 | MachineClass *mc = MACHINE_CLASS(oc); |
| 410 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
| 411 | |
| 412 | mc->desc = "Heathrow based PowerMac"; |
| 413 | mc->init = ppc_heathrow_init; |
| 414 | mc->block_default_type = IF_IDE; |
| 415 | /* SMP is not supported currently */ |
| 416 | mc->max_cpus = 1; |
| 417 | #ifndef TARGET_PPC64 |
| 418 | mc->is_default = true; |
| 419 | #endif |
| 420 | /* TOFIX "cad" when Mac floppy is implemented */ |
| 421 | mc->default_boot_order = "cd"; |
| 422 | mc->kvm_type = heathrow_kvm_type; |
| 423 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); |
| 424 | mc->default_display = "std"; |
| 425 | mc->default_nic = "ne2k_pci"; |
| 426 | mc->ignore_boot_device_suffixes = true; |
| 427 | mc->default_ram_id = "ppc_heathrow.ram"; |
| 428 | fwc->get_dev_path = heathrow_fw_dev_path; |
| 429 | } |
| 430 | |
| 431 | static const TypeInfo ppc_heathrow_machine_info = { |
| 432 | .name = MACHINE_TYPE_NAME("g3beige"), |
| 433 | .parent = TYPE_MACHINE, |
| 434 | .class_init = heathrow_class_init, |
| 435 | .interfaces = (const InterfaceInfo[]) { |
| 436 | { TYPE_FW_PATH_PROVIDER }, |
| 437 | { } |
| 438 | }, |
| 439 | }; |
| 440 | |
| 441 | static void ppc_heathrow_register_types(void) |
| 442 | { |
| 443 | type_register_static(&ppc_heathrow_machine_info); |
| 444 | } |
| 445 | |
| 446 | type_init(ppc_heathrow_register_types); |