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1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos I/II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qapi/error.h"
13 #include "hw/ppc/ppc.h"
14 #include "hw/core/sysbus.h"
15 #include "hw/pci/pci_host.h"
16 #include "hw/core/irq.h"
17 #include "hw/core/or-irq.h"
18 #include "hw/pci-host/articia.h"
19 #include "hw/pci-host/mv64361.h"
20 #include "hw/isa/vt82c686.h"
21 #include "hw/ide/pci.h"
22 #include "hw/i2c/smbus_eeprom.h"
23 #include "hw/core/qdev-properties.h"
24 #include "system/physmem.h"
25 #include "system/reset.h"
26 #include "system/runstate.h"
27 #include "system/qtest.h"
28 #include "hw/core/boards.h"
29 #include "hw/core/loader.h"
30 #include "hw/core/fw-path-provider.h"
31 #include "elf.h"
32 #include "qemu/log.h"
33 #include "qemu/error-report.h"
34 #include "system/kvm.h"
35 #include "kvm_ppc.h"
36 #include "system/address-spaces.h"
37 #include "qom/qom-qobject.h"
38 #include "qobject/qdict.h"
39 #include "trace.h"
40 #include "qemu/datadir.h"
41 #include "system/device_tree.h"
42 #include "hw/ppc/vof.h"
43 #include "exec/cpu-common.h"
44
45 #include <libfdt.h>
46
47 #define PROM_FILENAME "vof.bin"
48 #define PROM_ADDR 0xfff00000
49 #define PROM_SIZE 0x80000
50
51 #define INITRD_MIN_ADDR 0x600000
52
53 #define KVMPPC_HCALL_BASE 0xf000
54 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
55 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
56
57 #define H_SUCCESS 0
58 #define H_PRIVILEGE -3 /* Caller not privileged */
59 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
60
61 typedef enum {
62 PEGASOS1 = 1,
63 PEGASOS2 = 2,
64 } PegasosMachineType;
65
66 #define TYPE_PEGASOS_MACHINE MACHINE_TYPE_NAME("pegasos")
67 OBJECT_DECLARE_SIMPLE_TYPE(PegasosMachineState, PEGASOS_MACHINE)
68
69 struct PegasosMachineState {
70 MachineState parent_obj;
71
72 PegasosMachineType type;
73 PowerPCCPU *cpu;
74 DeviceState *nb; /* north bridge */
75 DeviceState *sb; /* south bridge */
76 int bus_freq_hz;
77 IRQState pci_irqs[PCI_NUM_PINS];
78 OrIRQState orirq[PCI_NUM_PINS];
79 qemu_irq mv_pirq[PCI_NUM_PINS];
80 qemu_irq via_pirq[PCI_NUM_PINS];
81 Vof *vof;
82 uint64_t kernel_addr;
83 uint64_t kernel_entry;
84 uint64_t kernel_size;
85 uint64_t initrd_addr;
86 uint64_t initrd_size;
87 };
88
89 static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size);
90 static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size);
91
92 static void pegasos_cpu_reset(void *opaque)
93 {
94 PowerPCCPU *cpu = opaque;
95 PegasosMachineState *pm = PEGASOS_MACHINE(current_machine);
96
97 cpu_reset(CPU(cpu));
98 cpu->env.spr[SPR_HID1] = 7ULL << 28;
99 if (pm->vof) {
100 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
101 cpu->env.nip = 0x100;
102 } else if (pm->type == PEGASOS1) {
103 cpu->env.nip = 0xfffc0100;
104 }
105 cpu_ppc_tb_reset(&cpu->env);
106 }
107
108 static void pegasos2_pci_irq(void *opaque, int n, int level)
109 {
110 PegasosMachineState *pm = opaque;
111
112 /* PCI interrupt lines are connected to both MV64361 and VT8231 */
113 qemu_set_irq(pm->mv_pirq[n], level);
114 qemu_set_irq(pm->via_pirq[n], level);
115 }
116
117 /* Set up PCI interrupt routing: lines from pci.0 and pci.1 are ORed */
118 static void pegasos2_setup_pci_irq(PegasosMachineState *pm)
119 {
120 for (int h = 0; h < 2; h++) {
121 DeviceState *pd;
122 g_autofree const char *pn = g_strdup_printf("pcihost%d", h);
123
124 pd = DEVICE(object_resolve_path_component(OBJECT(pm->nb), pn));
125 assert(pd);
126 for (int i = 0; i < PCI_NUM_PINS; i++) {
127 OrIRQState *ori = &pm->orirq[i];
128
129 if (h == 0) {
130 g_autofree const char *n = g_strdup_printf("pci-orirq[%d]", i);
131
132 object_initialize_child_with_props(OBJECT(pm), n,
133 ori, sizeof(*ori),
134 TYPE_OR_IRQ, &error_fatal,
135 "num-lines", "2", NULL);
136 qdev_realize(DEVICE(ori), NULL, &error_fatal);
137 qemu_init_irq(&pm->pci_irqs[i], pegasos2_pci_irq, pm, i);
138 qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]);
139 pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->nb, "gpp", 12 + i);
140 pm->via_pirq[i] = qdev_get_gpio_in_named(pm->sb, "pirq", i);
141 }
142 qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h));
143 }
144 }
145 qdev_connect_gpio_out_named(pm->sb, "intr", 0,
146 qdev_get_gpio_in_named(pm->nb, "gpp", 31));
147 }
148
149 static void pegasos_init(MachineState *machine)
150 {
151 PegasosMachineState *pm = PEGASOS_MACHINE(machine);
152 CPUPPCState *env;
153 MemoryRegion *rom = g_new(MemoryRegion, 1);
154 PCIBus *pci_bus = NULL;
155 Object *via;
156 PCIDevice *dev;
157 I2CBus *i2c_bus;
158 const char *fwname = machine->firmware ?: PROM_FILENAME;
159 char *filename;
160 hwaddr prom_addr;
161 ssize_t sz;
162 int devfn;
163 uint8_t *spd_data;
164
165 /* init CPU */
166 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
167 env = &pm->cpu->env;
168 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
169 error_report("Incompatible CPU, only 6xx bus supported");
170 exit(1);
171 }
172
173 /* Set time-base frequency */
174 cpu_ppc_tb_init(env, pm->bus_freq_hz / 4);
175 qemu_register_reset(pegasos_cpu_reset, pm->cpu);
176
177 /* RAM */
178 if (machine->ram_size > 2 * GiB) {
179 error_report("RAM size more than 2 GiB is not supported");
180 exit(1);
181 }
182 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
183
184 /* allocate and load firmware */
185 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
186 if (!filename) {
187 error_report("Could not find firmware '%s'", fwname);
188 exit(1);
189 }
190 if (!machine->firmware && !pm->vof) {
191 pm->vof = g_malloc0(sizeof(*pm->vof));
192 }
193 prom_addr = PROM_ADDR;
194 if (pm->type == PEGASOS1) {
195 prom_addr += PROM_SIZE;
196 }
197 memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal);
198 memory_region_add_subregion(get_system_memory(), prom_addr, rom);
199 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
200 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
201 if (sz <= 0) {
202 sz = load_image_targphys(filename, pm->vof ? 0 : prom_addr, PROM_SIZE,
203 &error_fatal);
204 }
205 if (sz <= 0 || sz > PROM_SIZE) {
206 error_report("Could not load firmware '%s'", filename);
207 exit(1);
208 }
209 g_free(filename);
210 if (pm->vof) {
211 pm->vof->fw_size = sz;
212 }
213
214 /* north bridge */
215 switch (pm->type) {
216 case PEGASOS1:
217 {
218 MemoryRegion *pci_mem, *mr;
219
220 /* Articia S */
221 pm->nb = DEVICE(sysbus_create_simple(TYPE_ARTICIA, 0xfe000000, NULL));
222 pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 1);
223 mr = g_new(MemoryRegion, 1);
224 memory_region_init_alias(mr, OBJECT(pm->nb), "pci-mem-low", pci_mem,
225 0, 0x1000000);
226 memory_region_add_subregion(get_system_memory(), 0xfd000000, mr);
227 mr = g_new(MemoryRegion, 1);
228 memory_region_init_alias(mr, OBJECT(pm->nb), "pci-mem-high", pci_mem,
229 0x80000000, 0x7d000000);
230 memory_region_add_subregion(get_system_memory(), 0x80000000, mr);
231 pci_bus = PCI_BUS(qdev_get_child_bus(pm->nb, "pci.0"));
232 break;
233 }
234 case PEGASOS2:
235 /* Marvell Discovery II system controller */
236 pm->nb = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
237 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
238 pci_bus = mv64361_get_pci_bus(pm->nb, 1);
239 break;
240 }
241
242 /* VIA VT8231 South Bridge (multifunction PCI device) */
243 devfn = PCI_DEVFN(pm->type == PEGASOS1 ? 7 : 12, 0);
244 pm->sb = DEVICE(pci_new_multifunction(devfn, TYPE_VT8231_ISA));
245 via = OBJECT(pm->sb);
246
247 /* Set properties on individual devices before realizing the south bridge */
248 if (machine->audiodev) {
249 dev = PCI_DEVICE(object_resolve_path_component(via, "ac97"));
250 qdev_prop_set_string(DEVICE(dev), "audiodev", machine->audiodev);
251 }
252
253 pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_abort);
254 object_property_add_alias(OBJECT(machine), "rtc-time",
255 object_resolve_path_component(via, "rtc"),
256 "date");
257
258 dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
259 pci_ide_create_devs(dev);
260
261 dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
262 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
263 spd_data = spd_data_generate(DDR, machine->ram_size);
264 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
265
266 /* other PC hardware */
267 pci_vga_init(pci_bus);
268
269 /* pci interrupt routing */
270 switch (pm->type) {
271 case PEGASOS1:
272 qdev_connect_gpio_out_named(pm->sb, "intr", 0,
273 qdev_get_gpio_in(DEVICE(pm->cpu),
274 PPC6xx_INPUT_INT));
275 for (int i = 0; i < PCI_NUM_PINS; i++) {
276 qdev_connect_gpio_out(pm->nb, i,
277 qdev_get_gpio_in_named(pm->sb, "pirq", i));
278 }
279 break;
280 case PEGASOS2:
281 pegasos2_setup_pci_irq(pm);
282 break;
283 }
284
285 if (machine->kernel_filename) {
286 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
287 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL,
288 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
289 if (sz <= 0) {
290 error_report("Could not load kernel '%s'",
291 machine->kernel_filename);
292 exit(1);
293 }
294 pm->kernel_size = sz;
295 if (!pm->vof) {
296 warn_report("Option -kernel may be ineffective with -bios.");
297 }
298 } else if (pm->vof && !qtest_enabled()) {
299 warn_report("Using Virtual OpenFirmware but no -kernel option.");
300 }
301
302 if (machine->initrd_filename) {
303 pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB;
304 pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4);
305 pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR);
306 sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr,
307 machine->ram_size - pm->initrd_addr, &error_fatal);
308 pm->initrd_size = sz;
309 }
310
311 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
312 warn_report("Option -append may be ineffective with -bios.");
313 }
314 }
315
316 static void pegasos_superio_write(uint8_t addr, uint8_t val)
317 {
318 physical_memory_write(0xfe0003f0, &addr, 1);
319 physical_memory_write(0xfe0003f1, &val, 1);
320 }
321
322 static void pegasos1_pci_config_write(PegasosMachineState *pm, int bus,
323 uint32_t addr, uint32_t len, uint32_t val)
324 {
325 addr |= BIT(31);
326 physical_memory_write(0xfec00cf8, &addr, 4);
327 physical_memory_write(0xfee00cfc, &val, len);
328 }
329
330 static void pegasos1_chipset_reset(PegasosMachineState *pm)
331 {
332 uint8_t elcr = 0x2e;
333 physical_memory_write(0xfe0004d1, &elcr, sizeof(elcr));
334
335 pegasos1_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
336 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
337
338 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
339 PCI_INTERRUPT_LINE, 2, 0x9);
340 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
341 0x50, 1, 0x6);
342 pegasos_superio_write(0xf4, 0xbe);
343 pegasos_superio_write(0xf6, 0xef);
344 pegasos_superio_write(0xf7, 0xfc);
345 pegasos_superio_write(0xf2, 0x14);
346 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
347 0x51, 1, 0x3d);
348 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
349 0x55, 1, 0x90);
350 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
351 0x56, 1, 0x99);
352 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
353 0x57, 1, 0x90);
354
355 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
356 PCI_INTERRUPT_LINE, 2, 0x10e);
357 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
358 PCI_CLASS_PROG, 1, 0xf);
359 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
360 0x40, 1, 0xb);
361 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
362 0x50, 4, 0x17171717);
363 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
364 PCI_COMMAND, 2, 0x87);
365
366 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
367 PCI_INTERRUPT_LINE, 2, 0x409);
368 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
369 PCI_COMMAND, 2, 0x7);
370
371 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
372 PCI_INTERRUPT_LINE, 2, 0x409);
373 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
374 PCI_COMMAND, 2, 0x7);
375
376 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
377 PCI_INTERRUPT_LINE, 2, 0x9);
378 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
379 0x48, 4, 0x2001);
380 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
381 0x41, 1, 0);
382 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
383 0x90, 4, 0x1000);
384
385 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 5) << 8) |
386 PCI_INTERRUPT_LINE, 2, 0x309);
387
388 pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 6) << 8) |
389 PCI_INTERRUPT_LINE, 2, 0x309);
390 }
391
392 static uint32_t pegasos2_mv_reg_read(PegasosMachineState *pm,
393 uint32_t addr, uint32_t len)
394 {
395 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 0);
396 uint64_t val = 0xffffffffULL;
397 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
398 MEMTXATTRS_UNSPECIFIED);
399 return val;
400 }
401
402 static void pegasos2_mv_reg_write(PegasosMachineState *pm, uint32_t addr,
403 uint32_t len, uint32_t val)
404 {
405 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 0);
406 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
407 MEMTXATTRS_UNSPECIFIED);
408 }
409
410 #define PCI0_CFG_ADDR 0xcf8
411 #define PCI1_CFG_ADDR 0xc78
412
413 static uint32_t pegasos2_pci_config_read(PegasosMachineState *pm, int bus,
414 uint32_t addr, uint32_t len)
415 {
416 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
417 uint64_t val = 0xffffffffULL;
418
419 if (len <= 4) {
420 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
421 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
422 }
423 return val;
424 }
425
426 static void pegasos2_pci_config_write(PegasosMachineState *pm, int bus,
427 uint32_t addr, uint32_t len, uint32_t val)
428 {
429 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
430
431 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
432 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
433 }
434
435 static void pegasos2_chipset_reset(PegasosMachineState *pm)
436 {
437 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
438 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
439 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
440 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
441 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
442 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
443 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
444 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
445 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
446
447 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
448 PCI_INTERRUPT_LINE, 2, 0x9);
449 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
450 0x50, 1, 0x6);
451 pegasos_superio_write(0xf4, 0xbe);
452 pegasos_superio_write(0xf6, 0xef);
453 pegasos_superio_write(0xf7, 0xfc);
454 pegasos_superio_write(0xf2, 0x14);
455 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
456 0x50, 1, 0x2);
457 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
458 0x55, 1, 0x90);
459 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
460 0x56, 1, 0x99);
461 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
462 0x57, 1, 0x90);
463
464 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
465 PCI_INTERRUPT_LINE, 2, 0x109);
466 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
467 PCI_CLASS_PROG, 1, 0xf);
468 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
469 0x40, 1, 0xb);
470 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
471 0x50, 4, 0x17171717);
472 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
473 PCI_COMMAND, 2, 0x87);
474
475 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
476 PCI_INTERRUPT_LINE, 2, 0x409);
477 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
478 PCI_COMMAND, 2, 0x7);
479
480 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
481 PCI_INTERRUPT_LINE, 2, 0x409);
482 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
483 PCI_COMMAND, 2, 0x7);
484
485 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
486 PCI_INTERRUPT_LINE, 2, 0x9);
487 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
488 0x48, 4, 0xf00);
489 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
490 0x40, 4, 0x558020);
491 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
492 0x90, 4, 0xd00);
493
494 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
495 PCI_INTERRUPT_LINE, 2, 0x309);
496
497 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
498 PCI_INTERRUPT_LINE, 2, 0x309);
499 }
500
501 static void pegasos_machine_reset(MachineState *machine, ResetType type)
502 {
503 PegasosMachineState *pm = PEGASOS_MACHINE(machine);
504 void *fdt = NULL;
505 uint32_t c[2];
506 uint64_t d[2];
507 int sz;
508
509 qemu_devices_reset(type);
510 if (!pm->vof) {
511 return; /* Firmware should set up machine so nothing to do */
512 }
513
514 /* Otherwise, set up devices that board firmware would normally do */
515 switch (pm->type) {
516 case PEGASOS1:
517 pegasos1_chipset_reset(pm);
518 fdt = pegasos1_build_fdt(pm, &sz);
519 break;
520 case PEGASOS2:
521 pegasos2_chipset_reset(pm);
522 fdt = pegasos2_build_fdt(pm, &sz);
523 break;
524 }
525 if (!fdt) {
526 exit(1);
527 }
528
529 /* Device tree and VOF set up */
530 vof_init(pm->vof, machine->ram_size, &error_fatal);
531 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
532 error_report("Memory allocation for stack failed");
533 exit(1);
534 }
535 if (pm->kernel_size &&
536 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
537 error_report("Memory for kernel is in use");
538 exit(1);
539 }
540 if (pm->initrd_size &&
541 vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) {
542 error_report("Memory for initrd is in use");
543 exit(1);
544 }
545
546 /* Set memory size */
547 c[0] = 0;
548 c[1] = cpu_to_be32(machine->ram_size);
549 qemu_fdt_setprop(fdt, "/memory@0", "reg", c, sizeof(c));
550
551 /* Boot parameters */
552 if (pm->initrd_addr && pm->initrd_size) {
553 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
554 pm->initrd_addr + pm->initrd_size);
555 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
556 pm->initrd_addr);
557 }
558 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
559 machine->kernel_cmdline ?: "");
560 /* FIXME: VOF assumes entry is same as load address */
561 d[0] = cpu_to_be64(pm->kernel_entry);
562 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
563 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
564
565 vof_build_dt(fdt, pm->vof);
566 vof_client_open_store(fdt, pm->vof, "/chosen", "stdin", "/failsafe");
567 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
568
569 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
570 g_free(machine->fdt);
571 machine->fdt = fdt;
572
573 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
574 pm->cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(pm->cpu->vhyp);
575 }
576
577 enum pegasos2_rtas_tokens {
578 RTAS_RESTART_RTAS = 0,
579 RTAS_NVRAM_FETCH = 1,
580 RTAS_NVRAM_STORE = 2,
581 RTAS_GET_TIME_OF_DAY = 3,
582 RTAS_SET_TIME_OF_DAY = 4,
583 RTAS_EVENT_SCAN = 6,
584 RTAS_CHECK_EXCEPTION = 7,
585 RTAS_READ_PCI_CONFIG = 8,
586 RTAS_WRITE_PCI_CONFIG = 9,
587 RTAS_DISPLAY_CHARACTER = 10,
588 RTAS_SET_INDICATOR = 11,
589 RTAS_POWER_OFF = 17,
590 RTAS_SUSPEND = 18,
591 RTAS_HIBERNATE = 19,
592 RTAS_SYSTEM_REBOOT = 20,
593 };
594
595 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
596 target_ulong args_real)
597 {
598 AddressSpace *as = CPU(cpu)->as;
599 uint32_t token = ldl_be_phys(as, args_real);
600 uint32_t nargs = ldl_be_phys(as, args_real + 4);
601 uint32_t nrets = ldl_be_phys(as, args_real + 8);
602 uint32_t args = args_real + 12;
603 uint32_t rets = args_real + 12 + nargs * 4;
604
605 if (nrets < 1) {
606 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
607 return H_PARAMETER;
608 }
609 switch (token) {
610 case RTAS_GET_TIME_OF_DAY:
611 {
612 QObject *qo = object_property_get_qobject(qdev_get_machine(),
613 "rtc-time", &error_fatal);
614 QDict *qd = qobject_to(QDict, qo);
615
616 if (nargs != 0 || nrets != 8 || !qd) {
617 stl_be_phys(as, rets, -1);
618 qobject_unref(qo);
619 return H_PARAMETER;
620 }
621
622 stl_be_phys(as, rets, 0);
623 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
624 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
625 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
626 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
627 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
628 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
629 stl_be_phys(as, rets + 28, 0);
630 qobject_unref(qo);
631 return H_SUCCESS;
632 }
633 case RTAS_READ_PCI_CONFIG:
634 {
635 uint32_t addr, len, val;
636
637 if (nargs != 2 || nrets != 2) {
638 stl_be_phys(as, rets, -1);
639 return H_PARAMETER;
640 }
641 addr = ldl_be_phys(as, args);
642 len = ldl_be_phys(as, args + 4);
643 val = pegasos2_pci_config_read(pm, !(addr >> 24),
644 addr & 0x0fffffff, len);
645 stl_be_phys(as, rets, 0);
646 stl_be_phys(as, rets + 4, val);
647 return H_SUCCESS;
648 }
649 case RTAS_WRITE_PCI_CONFIG:
650 {
651 uint32_t addr, len, val;
652
653 if (nargs != 3 || nrets != 1) {
654 stl_be_phys(as, rets, -1);
655 return H_PARAMETER;
656 }
657 addr = ldl_be_phys(as, args);
658 len = ldl_be_phys(as, args + 4);
659 val = ldl_be_phys(as, args + 8);
660 pegasos2_pci_config_write(pm, !(addr >> 24),
661 addr & 0x0fffffff, len, val);
662 stl_be_phys(as, rets, 0);
663 return H_SUCCESS;
664 }
665 case RTAS_DISPLAY_CHARACTER:
666 if (nargs != 1 || nrets != 1) {
667 stl_be_phys(as, rets, -1);
668 return H_PARAMETER;
669 }
670 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
671 stl_be_phys(as, rets, 0);
672 return H_SUCCESS;
673 case RTAS_POWER_OFF:
674 {
675 if (nargs != 2 || nrets != 1) {
676 stl_be_phys(as, rets, -1);
677 return H_PARAMETER;
678 }
679 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
680 stl_be_phys(as, rets, 0);
681 return H_SUCCESS;
682 }
683 default:
684 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
685 token, nargs, nrets);
686 stl_be_phys(as, rets, 0);
687 return H_SUCCESS;
688 }
689 }
690
691 static bool pegasos_cpu_in_nested(PowerPCCPU *cpu)
692 {
693 return false;
694 }
695
696 static void pegasos_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
697 {
698 PegasosMachineState *pm = PEGASOS_MACHINE(vhyp);
699 CPUPPCState *env = &cpu->env;
700
701 /* The TCG path should also be holding the BQL at this point */
702 g_assert(bql_locked());
703
704 if (FIELD_EX64(env->msr, MSR, PR)) {
705 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
706 env->gpr[3] = H_PRIVILEGE;
707 } else if (env->gpr[3] == KVMPPC_H_RTAS && pm->type == PEGASOS2) {
708 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
709 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
710 int ret = vof_client_call(MACHINE(pm), pm->vof, MACHINE(pm)->fdt,
711 env->gpr[4]);
712 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
713 } else {
714 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
715 "\n", env->gpr[3]);
716 env->gpr[3] = -1;
717 }
718 }
719
720 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
721 {
722 }
723
724 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
725 {
726 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
727 }
728
729 static bool pegasos_setprop(MachineState *ms, const char *path,
730 const char *propname, void *val, int vallen)
731 {
732 return true;
733 }
734
735 static void pegasos_machine_init(MachineClass *mc)
736 {
737 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(mc);
738 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(mc);
739
740 mc->init = pegasos_init;
741 mc->reset = pegasos_machine_reset;
742 mc->block_default_type = IF_IDE;
743 mc->default_boot_order = "cd";
744 mc->default_display = "std";
745 mc->default_ram_id = "ram";
746 mc->default_ram_size = 512 * MiB;
747 machine_add_audiodev_property(mc);
748
749 vhc->cpu_in_nested = pegasos_cpu_in_nested;
750 vhc->hypercall = pegasos_hypercall;
751 vhc->cpu_exec_enter = vhyp_nop;
752 vhc->cpu_exec_exit = vhyp_nop;
753 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
754
755 vmc->setprop = pegasos_setprop;
756 }
757
758 static void pegasos1_init(Object *obj)
759 {
760 PegasosMachineState *pm = PEGASOS_MACHINE(obj);
761
762 pm->type = PEGASOS1;
763 pm->bus_freq_hz = 33000000;
764 }
765
766 static void pegasos1_machine_class_init(ObjectClass *oc, const void *data)
767 {
768 MachineClass *mc = MACHINE_CLASS(oc);
769
770 mc->desc = "Genesi/bPlan Pegasos I";
771 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750cxe_v3.1b");
772 }
773
774 static void pegasos2_init(Object *obj)
775 {
776 PegasosMachineState *pm = PEGASOS_MACHINE(obj);
777
778 pm->type = PEGASOS2;
779 pm->bus_freq_hz = 133333333;
780 }
781
782 static void pegasos2_machine_class_init(ObjectClass *oc, const void *data)
783 {
784 MachineClass *mc = MACHINE_CLASS(oc);
785
786 mc->desc = "Genesi/bPlan Pegasos II";
787 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
788 }
789
790 DEFINE_MACHINE_EXTENDED("pegasos", MACHINE, PegasosMachineState,
791 pegasos_machine_init, true, (const InterfaceInfo[]) {
792 { TYPE_PPC_VIRTUAL_HYPERVISOR },
793 { TYPE_VOF_MACHINE_IF }, { } })
794
795 static const TypeInfo pegasos_machine_types[] = {
796 {
797 .name = MACHINE_TYPE_NAME("pegasos1"),
798 .parent = TYPE_PEGASOS_MACHINE,
799 .class_init = pegasos1_machine_class_init,
800 .instance_init = pegasos1_init,
801 },
802 {
803 .name = MACHINE_TYPE_NAME("pegasos2"),
804 .parent = TYPE_PEGASOS_MACHINE,
805 .class_init = pegasos2_machine_class_init,
806 .instance_init = pegasos2_init,
807 },
808 };
809
810 DEFINE_TYPES(pegasos_machine_types)
811
812 /* FDT creation for passing to firmware */
813
814 typedef struct {
815 void *fdt;
816 const char *path;
817 } FDTInfo;
818
819 /* We do everything in reverse order so it comes out right in the tree */
820
821 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
822 {
823 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
824 }
825
826 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
827 {
828 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
829 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
830 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
831 }
832
833 static struct {
834 const char *id;
835 const char *name;
836 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
837 } device_map[] = {
838 { "pci10cc,660", "host", NULL },
839 { "pci10cc,661", "host", NULL },
840 { "pci11ab,6460", "host", NULL },
841 { "pci1106,571", "ide", dt_ide },
842 { "pci1106,3044", "firewire", NULL },
843 { "pci1106,3038", "usb", dt_usb },
844 { "pci1106,8235", "other", NULL },
845 { "pci1106,3058", "sound", NULL },
846 { NULL, NULL }
847 };
848
849 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
850 {
851 FDTInfo *fi = opaque;
852 GString *node;
853 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
854 int i, j;
855 const char *name = NULL;
856 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
857 pci_get_word(&d->config[PCI_VENDOR_ID]),
858 pci_get_word(&d->config[PCI_DEVICE_ID]));
859
860 if (!strcmp(pn, "pci1106,8231")) {
861 return; /* ISA bridge and devices are included in dtb */
862 }
863 if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) ==
864 PCI_CLASS_NETWORK_ETHERNET) {
865 name = "ethernet";
866 } else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 ==
867 PCI_BASE_CLASS_DISPLAY) {
868 name = "display";
869 }
870 for (i = 0; device_map[i].id; i++) {
871 if (!strcmp(pn, device_map[i].id)) {
872 name = device_map[i].name;
873 break;
874 }
875 }
876 node = g_string_new(NULL);
877 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
878 PCI_SLOT(d->devfn));
879 if (PCI_FUNC(d->devfn)) {
880 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
881 }
882
883 qemu_fdt_add_subnode(fi->fdt, node->str);
884 if (device_map[i].dtf) {
885 FDTInfo cfi = { fi->fdt, node->str };
886 device_map[i].dtf(bus, d, &cfi);
887 }
888 cells[0] = cpu_to_be32(d->devfn << 8);
889 cells[1] = 0;
890 cells[2] = 0;
891 cells[3] = 0;
892 cells[4] = 0;
893 j = 5;
894 for (i = 0; i < PCI_NUM_REGIONS; i++) {
895 if (!d->io_regions[i].size) {
896 continue;
897 }
898 cells[j] = PCI_BASE_ADDRESS_0 + i * 4;
899 if (cells[j] == 0x28) {
900 cells[j] = 0x30;
901 }
902 cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]);
903 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
904 cells[j] |= cpu_to_be32(1 << 24);
905 } else {
906 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
907 cells[j] |= cpu_to_be32(3 << 24);
908 } else {
909 cells[j] |= cpu_to_be32(2 << 24);
910 }
911 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
912 cells[j] |= cpu_to_be32(4 << 28);
913 }
914 }
915 cells[j + 1] = 0;
916 cells[j + 2] = 0;
917 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
918 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
919 j += 5;
920 }
921 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
922 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
923 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
924 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
925 }
926 /* Pegasos firmware has subsystem-id and subsystem-vendor-id swapped */
927 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
928 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
929 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
930 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
931 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
932 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
933 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
934 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
935 pci_get_word(&d->config[PCI_DEVICE_ID]));
936 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
937 pci_get_word(&d->config[PCI_VENDOR_ID]));
938
939 g_string_free(node, TRUE);
940 }
941
942 static void add_cpu_info(void *fdt, PowerPCCPU *cpu, int bus_freq)
943 {
944 uint32_t cells[2];
945
946 /* FIXME Get CPU name from CPU object */
947 const char *cp = "/cpus/PowerPC,G4";
948 qemu_fdt_add_subnode(fdt, cp);
949 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
950 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
951 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
952 cpu->env.dcache_line_size);
953 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
954 cpu->env.dcache_line_size);
955 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
956 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
957 cpu->env.icache_line_size);
958 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
959 cpu->env.icache_line_size);
960 if (ppc_is_split_tlb(cpu)) {
961 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
962 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
963 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
964 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
965 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
966 }
967 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
968 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
969 qemu_fdt_setprop_string(fdt, cp, "state", "running");
970 if (cpu->env.insns_flags & PPC_ALTIVEC) {
971 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
972 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
973 }
974 /*
975 * FIXME What flags do data-streams, external-control and
976 * performance-monitor depend on?
977 */
978 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
979 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
980 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
981 }
982 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
983 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
984 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
985 }
986 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
987 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
988 cpu->env.tb_env->tb_freq);
989 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", bus_freq);
990 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", bus_freq * 7.5);
991 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
992 cells[0] = 0;
993 cells[1] = 0;
994 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
995 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
996 }
997
998 static void *load_dtb(const char *filename, int *fdt_size)
999 {
1000 void *fdt;
1001 g_autofree char *name = qemu_find_file(QEMU_FILE_TYPE_DTB, filename);
1002
1003 if (!name) {
1004 error_report("Could not find dtb file '%s'", filename);
1005 return NULL;
1006 }
1007 fdt = load_device_tree(name, fdt_size);
1008 if (!fdt) {
1009 error_report("Could not load dtb file '%s'", name);
1010 }
1011 return fdt;
1012 }
1013
1014 static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size)
1015 {
1016 FDTInfo fi;
1017 PCIBus *pci_bus;
1018 void *fdt = load_dtb("pegasos1.dtb", fdt_size);
1019
1020 if (!fdt) {
1021 return NULL;
1022 }
1023 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos");
1024
1025 add_cpu_info(fdt, pm->cpu, pm->bus_freq_hz);
1026
1027 fi.fdt = fdt;
1028 fi.path = "/pci@80000000";
1029 pci_bus = PCI_BUS(qdev_get_child_bus(pm->nb, "pci.0"));
1030 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
1031
1032 return fdt;
1033 }
1034
1035 static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size)
1036 {
1037 FDTInfo fi;
1038 PCIBus *pci_bus;
1039 void *fdt = load_dtb("pegasos2.dtb", fdt_size);
1040
1041 if (!fdt) {
1042 return NULL;
1043 }
1044 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
1045
1046 add_cpu_info(fdt, pm->cpu, pm->bus_freq_hz);
1047
1048 fi.fdt = fdt;
1049 fi.path = "/pci@c0000000";
1050 pci_bus = mv64361_get_pci_bus(pm->nb, 0);
1051 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
1052 fi.path = "/pci@80000000";
1053 pci_bus = mv64361_get_pci_bus(pm->nb, 1);
1054 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
1055
1056 return fdt;
1057 }