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1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016-2024, IBM Corporation.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/datadir.h"
24 #include "qemu/log.h"
25 #include "qemu/units.h"
26 #include "qemu/cutils.h"
27 #include "qapi/error.h"
28 #include "system/physmem.h"
29 #include "system/qtest.h"
30 #include "system/system.h"
31 #include "system/numa.h"
32 #include "system/reset.h"
33 #include "system/runstate.h"
34 #include "system/cpus.h"
35 #include "system/device_tree.h"
36 #include "system/hw_accel.h"
37 #include "target/ppc/cpu.h"
38 #include "hw/ppc/fdt.h"
39 #include "hw/ppc/ppc.h"
40 #include "hw/ppc/pnv.h"
41 #include "hw/ppc/pnv_core.h"
42 #include "hw/core/loader.h"
43 #include "hw/core/nmi.h"
44 #include "qapi/visitor.h"
45 #include "hw/intc/intc.h"
46 #include "hw/ipmi/ipmi.h"
47 #include "target/ppc/mmu-hash64.h"
48 #include "hw/pci/msi.h"
49 #include "hw/pci-host/pnv_phb.h"
50 #include "hw/pci-host/pnv_phb3.h"
51 #include "hw/pci-host/pnv_phb4.h"
52
53 #include "hw/ppc/xics.h"
54 #include "hw/core/qdev-properties.h"
55 #include "hw/ppc/pnv_chip.h"
56 #include "hw/ppc/pnv_xscom.h"
57 #include "hw/ppc/pnv_pnor.h"
58 #include "hw/ppc/pnv_mpipl.h"
59
60 #include "hw/isa/isa.h"
61 #include "hw/char/serial-isa.h"
62 #include "hw/rtc/mc146818rtc.h"
63 #include "exec/cpu-common.h"
64
65 #include <libfdt.h>
66
67 #define FDT_MAX_SIZE (1 * MiB)
68
69 #define FW_FILE_NAME "skiboot.lid"
70 #define FW_LOAD_ADDR 0x0
71 #define FW_MAX_SIZE (16 * MiB)
72
73 #define PNOR_FILE_NAME "pnv-pnor.bin"
74
75 #define KERNEL_LOAD_ADDR 0x20000000
76 #define KERNEL_MAX_SIZE (128 * MiB)
77 #define INITRD_LOAD_ADDR 0x28000000
78 #define INITRD_MAX_SIZE (128 * MiB)
79
80 static const char *pnv_chip_core_typename(const PnvChip *o)
81 {
82 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
83 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
84 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
85 const char *core_type = object_class_get_name(object_class_by_name(s));
86 g_free(s);
87 return core_type;
88 }
89
90 /*
91 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
92 * 4 * 4 sockets * 12 cores * 8 threads = 1536
93 * Let's make it 2^11
94 */
95 #define MAX_CPUS 2048
96
97 /*
98 * Memory nodes are created by hostboot, one for each range of memory
99 * that has a different "affinity". In practice, it means one range
100 * per chip.
101 */
102 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
103 {
104 char *mem_name;
105 uint64_t mem_reg_property[2];
106 int off;
107
108 mem_reg_property[0] = cpu_to_be64(start);
109 mem_reg_property[1] = cpu_to_be64(size);
110
111 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
112 off = fdt_add_subnode(fdt, 0, mem_name);
113 g_free(mem_name);
114
115 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
116 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
117 sizeof(mem_reg_property))));
118 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
119 }
120
121 static int get_cpus_node(void *fdt)
122 {
123 int cpus_offset = fdt_path_offset(fdt, "/cpus");
124
125 if (cpus_offset < 0) {
126 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
127 if (cpus_offset) {
128 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
129 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
130 }
131 }
132 _FDT(cpus_offset);
133 return cpus_offset;
134 }
135
136 /*
137 * The PowerNV cores (and threads) need to use real HW ids and not an
138 * incremental index like it has been done on other platforms. This HW
139 * id is stored in the CPU PIR, it is used to create cpu nodes in the
140 * device tree, used in XSCOM to address cores and in interrupt
141 * servers.
142 */
143 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
144 {
145 PowerPCCPU *cpu = pc->threads[0];
146 CPUState *cs = CPU(cpu);
147 DeviceClass *dc = DEVICE_GET_CLASS(cs);
148 int smt_threads = CPU_CORE(pc)->nr_threads;
149 CPUPPCState *env = &cpu->env;
150 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
151 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
152 uint32_t *servers_prop;
153 int i;
154 uint32_t pir, tir;
155 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
156 0xffffffff, 0xffffffff};
157 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
158 uint32_t cpufreq = 1000000000;
159 uint32_t page_sizes_prop[64];
160 size_t page_sizes_prop_size;
161 int offset;
162 char *nodename;
163 int cpus_offset = get_cpus_node(fdt);
164
165 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir);
166
167 /* Only one DT node per (big) core */
168 g_assert(tir == 0);
169
170 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
171 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
172 _FDT(offset);
173 g_free(nodename);
174
175 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
176
177 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
178 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
179 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
180
181 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
182 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
183 env->dcache_line_size)));
184 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
185 env->dcache_line_size)));
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
187 env->icache_line_size)));
188 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
189 env->icache_line_size)));
190
191 if (pcc->l1_dcache_size) {
192 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
193 pcc->l1_dcache_size)));
194 } else {
195 warn_report("Unknown L1 dcache size for cpu");
196 }
197 if (pcc->l1_icache_size) {
198 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
199 pcc->l1_icache_size)));
200 } else {
201 warn_report("Unknown L1 icache size for cpu");
202 }
203
204 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
205 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
206 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
207 cpu->hash64_opts->slb_size)));
208 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
209 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
210
211 if (ppc_has_spr(cpu, SPR_PURR)) {
212 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
213 }
214
215 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
216 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
217 segs, sizeof(segs))));
218 }
219
220 /*
221 * Advertise VMX/VSX (vector extensions) if available
222 * 0 / no property == no vector extensions
223 * 1 == VMX / Altivec available
224 * 2 == VSX available
225 */
226 if (env->insns_flags & PPC_ALTIVEC) {
227 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
228
229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
230 }
231
232 /*
233 * Advertise DFP (Decimal Floating Point) if available
234 * 0 / no property == no DFP
235 * 1 == DFP available
236 */
237 if (env->insns_flags2 & PPC2_DFP) {
238 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
239 }
240
241 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
242 sizeof(page_sizes_prop));
243 if (page_sizes_prop_size) {
244 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
245 page_sizes_prop, page_sizes_prop_size)));
246 }
247
248 /* Build interrupt servers properties */
249 if (pc->big_core) {
250 servers_prop = g_new(uint32_t, smt_threads * 2);
251 for (i = 0; i < smt_threads; i++) {
252 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
253 servers_prop[i * 2] = cpu_to_be32(pir);
254
255 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL);
256 servers_prop[i * 2 + 1] = cpu_to_be32(pir);
257 }
258 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
259 servers_prop, sizeof(*servers_prop) * smt_threads
260 * 2)));
261 } else {
262 servers_prop = g_new(uint32_t, smt_threads);
263 for (i = 0; i < smt_threads; i++) {
264 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
265 servers_prop[i] = cpu_to_be32(pir);
266 }
267 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
268 servers_prop, sizeof(*servers_prop) * smt_threads)));
269 }
270 g_free(servers_prop);
271
272 return offset;
273 }
274
275 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
276 uint32_t nr_threads)
277 {
278 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
279 uint32_t pir;
280 uint64_t addr;
281 char *name;
282 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
283 uint32_t irange[2], i, rsize;
284 uint64_t *reg;
285 int offset;
286
287 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL);
288 addr = PNV_ICP_BASE(chip) | (pir << 12);
289
290 irange[0] = cpu_to_be32(pir);
291 irange[1] = cpu_to_be32(nr_threads);
292
293 rsize = sizeof(uint64_t) * 2 * nr_threads;
294 reg = g_malloc(rsize);
295 for (i = 0; i < nr_threads; i++) {
296 /* We know P8 PIR is linear with thread id */
297 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
298 reg[i * 2 + 1] = cpu_to_be64(0x1000);
299 }
300
301 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
302 offset = fdt_add_subnode(fdt, 0, name);
303 _FDT(offset);
304 g_free(name);
305
306 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
307 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
308 _FDT((fdt_setprop_string(fdt, offset, "device_type",
309 "PowerPC-External-Interrupt-Presentation")));
310 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
311 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
312 irange, sizeof(irange))));
313 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
314 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
315 g_free(reg);
316 }
317
318 /*
319 * Adds a PnvPHB to the chip on P8.
320 * Implemented here, like for defaults PHBs
321 */
322 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
323 {
324 Pnv8Chip *chip8 = PNV8_CHIP(chip);
325
326 phb->chip = chip;
327
328 chip8->phbs[chip8->num_phbs] = phb;
329 chip8->num_phbs++;
330 return chip;
331 }
332
333 /*
334 * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
335 * HTM is always enabled because TCG does implement HTM, it's just a
336 * degenerate implementation.
337 */
338 static const uint8_t pa_features_207[] = { 24, 0,
339 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
340 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
341 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
342 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
343
344 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
345 {
346 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
347 int i;
348
349 pnv_dt_xscom(chip, fdt, 0,
350 cpu_to_be64(PNV_XSCOM_BASE(chip)),
351 cpu_to_be64(PNV_XSCOM_SIZE),
352 compat, sizeof(compat));
353
354 for (i = 0; i < chip->nr_cores; i++) {
355 PnvCore *pnv_core = chip->cores[i];
356 int offset;
357
358 offset = pnv_dt_core(chip, pnv_core, fdt);
359
360 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
361 pa_features_207, sizeof(pa_features_207))));
362
363 /* Interrupt Control Presenters (ICP). One per core. */
364 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
365 }
366
367 if (chip->ram_size) {
368 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
369 }
370 }
371
372 /*
373 * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
374 */
375 static const uint8_t pa_features_300[] = { 66, 0,
376 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
377 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
378 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
379 /* 6: DS207 */
380 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
381 /* 16: Vector */
382 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
383 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
384 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
385 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
387 /* 32: LE atomic, 34: EBB + ext EBB */
388 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
389 /* 40: Radix MMU */
390 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
391 /* 42: PM, 44: PC RA, 46: SC vec'd */
392 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
393 /* 48: SIMD, 50: QP BFP, 52: String */
394 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
395 /* 54: DecFP, 56: DecI, 58: SHA */
396 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
397 /* 60: NM atomic, 62: RNG */
398 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
399 };
400
401 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
402 {
403 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
404 int i;
405
406 pnv_dt_xscom(chip, fdt, 0,
407 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
408 cpu_to_be64(PNV9_XSCOM_SIZE),
409 compat, sizeof(compat));
410
411 for (i = 0; i < chip->nr_cores; i++) {
412 PnvCore *pnv_core = chip->cores[i];
413 int offset;
414
415 offset = pnv_dt_core(chip, pnv_core, fdt);
416
417 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
418 pa_features_300, sizeof(pa_features_300))));
419
420 if (pnv_core->big_core) {
421 i++; /* Big-core groups two QEMU cores */
422 }
423 }
424
425 if (chip->ram_size) {
426 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
427 }
428
429 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
430 }
431
432 /*
433 * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
434 * always disables copy/paste.
435 */
436 static const uint8_t pa_features_31[] = { 74, 0,
437 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
438 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
439 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
440 /* 6: DS207 */
441 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
442 /* 16: Vector */
443 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
444 /* 18: Vec. Scalar, 20: Vec. XOR */
445 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
446 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
448 /* 32: LE atomic, 34: EBB + ext EBB */
449 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
450 /* 40: Radix MMU */
451 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
452 /* 42: PM, 44: PC RA, 46: SC vec'd */
453 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
454 /* 48: SIMD, 50: QP BFP, 52: String */
455 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
456 /* 54: DecFP, 56: DecI, 58: SHA */
457 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
458 /* 60: NM atomic, 62: RNG */
459 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
460 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
461 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
462 /* 72: [P]HASHST/[P]HASHCHK */
463 0x80, 0x00, /* 72 - 73 */
464 };
465
466 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
467 {
468 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
469 int i;
470
471 pnv_dt_xscom(chip, fdt, 0,
472 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
473 cpu_to_be64(PNV10_XSCOM_SIZE),
474 compat, sizeof(compat));
475
476 for (i = 0; i < chip->nr_cores; i++) {
477 PnvCore *pnv_core = chip->cores[i];
478 int offset;
479
480 offset = pnv_dt_core(chip, pnv_core, fdt);
481
482 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
483 pa_features_31, sizeof(pa_features_31))));
484
485 if (pnv_core->big_core) {
486 i++; /* Big-core groups two QEMU cores */
487 }
488 }
489
490 if (chip->ram_size) {
491 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
492 }
493
494 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
495 }
496
497 static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt)
498 {
499 static const char compat[] = "ibm,power11-xscom\0ibm,xscom";
500 int i;
501
502 pnv_dt_xscom(chip, fdt, 0,
503 cpu_to_be64(PNV11_XSCOM_BASE(chip)),
504 cpu_to_be64(PNV11_XSCOM_SIZE),
505 compat, sizeof(compat));
506
507 for (i = 0; i < chip->nr_cores; i++) {
508 PnvCore *pnv_core = chip->cores[i];
509 int offset;
510
511 offset = pnv_dt_core(chip, pnv_core, fdt);
512
513 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
514 pa_features_31, sizeof(pa_features_31))));
515
516 if (pnv_core->big_core) {
517 i++; /* Big-core groups two QEMU cores */
518 }
519 }
520
521 if (chip->ram_size) {
522 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
523 }
524
525 pnv_dt_lpc(chip, fdt, 0, PNV11_LPCM_BASE(chip), PNV11_LPCM_SIZE);
526 }
527
528 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
529 {
530 uint32_t io_base = d->ioport_id;
531 uint32_t io_regs[] = {
532 cpu_to_be32(1),
533 cpu_to_be32(io_base),
534 cpu_to_be32(2)
535 };
536 char *name;
537 int node;
538
539 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
540 node = fdt_add_subnode(fdt, lpc_off, name);
541 _FDT(node);
542 g_free(name);
543
544 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
545 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
546 }
547
548 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
549 {
550 const char compatible[] = "ns16550\0pnpPNP,501";
551 uint32_t io_base = d->ioport_id;
552 uint32_t io_regs[] = {
553 cpu_to_be32(1),
554 cpu_to_be32(io_base),
555 cpu_to_be32(8)
556 };
557 uint32_t irq;
558 char *name;
559 int node;
560
561 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
562
563 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
564 node = fdt_add_subnode(fdt, lpc_off, name);
565 _FDT(node);
566 g_free(name);
567
568 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
569 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
570 sizeof(compatible))));
571
572 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
573 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
574 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
575 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
576 fdt_get_phandle(fdt, lpc_off))));
577
578 /* This is needed by Linux */
579 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
580 }
581
582 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
583 {
584 const char compatible[] = "bt\0ipmi-bt";
585 uint32_t io_base;
586 uint32_t io_regs[] = {
587 cpu_to_be32(1),
588 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
589 cpu_to_be32(3)
590 };
591 uint32_t irq;
592 char *name;
593 int node;
594
595 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
596 io_regs[1] = cpu_to_be32(io_base);
597
598 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
599
600 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
601 node = fdt_add_subnode(fdt, lpc_off, name);
602 _FDT(node);
603 g_free(name);
604
605 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
606 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
607 sizeof(compatible))));
608
609 /* Mark it as reserved to avoid Linux trying to claim it */
610 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
611 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
612 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
613 fdt_get_phandle(fdt, lpc_off))));
614 }
615
616 typedef struct ForeachPopulateArgs {
617 void *fdt;
618 int offset;
619 } ForeachPopulateArgs;
620
621 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
622 {
623 ForeachPopulateArgs *args = opaque;
624 ISADevice *d = ISA_DEVICE(dev);
625
626 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
627 pnv_dt_rtc(d, args->fdt, args->offset);
628 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
629 pnv_dt_serial(d, args->fdt, args->offset);
630 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
631 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
632 } else {
633 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
634 d->ioport_id);
635 }
636
637 return 0;
638 }
639
640 /*
641 * The default LPC bus of a multichip system is on chip 0. It's
642 * recognized by the firmware (skiboot) using a "primary" property.
643 */
644 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
645 {
646 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
647 ForeachPopulateArgs args = {
648 .fdt = fdt,
649 .offset = isa_offset,
650 };
651 uint32_t phandle;
652
653 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
654
655 phandle = qemu_fdt_alloc_phandle(fdt);
656 assert(phandle > 0);
657 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
658
659 /*
660 * ISA devices are not necessarily parented to the ISA bus so we
661 * can not use object_child_foreach()
662 */
663 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
664 &args);
665 }
666
667 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
668 {
669 int off;
670
671 off = fdt_add_subnode(fdt, 0, "ibm,opal");
672 off = fdt_add_subnode(fdt, off, "power-mgt");
673
674 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
675 }
676
677 static void pnv_dt_mpipl_dump(PnvMachineState *pnv, void *fdt)
678 {
679 int off;
680
681 /*
682 * Add "dump" node so kernel knows MPIPL (aka fadump) is supported
683 *
684 * Note: This is only needed to be done since we are passing device tree to
685 * opal
686 *
687 * In case HDAT is supported in future, then opal can add these nodes by
688 * itself based on system attribute having MPIPL_SUPPORTED bit set
689 */
690 off = fdt_add_subnode(fdt, 0, "ibm,opal");
691 if (off == -FDT_ERR_EXISTS) {
692 off = fdt_path_offset(fdt, "/ibm,opal");
693 }
694
695 _FDT(off);
696 off = fdt_add_subnode(fdt, off, "dump");
697 _FDT(off);
698 _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,opal-dump")));
699
700 /* Add kernel and initrd as fw-load-area */
701 uint64_t fw_load_area[4] = {
702 cpu_to_be64(KERNEL_LOAD_ADDR), cpu_to_be64(KERNEL_MAX_SIZE),
703 cpu_to_be64(INITRD_LOAD_ADDR), cpu_to_be64(INITRD_MAX_SIZE)
704 };
705
706 _FDT((fdt_setprop(fdt, off, "fw-load-area",
707 fw_load_area, sizeof(fw_load_area))));
708 }
709
710 static void *pnv_dt_create(MachineState *machine)
711 {
712 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
713 PnvMachineState *pnv = PNV_MACHINE(machine);
714 void *fdt;
715 char *buf;
716 int off;
717 int i;
718
719 fdt = g_malloc0(FDT_MAX_SIZE);
720 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
721
722 /* /qemu node */
723 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
724
725 /* Root node */
726 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
727 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
728 _FDT((fdt_setprop_string(fdt, 0, "model",
729 "IBM PowerNV (emulated by qemu)")));
730 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
731
732 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
733 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
734 if (qemu_uuid_set) {
735 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
736 }
737 g_free(buf);
738
739 off = fdt_add_subnode(fdt, 0, "chosen");
740 if (machine->kernel_cmdline) {
741 _FDT((fdt_setprop_string(fdt, off, "bootargs",
742 machine->kernel_cmdline)));
743 }
744
745 if (pnv->initrd_size) {
746 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
747 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
748
749 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
750 &start_prop, sizeof(start_prop))));
751 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
752 &end_prop, sizeof(end_prop))));
753 }
754
755 /* Populate device tree for each chip */
756 for (i = 0; i < pnv->num_chips; i++) {
757 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
758 }
759
760 /* Populate ISA devices on chip 0 */
761 pnv_dt_isa(pnv, fdt);
762
763 if (pnv->bmc) {
764 pnv_dt_bmc_sensors(pnv->bmc, fdt);
765 }
766
767 /* Create an extra node for power management on machines that support it */
768 if (pmc->dt_power_mgt) {
769 pmc->dt_power_mgt(pnv, fdt);
770 }
771
772 /* Advertise support for MPIPL */
773 pnv_dt_mpipl_dump(pnv, fdt);
774
775 return fdt;
776 }
777
778 static void pnv_powerdown_notify(Notifier *n, void *opaque)
779 {
780 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
781
782 if (pnv->bmc) {
783 pnv_bmc_powerdown(pnv->bmc);
784 }
785 }
786
787 static void pnv_reset(MachineState *machine, ResetType type)
788 {
789 PnvMachineState *pnv = PNV_MACHINE(machine);
790 void *fdt;
791 int node_offset;
792 bool mpipl_write_succeeded = false;
793
794 qemu_devices_reset(type);
795
796 /*
797 * Only on success of writing MPIPL data will the next boot be provided
798 * "mpipl-boot" property in device tree
799 * Otherwise boot like a normal non-MPIPL boot
800 */
801 if (pnv->mpipl_state.is_next_boot_mpipl) {
802 /* Write the preserved MDRT and CPU State Data */
803 mpipl_write_succeeded = do_mpipl_write(pnv);
804 }
805
806 /* Only create new dt if not provided in -dtb */
807 if (!machine->dtb) {
808 fdt = pnv_dt_create(machine);
809 _FDT((fdt_pack(fdt)));
810 } else {
811 fdt = machine->fdt;
812 }
813
814 /*
815 * If it's a MPIPL boot, add the "mpipl-boot" property, and reset the
816 * boolean for MPIPL boot for next boot
817 */
818 if (mpipl_write_succeeded) {
819 void *fdt_copy = g_malloc0(FDT_MAX_SIZE);
820
821 /* Create a writable copy of the fdt */
822 _FDT((fdt_open_into(fdt, fdt_copy, FDT_MAX_SIZE)));
823
824 node_offset = fdt_path_offset(fdt_copy, "/ibm,opal/dump");
825 _FDT((fdt_appendprop_u64(fdt_copy, node_offset, "mpipl-boot", 1)));
826
827 /* Update the fdt, and free the original fdt */
828 if (fdt != machine->fdt) {
829 /*
830 * Only free the fdt if it's not machine->fdt, to prevent
831 * double free, since we already free machine->fdt later
832 */
833 g_free(fdt);
834 }
835 fdt = fdt_copy;
836
837 /* This boot is an MPIPL, reset the boolean for next boot */
838 pnv->mpipl_state.is_next_boot_mpipl = false;
839 } else {
840 /*
841 * Set the "Thread Register State Entry Size", so that firmware can
842 * allocate enough memory to capture CPU state in the event of a
843 * crash
844 */
845
846 MpiplProcDumpArea proc_area = {
847 .version = PROC_DUMP_AREA_VERSION_P9,
848 .thread_size = cpu_to_be32(sizeof(MpiplPreservedCPUState)),
849 };
850
851 physical_memory_write(PROC_DUMP_AREA_OFF, &proc_area,
852 sizeof(proc_area));
853 }
854
855 physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
856
857 /* Free previous device tree set by pnv_init/reset/machine_init_done */
858 g_free(machine->fdt);
859 machine->fdt = fdt;
860 }
861
862 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
863 {
864 Pnv8Chip *chip8 = PNV8_CHIP(chip);
865 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
866
867 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq);
868
869 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
870 }
871
872 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
873 {
874 Pnv9Chip *chip9 = PNV9_CHIP(chip);
875 qemu_irq irq;
876
877 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
878 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq);
879
880 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0);
881 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq);
882 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1);
883 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq);
884 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2);
885 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq);
886 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3);
887 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq);
888
889 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
890 }
891
892 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
893 {
894 Pnv10Chip *chip10 = PNV10_CHIP(chip);
895 qemu_irq irq;
896
897 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
898 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq);
899
900 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0);
901 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq);
902 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1);
903 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq);
904 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2);
905 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq);
906 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3);
907 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq);
908
909 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
910 }
911
912 static ISABus *pnv_chip_power11_isa_create(PnvChip *chip, Error **errp)
913 {
914 Pnv11Chip *chip11 = PNV11_CHIP(chip);
915 qemu_irq irq;
916
917 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPCHC);
918 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "LPCHC", 0, irq);
919
920 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ0);
921 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 0, irq);
922 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ1);
923 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 1, irq);
924 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ2);
925 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 2, irq);
926 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ3);
927 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 3, irq);
928
929 return pnv_lpc_isa_create(&chip11->lpc, false, errp);
930 }
931
932 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
933 {
934 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
935 }
936
937 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf)
938 {
939 Pnv8Chip *chip8 = PNV8_CHIP(chip);
940 int i;
941
942 ics_pic_print_info(&chip8->psi.ics, buf);
943
944 for (i = 0; i < chip8->num_phbs; i++) {
945 PnvPHB *phb = chip8->phbs[i];
946 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
947
948 pnv_phb3_msi_pic_print_info(&phb3->msis, buf);
949 ics_pic_print_info(&phb3->lsis, buf);
950 }
951 }
952
953 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
954 {
955 GString *buf = opaque;
956 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
957
958 if (!phb) {
959 return 0;
960 }
961
962 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf);
963
964 return 0;
965 }
966
967 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf)
968 {
969 Pnv9Chip *chip9 = PNV9_CHIP(chip);
970
971 pnv_xive_pic_print_info(&chip9->xive, buf);
972 pnv_psi_pic_print_info(&chip9->psi, buf);
973 object_child_foreach_recursive(OBJECT(chip),
974 pnv_chip_power9_pic_print_info_child, buf);
975 }
976
977 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
978 uint32_t core_id)
979 {
980 return PNV_XSCOM_EX_BASE(core_id);
981 }
982
983 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
984 uint32_t core_id)
985 {
986 return PNV9_XSCOM_EC_BASE(core_id);
987 }
988
989 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
990 uint32_t core_id)
991 {
992 return PNV10_XSCOM_EC_BASE(core_id);
993 }
994
995 static uint64_t pnv_chip_power11_xscom_core_base(PnvChip *chip,
996 uint32_t core_id)
997 {
998 return PNV11_XSCOM_EC_BASE(core_id);
999 }
1000
1001 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
1002 {
1003 PowerPCCPUClass *ppc_default =
1004 POWERPC_CPU_CLASS(object_class_by_name(default_type));
1005 PowerPCCPUClass *ppc =
1006 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
1007
1008 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
1009 }
1010
1011 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
1012 {
1013 ISADevice *dev = isa_new("isa-ipmi-bt");
1014
1015 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
1016 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
1017 isa_realize_and_unref(dev, bus, &error_fatal);
1018 }
1019
1020 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf)
1021 {
1022 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1023
1024 pnv_xive2_pic_print_info(&chip10->xive, buf);
1025 pnv_psi_pic_print_info(&chip10->psi, buf);
1026 object_child_foreach_recursive(OBJECT(chip),
1027 pnv_chip_power9_pic_print_info_child, buf);
1028 }
1029
1030 static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
1031 {
1032 Pnv11Chip *chip11 = PNV11_CHIP(chip);
1033
1034 pnv_xive2_pic_print_info(&chip11->xive, buf);
1035 pnv_psi_pic_print_info(&chip11->psi, buf);
1036 object_child_foreach_recursive(OBJECT(chip),
1037 pnv_chip_power9_pic_print_info_child, buf);
1038 }
1039
1040 /* Always give the first 1GB to chip 0 else we won't boot */
1041 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
1042 {
1043 MachineState *machine = MACHINE(pnv);
1044 uint64_t ram_per_chip;
1045
1046 assert(machine->ram_size >= 1 * GiB);
1047
1048 ram_per_chip = machine->ram_size / pnv->num_chips;
1049 if (ram_per_chip >= 1 * GiB) {
1050 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
1051 }
1052
1053 assert(pnv->num_chips > 1);
1054
1055 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
1056 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
1057 }
1058
1059 static void pnv_machine_init_done(Notifier *notifier, void *data)
1060 {
1061 PnvMachineState *pnv = container_of(notifier, PnvMachineState, machine_init_done);
1062 MachineState *machine = MACHINE(pnv);
1063 IPMIBmc *bmc;
1064
1065 /*
1066 * The machine should provide by default an internal BMC simulator.
1067 * If not, try to use the BMC device that was provided on the command
1068 * line.
1069 */
1070 bmc = pnv_bmc_find(&error_fatal);
1071 if (!pnv->bmc) {
1072 if (!bmc) {
1073 if (!qtest_enabled()) {
1074 warn_report("machine has no BMC device. Use '-device "
1075 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
1076 "to define one");
1077 }
1078 } else {
1079 pnv_bmc_set_pnor(bmc, pnv->pnor);
1080 pnv->bmc = bmc;
1081 }
1082 }
1083
1084 if (!machine->fdt) {
1085 machine->fdt = pnv_dt_create(machine);
1086 _FDT((fdt_pack(machine->fdt)));
1087 }
1088 }
1089
1090 static void pnv_init(MachineState *machine)
1091 {
1092 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
1093 PnvMachineState *pnv = PNV_MACHINE(machine);
1094 MachineClass *mc = MACHINE_GET_CLASS(machine);
1095 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
1096 int max_smt_threads = pmc->max_smt_threads;
1097 char *fw_filename;
1098 uint64_t chip_ram_start = 0;
1099 int i;
1100 char *chip_typename;
1101 DriveInfo *pnor;
1102 DeviceState *dev;
1103
1104 if (kvm_enabled()) {
1105 error_report("machine %s does not support the KVM accelerator",
1106 mc->name);
1107 exit(EXIT_FAILURE);
1108 }
1109
1110 /* allocate RAM */
1111 if (machine->ram_size < mc->default_ram_size) {
1112 char *sz = size_to_str(mc->default_ram_size);
1113 error_report("Invalid RAM size, should be bigger than %s", sz);
1114 g_free(sz);
1115 exit(EXIT_FAILURE);
1116 }
1117
1118 /* checks for invalid option combinations */
1119 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) {
1120 error_report("-append and -dtb cannot be used together, as passed"
1121 " command line is ignored in case of custom dtb");
1122 exit(EXIT_FAILURE);
1123 }
1124
1125 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
1126
1127 /*
1128 * Create our simple PNOR device
1129 */
1130 dev = qdev_new(TYPE_PNV_PNOR);
1131 pnor = drive_get(IF_MTD, 0, 0);
1132 if (!pnor && defaults_enabled()) {
1133 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, PNOR_FILE_NAME);
1134 if (!fw_filename) {
1135 warn_report("Could not find PNOR '%s'", PNOR_FILE_NAME);
1136 } else {
1137 QemuOpts *opts;
1138 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on");
1139 pnor = drive_new(opts, IF_MTD, &error_fatal);
1140 g_free(fw_filename);
1141 }
1142 }
1143 if (pnor) {
1144 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
1145 }
1146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1147 pnv->pnor = PNV_PNOR(dev);
1148
1149 /* load skiboot firmware */
1150 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1151 if (!fw_filename) {
1152 error_report("Could not find OPAL firmware '%s'", bios_name);
1153 exit(1);
1154 }
1155
1156 load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE,
1157 &error_fatal);
1158 g_free(fw_filename);
1159
1160 /* load kernel */
1161 if (machine->kernel_filename) {
1162 load_image_targphys(machine->kernel_filename,
1163 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE, &error_fatal);
1164 }
1165
1166 /* load initrd */
1167 if (machine->initrd_filename) {
1168 pnv->initrd_base = INITRD_LOAD_ADDR;
1169 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
1170 pnv->initrd_base,
1171 INITRD_MAX_SIZE, &error_fatal);
1172 }
1173
1174 /* load dtb if passed */
1175 if (machine->dtb) {
1176 int fdt_size;
1177
1178 warn_report("with manually passed dtb, some options like '-append'"
1179 " will get ignored and the dtb passed will be used as-is");
1180
1181 /* read the file 'machine->dtb', and load it into 'fdt' buffer */
1182 machine->fdt = load_device_tree(machine->dtb, &fdt_size);
1183 if (!machine->fdt) {
1184 error_report("Could not load dtb '%s'", machine->dtb);
1185 exit(1);
1186 }
1187 }
1188
1189 /* MSIs are supported on this platform */
1190 msi_nonbroken = true;
1191
1192 /*
1193 * Check compatibility of the specified CPU with the machine
1194 * default.
1195 */
1196 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
1197 error_report("invalid CPU model '%s' for %s machine",
1198 machine->cpu_type, mc->name);
1199 exit(1);
1200 }
1201
1202 /* Create the processor chips */
1203 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
1204 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
1205 i, machine->cpu_type);
1206 if (!object_class_by_name(chip_typename)) {
1207 error_report("invalid chip model '%.*s' for %s machine",
1208 i, machine->cpu_type, mc->name);
1209 exit(1);
1210 }
1211
1212 /* Set lpar-per-core mode if lpar-per-thread is not supported */
1213 if (!pmc->has_lpar_per_thread) {
1214 pnv->lpar_per_core = true;
1215 }
1216
1217 pnv->num_chips =
1218 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
1219
1220 if (pnv->big_core) {
1221 if (machine->smp.threads % 2 == 1) {
1222 error_report("Cannot support %d threads with big-core option "
1223 "because it must be an even number",
1224 machine->smp.threads);
1225 exit(1);
1226 }
1227 max_smt_threads *= 2;
1228 }
1229
1230 if (machine->smp.threads > max_smt_threads) {
1231 error_report("Cannot support more than %d threads/core "
1232 "on %s machine", max_smt_threads, mc->desc);
1233 if (pmc->max_smt_threads == 4) {
1234 error_report("(use big-core=on for 8 threads per core)");
1235 }
1236 exit(1);
1237 }
1238
1239 if (pnv->big_core) {
1240 /*
1241 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore
1242 * per core, so adjust topology here. pnv_dt_core() processor
1243 * device-tree and TCG SMT code make the 2 cores appear as one big core
1244 * from software point of view. pnv pervasive models and xscoms tend to
1245 * see the big core as 2 small core halves.
1246 */
1247 machine->smp.cores *= 2;
1248 machine->smp.threads /= 2;
1249 }
1250
1251 if (!is_power_of_2(machine->smp.threads)) {
1252 error_report("Cannot support %d threads/core on a powernv "
1253 "machine because it must be a power of 2",
1254 machine->smp.threads);
1255 exit(1);
1256 }
1257
1258 /*
1259 * TODO: should we decide on how many chips we can create based
1260 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1261 */
1262 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
1263 error_report("invalid number of chips: '%d'", pnv->num_chips);
1264 error_printf(
1265 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
1266 exit(1);
1267 }
1268
1269 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
1270 for (i = 0; i < pnv->num_chips; i++) {
1271 char chip_name[32];
1272 Object *chip = OBJECT(qdev_new(chip_typename));
1273 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
1274
1275 pnv->chips[i] = PNV_CHIP(chip);
1276
1277 /* Distribute RAM among the chips */
1278 object_property_set_int(chip, "ram-start", chip_ram_start,
1279 &error_fatal);
1280 object_property_set_int(chip, "ram-size", chip_ram_size,
1281 &error_fatal);
1282 chip_ram_start += chip_ram_size;
1283
1284 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
1285 object_property_add_child(OBJECT(pnv), chip_name, chip);
1286 object_property_set_int(chip, "chip-id", i, &error_fatal);
1287 object_property_set_int(chip, "nr-cores", machine->smp.cores,
1288 &error_fatal);
1289 object_property_set_int(chip, "nr-threads", machine->smp.threads,
1290 &error_fatal);
1291 object_property_set_bool(chip, "big-core", pnv->big_core,
1292 &error_fatal);
1293 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core,
1294 &error_fatal);
1295 /*
1296 * The POWER8 machine use the XICS interrupt interface.
1297 * Propagate the XICS fabric to the chip and its controllers.
1298 */
1299 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
1300 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
1301 }
1302 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
1303 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
1304 &error_abort);
1305 }
1306 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
1307 }
1308 g_free(chip_typename);
1309
1310 /* Instantiate ISA bus on chip 0 */
1311 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
1312
1313 /* Create serial port */
1314 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1315
1316 /* Create an RTC ISA device too */
1317 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
1318
1319 /*
1320 * Create the machine BMC simulator and the IPMI BT device for
1321 * communication with the BMC
1322 */
1323 if (defaults_enabled()) {
1324 pnv->bmc = pnv_bmc_create(pnv->pnor);
1325 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
1326 }
1327
1328 /*
1329 * The PNOR is mapped on the LPC FW address space by the BMC.
1330 * Since we can not reach the remote BMC machine with LPC memops,
1331 * map it always for now.
1332 */
1333 memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address,
1334 &pnv->pnor->mmio);
1335
1336 /*
1337 * OpenPOWER systems use a IPMI SEL Event message to notify the
1338 * host to powerdown
1339 */
1340 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1341 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1342
1343 /*
1344 * Create/Connect any machine-specific I2C devices
1345 */
1346 if (pmc->i2c_init) {
1347 pmc->i2c_init(pnv);
1348 }
1349
1350 pnv->machine_init_done.notify = pnv_machine_init_done;
1351 qemu_add_machine_init_done_notifier(&pnv->machine_init_done);
1352 }
1353
1354 /*
1355 * 0:21 Reserved - Read as zeros
1356 * 22:24 Chip ID
1357 * 25:28 Core number
1358 * 29:31 Thread ID
1359 */
1360 static void pnv_get_pir_tir_p8(PnvChip *chip,
1361 uint32_t core_id, uint32_t thread_id,
1362 uint32_t *pir, uint32_t *tir)
1363 {
1364 if (pir) {
1365 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id;
1366 }
1367 if (tir) {
1368 *tir = thread_id;
1369 }
1370 }
1371
1372 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1373 Error **errp)
1374 {
1375 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1376 Error *local_err = NULL;
1377 Object *obj;
1378 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1379
1380 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1381 if (local_err) {
1382 error_propagate(errp, local_err);
1383 return;
1384 }
1385
1386 pnv_cpu->intc = obj;
1387 }
1388
1389
1390 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1391 {
1392 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1393
1394 icp_reset(ICP(pnv_cpu->intc));
1395 }
1396
1397 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1398 {
1399 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1400
1401 icp_destroy(ICP(pnv_cpu->intc));
1402 pnv_cpu->intc = NULL;
1403 }
1404
1405 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1406 GString *buf)
1407 {
1408 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf);
1409 }
1410
1411 /*
1412 * 0:48 Reserved - Read as zeroes
1413 * 49:52 Node ID
1414 * 53:55 Chip ID
1415 * 56 Reserved - Read as zero
1416 * 57:61 Core number
1417 * 62:63 Thread ID
1418 *
1419 * We only care about the lower bits. uint32_t is fine for the moment.
1420 */
1421 static void pnv_get_pir_tir_p9(PnvChip *chip,
1422 uint32_t core_id, uint32_t thread_id,
1423 uint32_t *pir, uint32_t *tir)
1424 {
1425 if (chip->big_core) {
1426 /* Big-core interleaves thread ID between small-cores */
1427 thread_id <<= 1;
1428 thread_id |= core_id & 1;
1429 core_id >>= 1;
1430
1431 if (pir) {
1432 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id;
1433 }
1434 } else {
1435 if (pir) {
1436 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
1437 }
1438 }
1439 if (tir) {
1440 *tir = thread_id;
1441 }
1442 }
1443
1444 /*
1445 * 0:48 Reserved - Read as zeroes
1446 * 49:52 Node ID
1447 * 53:55 Chip ID
1448 * 56 Reserved - Read as zero
1449 * 57:59 Quad ID
1450 * 60 Core Chiplet Pair ID
1451 * 61:63 Thread/Core Chiplet ID t0-t2
1452 *
1453 * We only care about the lower bits. uint32_t is fine for the moment.
1454 */
1455 static void pnv_get_pir_tir_p10(PnvChip *chip,
1456 uint32_t core_id, uint32_t thread_id,
1457 uint32_t *pir, uint32_t *tir)
1458 {
1459 if (chip->big_core) {
1460 /* Big-core interleaves thread ID between small-cores */
1461 thread_id <<= 1;
1462 thread_id |= core_id & 1;
1463 core_id >>= 1;
1464
1465 if (pir) {
1466 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id;
1467 }
1468 } else {
1469 if (pir) {
1470 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
1471 }
1472 }
1473 if (tir) {
1474 *tir = thread_id;
1475 }
1476 }
1477
1478 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1479 Error **errp)
1480 {
1481 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1482 Error *local_err = NULL;
1483 Object *obj;
1484 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1485
1486 /*
1487 * The core creates its interrupt presenter but the XIVE interrupt
1488 * controller object is initialized afterwards. Hopefully, it's
1489 * only used at runtime.
1490 */
1491 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1492 &local_err);
1493 if (local_err) {
1494 error_propagate(errp, local_err);
1495 return;
1496 }
1497
1498 pnv_cpu->intc = obj;
1499 }
1500
1501 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1502 {
1503 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1504
1505 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1506 }
1507
1508 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1509 {
1510 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1511
1512 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1513 pnv_cpu->intc = NULL;
1514 }
1515
1516 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1517 GString *buf)
1518 {
1519 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1520 }
1521
1522 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1523 Error **errp)
1524 {
1525 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1526 Error *local_err = NULL;
1527 Object *obj;
1528 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1529
1530 /*
1531 * The core creates its interrupt presenter but the XIVE2 interrupt
1532 * controller object is initialized afterwards. Hopefully, it's
1533 * only used at runtime.
1534 */
1535 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1536 &local_err);
1537 if (local_err) {
1538 error_propagate(errp, local_err);
1539 return;
1540 }
1541
1542 pnv_cpu->intc = obj;
1543 }
1544
1545 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1546 {
1547 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1548
1549 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1550 }
1551
1552 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1553 {
1554 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1555
1556 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1557 pnv_cpu->intc = NULL;
1558 }
1559
1560 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1561 GString *buf)
1562 {
1563 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1564 }
1565
1566 static void *pnv_chip_power10_intc_get(PnvChip *chip)
1567 {
1568 return &PNV10_CHIP(chip)->xive;
1569 }
1570
1571 static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1572 Error **errp)
1573 {
1574 Pnv11Chip *chip11 = PNV11_CHIP(chip);
1575 Error *local_err = NULL;
1576 Object *obj;
1577 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1578
1579 /*
1580 * The core creates its interrupt presenter but the XIVE2 interrupt
1581 * controller object is initialized afterwards. Hopefully, it's
1582 * only used at runtime.
1583 */
1584 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive),
1585 &local_err);
1586 if (local_err) {
1587 error_propagate(errp, local_err);
1588 return;
1589 }
1590
1591 pnv_cpu->intc = obj;
1592 }
1593
1594 static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1595 {
1596 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1597
1598 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1599 }
1600
1601 static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1602 {
1603 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1604
1605 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1606 pnv_cpu->intc = NULL;
1607 }
1608
1609 static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1610 GString *buf)
1611 {
1612 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1613 }
1614
1615 static void *pnv_chip_power11_intc_get(PnvChip *chip)
1616 {
1617 return &PNV11_CHIP(chip)->xive;
1618 }
1619
1620 /*
1621 * Allowed core identifiers on a POWER8 Processor Chip :
1622 *
1623 * <EX0 reserved>
1624 * EX1 - Venice only
1625 * EX2 - Venice only
1626 * EX3 - Venice only
1627 * EX4
1628 * EX5
1629 * EX6
1630 * <EX7,8 reserved> <reserved>
1631 * EX9 - Venice only
1632 * EX10 - Venice only
1633 * EX11 - Venice only
1634 * EX12
1635 * EX13
1636 * EX14
1637 * <EX15 reserved>
1638 */
1639 #define POWER8_CORE_MASK (0x7e7eull)
1640
1641 /*
1642 * POWER9 has 24 cores, ids starting at 0x0
1643 */
1644 #define POWER9_CORE_MASK (0xffffffffffffffull)
1645
1646
1647 #define POWER10_CORE_MASK (0xffffffffffffffull)
1648
1649 #define POWER11_CORE_MASK (0xffffffffffffffull)
1650
1651 static void pnv_chip_power8_instance_init(Object *obj)
1652 {
1653 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1654 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1655 int i;
1656
1657 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1658 (Object **)&chip8->xics,
1659 object_property_allow_set_link,
1660 OBJ_PROP_LINK_STRONG);
1661
1662 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1663
1664 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1665
1666 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1667
1668 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1669
1670 if (defaults_enabled()) {
1671 chip8->num_phbs = pcc->num_phbs;
1672
1673 for (i = 0; i < chip8->num_phbs; i++) {
1674 Object *phb = object_new(TYPE_PNV_PHB);
1675
1676 /*
1677 * We need the chip to parent the PHB to allow the DT
1678 * to build correctly (via pnv_xscom_dt()).
1679 *
1680 * TODO: the PHB should be parented by a PEC device that, at
1681 * this moment, is not modelled powernv8/phb3.
1682 */
1683 object_property_add_child(obj, "phb[*]", phb);
1684 chip8->phbs[i] = PNV_PHB(phb);
1685 object_unref(phb);
1686 }
1687 }
1688
1689 }
1690
1691 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1692 {
1693 PnvChip *chip = PNV_CHIP(chip8);
1694 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1695 int i, j;
1696 char *name;
1697
1698 name = g_strdup_printf("icp-%x", chip->chip_id);
1699 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1700 g_free(name);
1701 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip),
1702 &chip8->icp_mmio);
1703
1704 /* Map the ICP registers for each thread */
1705 for (i = 0; i < chip->nr_cores; i++) {
1706 PnvCore *pnv_core = chip->cores[i];
1707 int core_hwid = CPU_CORE(pnv_core)->core_id;
1708
1709 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1710 uint32_t pir;
1711 PnvICPState *icp;
1712
1713 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL);
1714 icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1715
1716 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1717 &icp->mmio);
1718 }
1719 }
1720 }
1721
1722 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1723 {
1724 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1725 PnvChip *chip = PNV_CHIP(dev);
1726 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1727 Pnv8Psi *psi8 = &chip8->psi;
1728 Error *local_err = NULL;
1729 int i;
1730
1731 assert(chip8->xics);
1732
1733 /* XSCOM bridge is first */
1734 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip));
1735
1736 pcc->parent_realize(dev, &local_err);
1737 if (local_err) {
1738 error_propagate(errp, local_err);
1739 return;
1740 }
1741
1742 /* Processor Service Interface (PSI) Host Bridge */
1743 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip),
1744 &error_fatal);
1745 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS,
1746 OBJECT(chip8->xics), &error_abort);
1747 if (!qdev_realize(DEVICE(psi8), NULL, errp)) {
1748 return;
1749 }
1750 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1751 &PNV_PSI(psi8)->xscom_regs);
1752
1753 /* Create LPC controller */
1754 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1755 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1756
1757 chip->fw_mr = &chip8->lpc.isa_fw;
1758 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1759 (uint64_t) PNV_XSCOM_BASE(chip),
1760 PNV_XSCOM_LPC_BASE);
1761
1762 /*
1763 * Interrupt Management Area. This is the memory region holding
1764 * all the Interrupt Control Presenter (ICP) registers
1765 */
1766 pnv_chip_icp_realize(chip8, &local_err);
1767 if (local_err) {
1768 error_propagate(errp, local_err);
1769 return;
1770 }
1771
1772 /* HOMER (must be created before OCC) */
1773 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1774 &error_abort);
1775 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1776 return;
1777 }
1778 /* Homer Xscom region */
1779 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1780 /* Homer RAM region */
1781 memory_region_add_subregion(get_system_memory(), chip8->homer.base,
1782 &chip8->homer.mem);
1783
1784 /* Create the simplified OCC model */
1785 object_property_set_link(OBJECT(&chip8->occ), "homer",
1786 OBJECT(&chip8->homer), &error_abort);
1787 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1788 return;
1789 }
1790 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1791 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1792 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC));
1793
1794 /* OCC SRAM model */
1795 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1796 &chip8->occ.sram_regs);
1797
1798 /* PHB controllers */
1799 for (i = 0; i < chip8->num_phbs; i++) {
1800 PnvPHB *phb = chip8->phbs[i];
1801
1802 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1803 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1804 &error_fatal);
1805 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1806 &error_fatal);
1807 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1808 return;
1809 }
1810 }
1811 }
1812
1813 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1814 {
1815 addr &= (PNV_XSCOM_SIZE - 1);
1816 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1817 }
1818
1819 static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data)
1820 {
1821 DeviceClass *dc = DEVICE_CLASS(klass);
1822 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1823
1824 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1825 k->cores_mask = POWER8_CORE_MASK;
1826 k->num_phbs = 3;
1827 k->get_pir_tir = pnv_get_pir_tir_p8;
1828 k->intc_create = pnv_chip_power8_intc_create;
1829 k->intc_reset = pnv_chip_power8_intc_reset;
1830 k->intc_destroy = pnv_chip_power8_intc_destroy;
1831 k->intc_print_info = pnv_chip_power8_intc_print_info;
1832 k->isa_create = pnv_chip_power8_isa_create;
1833 k->dt_populate = pnv_chip_power8_dt_populate;
1834 k->pic_print_info = pnv_chip_power8_pic_print_info;
1835 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1836 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1837 dc->desc = "PowerNV Chip POWER8";
1838
1839 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1840 &k->parent_realize);
1841 }
1842
1843 static void pnv_chip_power9_instance_init(Object *obj)
1844 {
1845 PnvChip *chip = PNV_CHIP(obj);
1846 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1847 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1848 int i;
1849
1850 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU);
1851 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1852 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1853 "xive-fabric");
1854
1855 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1856
1857 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1858
1859 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD);
1860
1861 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1862
1863 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1864
1865 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1866
1867 /* Number of PECs is the chip default */
1868 chip->num_pecs = pcc->num_pecs;
1869
1870 for (i = 0; i < chip->num_pecs; i++) {
1871 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1872 TYPE_PNV_PHB4_PEC);
1873 }
1874
1875 for (i = 0; i < pcc->i2c_num_engines; i++) {
1876 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C);
1877 }
1878 }
1879
1880 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1881 PnvCore *pnv_core,
1882 const char *type)
1883 {
1884 char eq_name[32];
1885 int core_id = CPU_CORE(pnv_core)->core_id;
1886
1887 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1888 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1889 sizeof(*eq), type,
1890 &error_fatal, NULL);
1891
1892 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1893 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1894 }
1895
1896 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1897 {
1898 PnvChip *chip = PNV_CHIP(chip9);
1899 int i;
1900
1901 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1902 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1903
1904 for (i = 0; i < chip9->nr_quads; i++) {
1905 PnvQuad *eq = &chip9->quads[i];
1906
1907 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1908 PNV_QUAD_TYPE_NAME("power9"));
1909
1910 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1911 &eq->xscom_regs);
1912 }
1913 }
1914
1915 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1916 {
1917 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1918 int i;
1919
1920 for (i = 0; i < chip->num_pecs; i++) {
1921 PnvPhb4PecState *pec = &chip9->pecs[i];
1922 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1923 uint32_t pec_cplt_base;
1924 uint32_t pec_nest_base;
1925 uint32_t pec_pci_base;
1926
1927 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1928 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1929 &error_fatal);
1930 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1931 &error_fatal);
1932 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1933 return;
1934 }
1935
1936 pec_cplt_base = pecc->xscom_cplt_base(pec);
1937 pec_nest_base = pecc->xscom_nest_base(pec);
1938 pec_pci_base = pecc->xscom_pci_base(pec);
1939
1940 pnv_xscom_add_subregion(chip, pec_cplt_base,
1941 &pec->nest_pervasive.xscom_ctrl_regs_mr);
1942 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1943 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1944 }
1945 }
1946
1947 static uint64_t pnv_handle_sprd_load(CPUPPCState *env)
1948 {
1949 PowerPCCPU *cpu = env_archcpu(env);
1950 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
1951 uint64_t sprc = env->spr[SPR_POWER_SPRC];
1952
1953 if (pc->big_core) {
1954 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
1955 }
1956
1957 switch (sprc & 0x3e0) {
1958 case 0: /* SCRATCH0-3 */
1959 case 1: /* SCRATCH4-7 */
1960 return pc->scratch[(sprc >> 3) & 0x7];
1961
1962 case 0x1e0: /* core thread state */
1963 if (env->excp_model == POWERPC_EXCP_POWER9) {
1964 /*
1965 * Only implement for POWER9 because skiboot uses it to check
1966 * big-core mode. Other bits are unimplemented so we would
1967 * prefer to get unimplemented message on POWER10 if it were
1968 * used anywhere.
1969 */
1970 if (pc->big_core) {
1971 return PPC_BIT(63);
1972 } else {
1973 return 0;
1974 }
1975 }
1976 /* fallthru */
1977
1978 default:
1979 qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x"
1980 TARGET_FMT_lx"\n", sprc);
1981 break;
1982 }
1983 return 0;
1984 }
1985
1986 static void pnv_handle_sprd_store(CPUPPCState *env, uint64_t val)
1987 {
1988 PowerPCCPU *cpu = env_archcpu(env);
1989 uint64_t sprc = env->spr[SPR_POWER_SPRC];
1990 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
1991 int nr;
1992
1993 if (pc->big_core) {
1994 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
1995 }
1996
1997 switch (sprc & 0x3e0) {
1998 case 0: /* SCRATCH0-3 */
1999 case 1: /* SCRATCH4-7 */
2000 /*
2001 * Log stores to SCRATCH, because some firmware uses these for
2002 * debugging and logging, but they would normally be read by the BMC,
2003 * which is not implemented in QEMU yet. This gives a way to get at the
2004 * information. Could also dump these upon checkstop.
2005 */
2006 nr = (sprc >> 3) & 0x7;
2007 pc->scratch[nr] = val;
2008 break;
2009 default:
2010 qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x"
2011 TARGET_FMT_lx"\n", sprc);
2012 break;
2013 }
2014 }
2015
2016 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
2017 {
2018 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2019 Pnv9Chip *chip9 = PNV9_CHIP(dev);
2020 PnvChip *chip = PNV_CHIP(dev);
2021 Pnv9Psi *psi9 = &chip9->psi;
2022 PowerPCCPU *cpu;
2023 PowerPCCPUClass *cpu_class;
2024 Error *local_err = NULL;
2025 int i;
2026
2027 /* XSCOM bridge is first */
2028 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
2029
2030 pcc->parent_realize(dev, &local_err);
2031 if (local_err) {
2032 error_propagate(errp, local_err);
2033 return;
2034 }
2035
2036 /* ADU */
2037 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc),
2038 &error_abort);
2039 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) {
2040 return;
2041 }
2042 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE,
2043 &chip9->adu.xscom_regs);
2044
2045 pnv_chip_quad_realize(chip9, &local_err);
2046 if (local_err) {
2047 error_propagate(errp, local_err);
2048 return;
2049 }
2050
2051 /* Set handlers for Special registers, such as SPRD */
2052 cpu = chip->cores[0]->threads[0];
2053 cpu_class = POWERPC_CPU_GET_CLASS(cpu);
2054 cpu_class->load_sprd = pnv_handle_sprd_load;
2055 cpu_class->store_sprd = pnv_handle_sprd_store;
2056
2057 /* XIVE interrupt controller (POWER9) */
2058 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
2059 PNV9_XIVE_IC_BASE(chip), &error_fatal);
2060 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
2061 PNV9_XIVE_VC_BASE(chip), &error_fatal);
2062 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
2063 PNV9_XIVE_PC_BASE(chip), &error_fatal);
2064 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
2065 PNV9_XIVE_TM_BASE(chip), &error_fatal);
2066 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
2067 &error_abort);
2068 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
2069 return;
2070 }
2071 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
2072 &chip9->xive.xscom_regs);
2073
2074 /* Processor Service Interface (PSI) Host Bridge */
2075 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip),
2076 &error_fatal);
2077 /* This is the only device with 4k ESB pages */
2078 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K,
2079 &error_fatal);
2080 if (!qdev_realize(DEVICE(psi9), NULL, errp)) {
2081 return;
2082 }
2083 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
2084 &PNV_PSI(psi9)->xscom_regs);
2085
2086 /* LPC */
2087 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
2088 return;
2089 }
2090 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
2091 &chip9->lpc.xscom_regs);
2092
2093 chip->fw_mr = &chip9->lpc.isa_fw;
2094 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
2095 (uint64_t) PNV9_LPCM_BASE(chip));
2096
2097 /* ChipTOD */
2098 object_property_set_bool(OBJECT(&chip9->chiptod), "primary",
2099 chip->chip_id == 0, &error_abort);
2100 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary",
2101 chip->chip_id == 1, &error_abort);
2102 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip),
2103 &error_abort);
2104 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) {
2105 return;
2106 }
2107 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE,
2108 &chip9->chiptod.xscom_regs);
2109
2110 /* SBE */
2111 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
2112 return;
2113 }
2114 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
2115 &chip9->sbe.xscom_ctrl_regs);
2116 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
2117 &chip9->sbe.xscom_mbox_regs);
2118 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
2119 DEVICE(psi9), PSIHB9_IRQ_PSU));
2120
2121 /* HOMER (must be created before OCC) */
2122 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
2123 &error_abort);
2124 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
2125 return;
2126 }
2127 /* Homer Xscom region */
2128 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
2129 /* Homer RAM region */
2130 memory_region_add_subregion(get_system_memory(), chip9->homer.base,
2131 &chip9->homer.mem);
2132
2133 /* Create the simplified OCC model */
2134 object_property_set_link(OBJECT(&chip9->occ), "homer",
2135 OBJECT(&chip9->homer), &error_abort);
2136 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
2137 return;
2138 }
2139 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
2140 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
2141 DEVICE(psi9), PSIHB9_IRQ_OCC));
2142
2143 /* OCC SRAM model */
2144 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
2145 &chip9->occ.sram_regs);
2146
2147 /* PEC PHBs */
2148 pnv_chip_power9_pec_realize(chip, &local_err);
2149 if (local_err) {
2150 error_propagate(errp, local_err);
2151 return;
2152 }
2153
2154 /*
2155 * I2C
2156 */
2157 for (i = 0; i < pcc->i2c_num_engines; i++) {
2158 Object *obj = OBJECT(&chip9->i2c[i]);
2159
2160 object_property_set_int(obj, "engine", i + 1, &error_fatal);
2161 object_property_set_int(obj, "num-busses",
2162 pcc->i2c_ports_per_engine[i],
2163 &error_fatal);
2164 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
2165 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
2166 return;
2167 }
2168 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
2169 (chip9->i2c[i].engine - 1) *
2170 PNV9_XSCOM_I2CM_SIZE,
2171 &chip9->i2c[i].xscom_regs);
2172 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
2173 qdev_get_gpio_in(DEVICE(psi9),
2174 PSIHB9_IRQ_SBE_I2C));
2175 }
2176 }
2177
2178 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
2179 {
2180 addr &= (PNV9_XSCOM_SIZE - 1);
2181 return addr >> 3;
2182 }
2183
2184 static void pnv_chip_power9_class_init(ObjectClass *klass, const void *data)
2185 {
2186 DeviceClass *dc = DEVICE_CLASS(klass);
2187 PnvChipClass *k = PNV_CHIP_CLASS(klass);
2188 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
2189
2190 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
2191 k->cores_mask = POWER9_CORE_MASK;
2192 k->get_pir_tir = pnv_get_pir_tir_p9;
2193 k->intc_create = pnv_chip_power9_intc_create;
2194 k->intc_reset = pnv_chip_power9_intc_reset;
2195 k->intc_destroy = pnv_chip_power9_intc_destroy;
2196 k->intc_print_info = pnv_chip_power9_intc_print_info;
2197 k->isa_create = pnv_chip_power9_isa_create;
2198 k->dt_populate = pnv_chip_power9_dt_populate;
2199 k->pic_print_info = pnv_chip_power9_pic_print_info;
2200 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
2201 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
2202 dc->desc = "PowerNV Chip POWER9";
2203 k->num_pecs = PNV9_CHIP_MAX_PEC;
2204 k->i2c_num_engines = PNV9_CHIP_MAX_I2C;
2205 k->i2c_ports_per_engine = i2c_ports_per_engine;
2206
2207 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
2208 &k->parent_realize);
2209 }
2210
2211 static void pnv_chip_power10_instance_init(Object *obj)
2212 {
2213 PnvChip *chip = PNV_CHIP(obj);
2214 Pnv10Chip *chip10 = PNV10_CHIP(obj);
2215 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
2216 int i;
2217
2218 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU);
2219 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
2220 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
2221 "xive-fabric");
2222 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
2223 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
2224 object_initialize_child(obj, "chiptod", &chip10->chiptod,
2225 TYPE_PNV10_CHIPTOD);
2226 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
2227 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
2228 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
2229 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet,
2230 TYPE_PNV_N1_CHIPLET);
2231
2232 chip->num_pecs = pcc->num_pecs;
2233
2234 for (i = 0; i < chip->num_pecs; i++) {
2235 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
2236 TYPE_PNV_PHB5_PEC);
2237 }
2238
2239 for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {
2240 object_initialize_child(obj, "nmmu[*]", &chip10->nmmu[i],
2241 TYPE_PNV_NMMU);
2242 }
2243
2244 for (i = 0; i < pcc->i2c_num_engines; i++) {
2245 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
2246 }
2247
2248 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
2249 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i],
2250 TYPE_PNV_SPI);
2251 }
2252 }
2253
2254 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
2255 {
2256 PnvChip *chip = PNV_CHIP(chip10);
2257 int i;
2258
2259 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
2260 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
2261
2262 for (i = 0; i < chip10->nr_quads; i++) {
2263 PnvQuad *eq = &chip10->quads[i];
2264
2265 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
2266 PNV_QUAD_TYPE_NAME("power10"));
2267
2268 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
2269 &eq->xscom_regs);
2270
2271 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
2272 &eq->xscom_qme_regs);
2273 }
2274 }
2275
2276 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
2277 {
2278 Pnv10Chip *chip10 = PNV10_CHIP(chip);
2279 int i;
2280
2281 for (i = 0; i < chip->num_pecs; i++) {
2282 PnvPhb4PecState *pec = &chip10->pecs[i];
2283 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
2284 uint32_t pec_cplt_base;
2285 uint32_t pec_nest_base;
2286 uint32_t pec_pci_base;
2287
2288 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
2289 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
2290 &error_fatal);
2291 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
2292 &error_fatal);
2293 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
2294 return;
2295 }
2296
2297 pec_cplt_base = pecc->xscom_cplt_base(pec);
2298 pec_nest_base = pecc->xscom_nest_base(pec);
2299 pec_pci_base = pecc->xscom_pci_base(pec);
2300
2301 pnv_xscom_add_subregion(chip, pec_cplt_base,
2302 &pec->nest_pervasive.xscom_ctrl_regs_mr);
2303 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
2304 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
2305 }
2306 }
2307
2308 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
2309 {
2310 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2311 PnvChip *chip = PNV_CHIP(dev);
2312 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2313 PowerPCCPU *cpu;
2314 PowerPCCPUClass *cpu_class;
2315 Error *local_err = NULL;
2316 int i;
2317
2318 /* XSCOM bridge is first */
2319 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip));
2320
2321 pcc->parent_realize(dev, &local_err);
2322 if (local_err) {
2323 error_propagate(errp, local_err);
2324 return;
2325 }
2326
2327 /* ADU */
2328 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc),
2329 &error_abort);
2330 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) {
2331 return;
2332 }
2333 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE,
2334 &chip10->adu.xscom_regs);
2335
2336 pnv_chip_power10_quad_realize(chip10, &local_err);
2337 if (local_err) {
2338 error_propagate(errp, local_err);
2339 return;
2340 }
2341
2342 /* Set handlers for Special registers, such as SPRD */
2343 cpu = chip->cores[0]->threads[0];
2344 cpu_class = POWERPC_CPU_GET_CLASS(cpu);
2345 cpu_class->load_sprd = pnv_handle_sprd_load;
2346 cpu_class->store_sprd = pnv_handle_sprd_store;
2347
2348 /* XIVE2 interrupt controller (POWER10) */
2349 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
2350 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
2351 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
2352 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
2353 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
2354 PNV10_XIVE2_END_BASE(chip), &error_fatal);
2355 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
2356 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
2357 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
2358 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
2359 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
2360 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
2361 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
2362 &error_abort);
2363 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
2364 return;
2365 }
2366 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
2367 &chip10->xive.xscom_regs);
2368
2369 /* Processor Service Interface (PSI) Host Bridge */
2370 object_property_set_int(OBJECT(&chip10->psi), "bar",
2371 PNV10_PSIHB_BASE(chip), &error_fatal);
2372 /* PSI can now be configured to use 64k ESB pages on POWER10 */
2373 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
2374 &error_fatal);
2375 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
2376 return;
2377 }
2378 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
2379 &PNV_PSI(&chip10->psi)->xscom_regs);
2380
2381 /* LPC */
2382 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
2383 return;
2384 }
2385 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
2386 &chip10->lpc.xscom_regs);
2387
2388 chip->fw_mr = &chip10->lpc.isa_fw;
2389 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
2390 (uint64_t) PNV10_LPCM_BASE(chip));
2391
2392 /* ChipTOD */
2393 object_property_set_bool(OBJECT(&chip10->chiptod), "primary",
2394 chip->chip_id == 0, &error_abort);
2395 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary",
2396 chip->chip_id == 1, &error_abort);
2397 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip),
2398 &error_abort);
2399 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) {
2400 return;
2401 }
2402 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE,
2403 &chip10->chiptod.xscom_regs);
2404
2405 /* HOMER (must be created before OCC) */
2406 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
2407 &error_abort);
2408 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
2409 return;
2410 }
2411 /* Homer Xscom region */
2412 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
2413 &chip10->homer.pba_regs);
2414 /* Homer RAM region */
2415 memory_region_add_subregion(get_system_memory(), chip10->homer.base,
2416 &chip10->homer.mem);
2417
2418 /* Create the simplified OCC model */
2419 object_property_set_link(OBJECT(&chip10->occ), "homer",
2420 OBJECT(&chip10->homer), &error_abort);
2421 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
2422 return;
2423 }
2424 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
2425 &chip10->occ.xscom_regs);
2426 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
2427 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
2428
2429 /* OCC SRAM model */
2430 memory_region_add_subregion(get_system_memory(),
2431 PNV10_OCC_SENSOR_BASE(chip),
2432 &chip10->occ.sram_regs);
2433
2434 /* SBE */
2435 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
2436 return;
2437 }
2438 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
2439 &chip10->sbe.xscom_ctrl_regs);
2440 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
2441 &chip10->sbe.xscom_mbox_regs);
2442 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
2443 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
2444
2445 /* N1 chiplet */
2446 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
2447 return;
2448 }
2449 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
2450 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
2451
2452 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
2453 &chip10->n1_chiplet.xscom_pb_eq_mr);
2454
2455 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
2456 &chip10->n1_chiplet.xscom_pb_es_mr);
2457
2458 /* nest0/1 MMU */
2459 for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {
2460 object_property_set_int(OBJECT(&chip10->nmmu[i]), "nmmu_id",
2461 i , &error_fatal);
2462 object_property_set_link(OBJECT(&chip10->nmmu[i]), "chip",
2463 OBJECT(chip), &error_abort);
2464 if (!qdev_realize(DEVICE(&chip10->nmmu[i]), NULL, errp)) {
2465 return;
2466 }
2467 }
2468 pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST0_MMU_BASE,
2469 &chip10->nmmu[0].xscom_regs);
2470 pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_MMU_BASE,
2471 &chip10->nmmu[1].xscom_regs);
2472
2473 /* PHBs */
2474 pnv_chip_power10_phb_realize(chip, &local_err);
2475 if (local_err) {
2476 error_propagate(errp, local_err);
2477 return;
2478 }
2479
2480
2481 /*
2482 * I2C
2483 */
2484 for (i = 0; i < pcc->i2c_num_engines; i++) {
2485 Object *obj = OBJECT(&chip10->i2c[i]);
2486
2487 object_property_set_int(obj, "engine", i + 1, &error_fatal);
2488 object_property_set_int(obj, "num-busses",
2489 pcc->i2c_ports_per_engine[i],
2490 &error_fatal);
2491 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
2492 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
2493 return;
2494 }
2495 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE +
2496 (chip10->i2c[i].engine - 1) *
2497 PNV10_XSCOM_I2CM_SIZE,
2498 &chip10->i2c[i].xscom_regs);
2499 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0,
2500 qdev_get_gpio_in(DEVICE(&chip10->psi),
2501 PSIHB9_IRQ_SBE_I2C));
2502 }
2503 /* PIB SPI Controller */
2504 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
2505 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num",
2506 i, &error_fatal);
2507 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
2508 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len",
2509 (i == 2) ? 1 : 4, &error_fatal);
2510 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id",
2511 chip->chip_id, &error_fatal);
2512 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
2513 (&chip10->pib_spic[i])), errp)) {
2514 return;
2515 }
2516 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE +
2517 i * PNV10_XSCOM_PIB_SPIC_SIZE,
2518 &chip10->pib_spic[i].xscom_spic_regs);
2519 }
2520 }
2521
2522 static void pnv_chip_power11_instance_init(Object *obj)
2523 {
2524 PnvChip *chip = PNV_CHIP(obj);
2525 Pnv11Chip *chip11 = PNV11_CHIP(obj);
2526 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
2527 int i;
2528
2529 object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU);
2530
2531 /*
2532 * Use Power10 device models for PSI/LPC/OCC/SBE/HOMER as corresponding
2533 * device models for Power11 are same
2534 */
2535 object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV10_PSI);
2536 object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV10_LPC);
2537 object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC);
2538 object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE);
2539 object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER);
2540
2541 object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
2542 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
2543 "xive-fabric");
2544 object_initialize_child(obj, "chiptod", &chip11->chiptod,
2545 TYPE_PNV11_CHIPTOD);
2546 object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
2547 TYPE_PNV_N1_CHIPLET);
2548
2549 chip->num_pecs = pcc->num_pecs;
2550
2551 for (i = 0; i < chip->num_pecs; i++) {
2552 object_initialize_child(obj, "pec[*]", &chip11->pecs[i],
2553 TYPE_PNV_PHB5_PEC);
2554 }
2555
2556 for (i = 0; i < pcc->i2c_num_engines; i++) {
2557 object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C);
2558 }
2559
2560 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
2561 object_initialize_child(obj, "pib_spic[*]", &chip11->pib_spic[i],
2562 TYPE_PNV_SPI);
2563 }
2564 }
2565
2566 static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp)
2567 {
2568 PnvChip *chip = PNV_CHIP(chip11);
2569 int i;
2570
2571 chip11->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
2572 chip11->quads = g_new0(PnvQuad, chip11->nr_quads);
2573
2574 for (i = 0; i < chip11->nr_quads; i++) {
2575 PnvQuad *eq = &chip11->quads[i];
2576
2577 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
2578 PNV_QUAD_TYPE_NAME("power11"));
2579
2580 pnv_xscom_add_subregion(chip, PNV11_XSCOM_EQ_BASE(eq->quad_id),
2581 &eq->xscom_regs);
2582
2583 pnv_xscom_add_subregion(chip, PNV11_XSCOM_QME_BASE(eq->quad_id),
2584 &eq->xscom_qme_regs);
2585 }
2586 }
2587
2588 static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp)
2589 {
2590 Pnv11Chip *chip11 = PNV11_CHIP(chip);
2591 int i;
2592
2593 for (i = 0; i < chip->num_pecs; i++) {
2594 PnvPhb4PecState *pec = &chip11->pecs[i];
2595 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
2596 uint32_t pec_cplt_base;
2597 uint32_t pec_nest_base;
2598 uint32_t pec_pci_base;
2599
2600 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
2601 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
2602 &error_fatal);
2603 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
2604 &error_fatal);
2605 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
2606 return;
2607 }
2608
2609 pec_cplt_base = pecc->xscom_cplt_base(pec);
2610 pec_nest_base = pecc->xscom_nest_base(pec);
2611 pec_pci_base = pecc->xscom_pci_base(pec);
2612
2613 pnv_xscom_add_subregion(chip, pec_cplt_base,
2614 &pec->nest_pervasive.xscom_ctrl_regs_mr);
2615 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
2616 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
2617 }
2618 }
2619
2620 static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
2621 {
2622 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2623 PnvChip *chip = PNV_CHIP(dev);
2624 Pnv11Chip *chip11 = PNV11_CHIP(dev);
2625 PowerPCCPU *cpu;
2626 PowerPCCPUClass *cpu_class;
2627 Error *local_err = NULL;
2628 int i;
2629
2630 /* XSCOM bridge is first */
2631 pnv_xscom_init(chip, PNV11_XSCOM_SIZE, PNV11_XSCOM_BASE(chip));
2632
2633 pcc->parent_realize(dev, &local_err);
2634 if (local_err) {
2635 error_propagate(errp, local_err);
2636 return;
2637 }
2638
2639 /* Set handlers for Special registers, such as SPRD */
2640 cpu = chip->cores[0]->threads[0];
2641 cpu_class = POWERPC_CPU_GET_CLASS(cpu);
2642 cpu_class->load_sprd = pnv_handle_sprd_load;
2643 cpu_class->store_sprd = pnv_handle_sprd_store;
2644
2645 /* ADU */
2646 object_property_set_link(OBJECT(&chip11->adu), "lpc", OBJECT(&chip11->lpc),
2647 &error_abort);
2648 if (!qdev_realize(DEVICE(&chip11->adu), NULL, errp)) {
2649 return;
2650 }
2651 pnv_xscom_add_subregion(chip, PNV11_XSCOM_ADU_BASE,
2652 &chip11->adu.xscom_regs);
2653
2654 pnv_chip_power11_quad_realize(chip11, &local_err);
2655 if (local_err) {
2656 error_propagate(errp, local_err);
2657 return;
2658 }
2659
2660 /* XIVE2 interrupt controller */
2661 object_property_set_int(OBJECT(&chip11->xive), "ic-bar",
2662 PNV11_XIVE2_IC_BASE(chip), &error_fatal);
2663 object_property_set_int(OBJECT(&chip11->xive), "esb-bar",
2664 PNV11_XIVE2_ESB_BASE(chip), &error_fatal);
2665 object_property_set_int(OBJECT(&chip11->xive), "end-bar",
2666 PNV11_XIVE2_END_BASE(chip), &error_fatal);
2667 object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar",
2668 PNV11_XIVE2_NVPG_BASE(chip), &error_fatal);
2669 object_property_set_int(OBJECT(&chip11->xive), "nvc-bar",
2670 PNV11_XIVE2_NVC_BASE(chip), &error_fatal);
2671 object_property_set_int(OBJECT(&chip11->xive), "tm-bar",
2672 PNV11_XIVE2_TM_BASE(chip), &error_fatal);
2673 object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip),
2674 &error_abort);
2675 if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) {
2676 return;
2677 }
2678 pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE,
2679 &chip11->xive.xscom_regs);
2680
2681 /* Processor Service Interface (PSI) Host Bridge */
2682 object_property_set_int(OBJECT(&chip11->psi), "bar",
2683 PNV11_PSIHB_BASE(chip), &error_fatal);
2684 /* PSI can be configured to use 64k ESB pages on Power11 */
2685 object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K,
2686 &error_fatal);
2687 if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) {
2688 return;
2689 }
2690 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PSIHB_BASE,
2691 &PNV_PSI(&chip11->psi)->xscom_regs);
2692
2693 /* LPC */
2694 if (!qdev_realize(DEVICE(&chip11->lpc), NULL, errp)) {
2695 return;
2696 }
2697 memory_region_add_subregion(get_system_memory(), PNV11_LPCM_BASE(chip),
2698 &chip11->lpc.xscom_regs);
2699
2700 chip->fw_mr = &chip11->lpc.isa_fw;
2701 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
2702 (uint64_t) PNV11_LPCM_BASE(chip));
2703
2704 /* ChipTOD */
2705 object_property_set_bool(OBJECT(&chip11->chiptod), "primary",
2706 chip->chip_id == 0, &error_abort);
2707 object_property_set_bool(OBJECT(&chip11->chiptod), "secondary",
2708 chip->chip_id == 1, &error_abort);
2709 object_property_set_link(OBJECT(&chip11->chiptod), "chip", OBJECT(chip),
2710 &error_abort);
2711 if (!qdev_realize(DEVICE(&chip11->chiptod), NULL, errp)) {
2712 return;
2713 }
2714 pnv_xscom_add_subregion(chip, PNV11_XSCOM_CHIPTOD_BASE,
2715 &chip11->chiptod.xscom_regs);
2716
2717 /* HOMER (must be created before OCC) */
2718 object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip),
2719 &error_abort);
2720 if (!qdev_realize(DEVICE(&chip11->homer), NULL, errp)) {
2721 return;
2722 }
2723 /* Homer Xscom region */
2724 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PBA_BASE,
2725 &chip11->homer.pba_regs);
2726 /* Homer RAM region */
2727 memory_region_add_subregion(get_system_memory(), chip11->homer.base,
2728 &chip11->homer.mem);
2729
2730 /* Create the simplified OCC model */
2731 object_property_set_link(OBJECT(&chip11->occ), "homer",
2732 OBJECT(&chip11->homer), &error_abort);
2733 if (!qdev_realize(DEVICE(&chip11->occ), NULL, errp)) {
2734 return;
2735 }
2736 pnv_xscom_add_subregion(chip, PNV11_XSCOM_OCC_BASE,
2737 &chip11->occ.xscom_regs);
2738 qdev_connect_gpio_out(DEVICE(&chip11->occ), 0, qdev_get_gpio_in(
2739 DEVICE(&chip11->psi), PSIHB9_IRQ_OCC));
2740
2741 /* OCC SRAM model */
2742 memory_region_add_subregion(get_system_memory(),
2743 PNV11_OCC_SENSOR_BASE(chip),
2744 &chip11->occ.sram_regs);
2745
2746 /* SBE */
2747 if (!qdev_realize(DEVICE(&chip11->sbe), NULL, errp)) {
2748 return;
2749 }
2750 pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_CTRL_BASE,
2751 &chip11->sbe.xscom_ctrl_regs);
2752 pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_MBOX_BASE,
2753 &chip11->sbe.xscom_mbox_regs);
2754 qdev_connect_gpio_out(DEVICE(&chip11->sbe), 0, qdev_get_gpio_in(
2755 DEVICE(&chip11->psi), PSIHB9_IRQ_PSU));
2756
2757 /* N1 chiplet */
2758 if (!qdev_realize(DEVICE(&chip11->n1_chiplet), NULL, errp)) {
2759 return;
2760 }
2761 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
2762 &chip11->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
2763
2764 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_EQ_BASE,
2765 &chip11->n1_chiplet.xscom_pb_eq_mr);
2766
2767 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
2768 &chip11->n1_chiplet.xscom_pb_es_mr);
2769
2770 /* PHBs */
2771 pnv_chip_power11_phb_realize(chip, &local_err);
2772 if (local_err) {
2773 error_propagate(errp, local_err);
2774 return;
2775 }
2776
2777 /*
2778 * I2C
2779 */
2780 for (i = 0; i < pcc->i2c_num_engines; i++) {
2781 Object *obj = OBJECT(&chip11->i2c[i]);
2782
2783 object_property_set_int(obj, "engine", i + 1, &error_fatal);
2784 object_property_set_int(obj, "num-busses",
2785 pcc->i2c_ports_per_engine[i],
2786 &error_fatal);
2787 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
2788 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
2789 return;
2790 }
2791 pnv_xscom_add_subregion(chip, PNV11_XSCOM_I2CM_BASE +
2792 (chip11->i2c[i].engine - 1) *
2793 PNV11_XSCOM_I2CM_SIZE,
2794 &chip11->i2c[i].xscom_regs);
2795 qdev_connect_gpio_out(DEVICE(&chip11->i2c[i]), 0,
2796 qdev_get_gpio_in(DEVICE(&chip11->psi),
2797 PSIHB9_IRQ_SBE_I2C));
2798 }
2799 /* PIB SPI Controller */
2800 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
2801 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "spic_num",
2802 i, &error_fatal);
2803 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
2804 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "transfer_len",
2805 (i == 2) ? 1 : 4, &error_fatal);
2806 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "chip-id",
2807 chip->chip_id, &error_fatal);
2808 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
2809 (&chip11->pib_spic[i])), errp)) {
2810 return;
2811 }
2812 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PIB_SPIC_BASE +
2813 i * PNV11_XSCOM_PIB_SPIC_SIZE,
2814 &chip11->pib_spic[i].xscom_spic_regs);
2815 }
2816 }
2817
2818 static void pnv_rainier_i2c_init(PnvMachineState *pnv)
2819 {
2820 int i;
2821 for (i = 0; i < pnv->num_chips; i++) {
2822 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2823
2824 /*
2825 * Add a PCA9552 I2C device for PCIe hotplug control
2826 * to engine 2, bus 1, address 0x63
2827 */
2828 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1],
2829 "pca9552", 0x63);
2830
2831 /*
2832 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9
2833 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots
2834 * after hypervisor code sets a SLOTx_EN pin high.
2835 */
2836 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5));
2837 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6));
2838 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7));
2839 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8));
2840 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9));
2841
2842 /*
2843 * Add a PCA9554 I2C device for cable card presence detection
2844 * to engine 2, bus 1, address 0x25
2845 */
2846 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25);
2847 }
2848 }
2849
2850 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
2851 {
2852 addr &= (PNV10_XSCOM_SIZE - 1);
2853 return addr >> 3;
2854 }
2855
2856 static void pnv_chip_power10_class_init(ObjectClass *klass, const void *data)
2857 {
2858 DeviceClass *dc = DEVICE_CLASS(klass);
2859 PnvChipClass *k = PNV_CHIP_CLASS(klass);
2860 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
2861
2862 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */
2863 k->cores_mask = POWER10_CORE_MASK;
2864 k->get_pir_tir = pnv_get_pir_tir_p10;
2865 k->intc_create = pnv_chip_power10_intc_create;
2866 k->intc_reset = pnv_chip_power10_intc_reset;
2867 k->intc_destroy = pnv_chip_power10_intc_destroy;
2868 k->intc_print_info = pnv_chip_power10_intc_print_info;
2869 k->intc_get = pnv_chip_power10_intc_get;
2870 k->isa_create = pnv_chip_power10_isa_create;
2871 k->dt_populate = pnv_chip_power10_dt_populate;
2872 k->pic_print_info = pnv_chip_power10_pic_print_info;
2873 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
2874 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2875 dc->desc = "PowerNV Chip POWER10";
2876 k->num_pecs = PNV10_CHIP_MAX_PEC;
2877 k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
2878 k->i2c_ports_per_engine = i2c_ports_per_engine;
2879
2880 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
2881 &k->parent_realize);
2882 }
2883
2884 static uint32_t pnv_chip_power11_xscom_pcba(PnvChip *chip, uint64_t addr)
2885 {
2886 addr &= (PNV11_XSCOM_SIZE - 1);
2887 return addr >> 3;
2888 }
2889
2890 static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
2891 {
2892 DeviceClass *dc = DEVICE_CLASS(klass);
2893 PnvChipClass *k = PNV_CHIP_CLASS(klass);
2894 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
2895
2896 k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
2897 k->cores_mask = POWER11_CORE_MASK;
2898 k->get_pir_tir = pnv_get_pir_tir_p10;
2899 k->intc_create = pnv_chip_power11_intc_create;
2900 k->intc_reset = pnv_chip_power11_intc_reset;
2901 k->intc_destroy = pnv_chip_power11_intc_destroy;
2902 k->intc_print_info = pnv_chip_power11_intc_print_info;
2903 k->intc_get = pnv_chip_power11_intc_get;
2904 k->isa_create = pnv_chip_power11_isa_create;
2905 k->dt_populate = pnv_chip_power11_dt_populate;
2906 k->pic_print_info = pnv_chip_power11_pic_print_info;
2907 k->xscom_core_base = pnv_chip_power11_xscom_core_base;
2908 k->xscom_pcba = pnv_chip_power11_xscom_pcba;
2909 dc->desc = "PowerNV Chip Power11";
2910 k->num_pecs = PNV10_CHIP_MAX_PEC;
2911 k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
2912 k->i2c_ports_per_engine = i2c_ports_per_engine;
2913
2914 device_class_set_parent_realize(dc, pnv_chip_power11_realize,
2915 &k->parent_realize);
2916 }
2917
2918 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip,
2919 Error **errp)
2920 {
2921 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2922 int cores_max;
2923
2924 /*
2925 * No custom mask for this chip, let's use the default one from *
2926 * the chip class
2927 */
2928 if (!chip->cores_mask) {
2929 chip->cores_mask = pcc->cores_mask;
2930 }
2931
2932 /* filter alien core ids ! some are reserved */
2933 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
2934 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
2935 chip->cores_mask);
2936 return;
2937 }
2938 chip->cores_mask &= pcc->cores_mask;
2939
2940 /* Ensure small-cores a paired up in big-core mode */
2941 if (pnv->big_core) {
2942 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL;
2943 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL;
2944
2945 if (even_cores ^ (odd_cores >> 1)) {
2946 error_setg(errp, "warning: unpaired cores in big-core mode !");
2947 return;
2948 }
2949 }
2950
2951 /* now that we have a sane layout, let check the number of cores */
2952 cores_max = ctpop64(chip->cores_mask);
2953 if (chip->nr_cores > cores_max) {
2954 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
2955 cores_max);
2956 return;
2957 }
2958 }
2959
2960 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
2961 {
2962 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
2963 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv);
2964 Error *error = NULL;
2965 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2966 const char *typename = pnv_chip_core_typename(chip);
2967 int i, core_hwid;
2968
2969 if (!object_class_by_name(typename)) {
2970 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
2971 return;
2972 }
2973
2974 /* Cores */
2975 pnv_chip_core_sanitize(pnv, chip, &error);
2976 if (error) {
2977 error_propagate(errp, error);
2978 return;
2979 }
2980
2981 chip->cores = g_new0(PnvCore *, chip->nr_cores);
2982
2983 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
2984 && (i < chip->nr_cores); core_hwid++) {
2985 char core_name[32];
2986 PnvCore *pnv_core;
2987 uint64_t xscom_core_base;
2988
2989 if (!(chip->cores_mask & (1ull << core_hwid))) {
2990 continue;
2991 }
2992
2993 pnv_core = PNV_CORE(object_new(typename));
2994
2995 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
2996 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
2997 chip->cores[i] = pnv_core;
2998 object_property_set_int(OBJECT(pnv_core), "nr-threads",
2999 chip->nr_threads, &error_fatal);
3000 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
3001 core_hwid, &error_fatal);
3002 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
3003 &error_fatal);
3004 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
3005 &error_fatal);
3006 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core,
3007 &error_fatal);
3008 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core",
3009 pmc->quirk_tb_big_core, &error_fatal);
3010 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core",
3011 chip->lpar_per_core, &error_fatal);
3012 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
3013 &error_abort);
3014
3015 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
3016
3017 /* Each core has an XSCOM MMIO region */
3018 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
3019
3020 pnv_xscom_add_subregion(chip, xscom_core_base,
3021 &pnv_core->xscom_regs);
3022 i++;
3023 }
3024 }
3025
3026 static void pnv_chip_realize(DeviceState *dev, Error **errp)
3027 {
3028 PnvChip *chip = PNV_CHIP(dev);
3029 Error *error = NULL;
3030
3031 /* Cores */
3032 pnv_chip_core_realize(chip, &error);
3033 if (error) {
3034 error_propagate(errp, error);
3035 return;
3036 }
3037 }
3038
3039 static const Property pnv_chip_properties[] = {
3040 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
3041 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
3042 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
3043 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
3044 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
3045 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
3046 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
3047 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
3048 };
3049
3050 static void pnv_chip_class_init(ObjectClass *klass, const void *data)
3051 {
3052 DeviceClass *dc = DEVICE_CLASS(klass);
3053
3054 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
3055 dc->realize = pnv_chip_realize;
3056 device_class_set_props(dc, pnv_chip_properties);
3057 dc->desc = "PowerNV Chip";
3058 }
3059
3060 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id)
3061 {
3062 int i;
3063
3064 for (i = 0; i < chip->nr_cores; i++) {
3065 PnvCore *pc = chip->cores[i];
3066 CPUCore *cc = CPU_CORE(pc);
3067
3068 if (cc->core_id == core_id) {
3069 return pc;
3070 }
3071 }
3072 return NULL;
3073 }
3074
3075 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
3076 {
3077 int i, j;
3078
3079 for (i = 0; i < chip->nr_cores; i++) {
3080 PnvCore *pc = chip->cores[i];
3081 CPUCore *cc = CPU_CORE(pc);
3082
3083 for (j = 0; j < cc->nr_threads; j++) {
3084 if (ppc_cpu_pir(pc->threads[j]) == pir) {
3085 return pc->threads[j];
3086 }
3087 }
3088 }
3089 return NULL;
3090 }
3091
3092 static void pnv_chip_foreach_cpu(PnvChip *chip,
3093 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque),
3094 void *opaque)
3095 {
3096 int i, j;
3097
3098 for (i = 0; i < chip->nr_cores; i++) {
3099 PnvCore *pc = chip->cores[i];
3100
3101 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) {
3102 fn(chip, pc->threads[j], opaque);
3103 }
3104 }
3105 }
3106
3107 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
3108 {
3109 PnvMachineState *pnv = PNV_MACHINE(xi);
3110 int i, j;
3111
3112 for (i = 0; i < pnv->num_chips; i++) {
3113 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
3114
3115 if (ics_valid_irq(&chip8->psi.ics, irq)) {
3116 return &chip8->psi.ics;
3117 }
3118
3119 for (j = 0; j < chip8->num_phbs; j++) {
3120 PnvPHB *phb = chip8->phbs[j];
3121 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
3122
3123 if (ics_valid_irq(&phb3->lsis, irq)) {
3124 return &phb3->lsis;
3125 }
3126
3127 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
3128 return ICS(&phb3->msis);
3129 }
3130 }
3131 }
3132 return NULL;
3133 }
3134
3135 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
3136 {
3137 int i;
3138
3139 for (i = 0; i < pnv->num_chips; i++) {
3140 PnvChip *chip = pnv->chips[i];
3141 if (chip->chip_id == chip_id) {
3142 return chip;
3143 }
3144 }
3145 return NULL;
3146 }
3147
3148 static void pnv_ics_resend(XICSFabric *xi)
3149 {
3150 PnvMachineState *pnv = PNV_MACHINE(xi);
3151 int i, j;
3152
3153 for (i = 0; i < pnv->num_chips; i++) {
3154 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
3155
3156 ics_resend(&chip8->psi.ics);
3157
3158 for (j = 0; j < chip8->num_phbs; j++) {
3159 PnvPHB *phb = chip8->phbs[j];
3160 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
3161
3162 ics_resend(&phb3->lsis);
3163 ics_resend(ICS(&phb3->msis));
3164 }
3165 }
3166 }
3167
3168 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
3169 {
3170 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
3171
3172 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
3173 }
3174
3175 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
3176 void *opaque)
3177 {
3178 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque);
3179 }
3180
3181 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf)
3182 {
3183 PnvMachineState *pnv = PNV_MACHINE(obj);
3184 int i;
3185
3186 for (i = 0; i < pnv->num_chips; i++) {
3187 PnvChip *chip = pnv->chips[i];
3188
3189 /* First CPU presenters */
3190 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf);
3191
3192 /* Then other devices, PHB, PSI, XIVE */
3193 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf);
3194 }
3195 }
3196
3197 static bool pnv_match_nvt(XiveFabric *xfb, uint8_t format,
3198 uint8_t nvt_blk, uint32_t nvt_idx,
3199 bool crowd, bool cam_ignore, uint8_t priority,
3200 uint32_t logic_serv,
3201 XiveTCTXMatch *match)
3202 {
3203 PnvMachineState *pnv = PNV_MACHINE(xfb);
3204 int i;
3205
3206 for (i = 0; i < pnv->num_chips; i++) {
3207 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
3208 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
3209 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
3210
3211 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
3212 cam_ignore, priority, logic_serv, match);
3213 }
3214
3215 return !!match->count;
3216 }
3217
3218 static bool pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
3219 uint8_t nvt_blk, uint32_t nvt_idx,
3220 bool crowd, bool cam_ignore, uint8_t priority,
3221 uint32_t logic_serv,
3222 XiveTCTXMatch *match)
3223 {
3224 PnvMachineState *pnv = PNV_MACHINE(xfb);
3225 int i;
3226
3227 for (i = 0; i < pnv->num_chips; i++) {
3228 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
3229 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
3230 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
3231
3232 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
3233 cam_ignore, priority, logic_serv, match);
3234 }
3235
3236 return !!match->count;
3237 }
3238
3239 static int pnv10_xive_broadcast(XiveFabric *xfb,
3240 uint8_t nvt_blk, uint32_t nvt_idx,
3241 bool crowd, bool cam_ignore,
3242 uint8_t priority)
3243 {
3244 PnvMachineState *pnv = PNV_MACHINE(xfb);
3245 int i;
3246
3247 for (i = 0; i < pnv->num_chips; i++) {
3248 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
3249 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
3250 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
3251
3252 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
3253 }
3254 return 0;
3255 }
3256
3257 static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format,
3258 uint8_t nvt_blk, uint32_t nvt_idx,
3259 bool crowd, bool cam_ignore, uint8_t priority,
3260 uint32_t logic_serv,
3261 XiveTCTXMatch *match)
3262 {
3263 PnvMachineState *pnv = PNV_MACHINE(xfb);
3264 int i;
3265
3266 for (i = 0; i < pnv->num_chips; i++) {
3267 Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
3268 XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
3269 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
3270
3271 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
3272 cam_ignore, priority, logic_serv, match);
3273 }
3274
3275 return !!match->count;
3276 }
3277
3278 static int pnv11_xive_broadcast(XiveFabric *xfb,
3279 uint8_t nvt_blk, uint32_t nvt_idx,
3280 bool crowd, bool cam_ignore,
3281 uint8_t priority)
3282 {
3283 PnvMachineState *pnv = PNV_MACHINE(xfb);
3284 int i;
3285
3286 for (i = 0; i < pnv->num_chips; i++) {
3287 Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
3288 XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
3289 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
3290
3291 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
3292 }
3293 return 0;
3294 }
3295
3296 static bool pnv_machine_get_big_core(Object *obj, Error **errp)
3297 {
3298 PnvMachineState *pnv = PNV_MACHINE(obj);
3299 return pnv->big_core;
3300 }
3301
3302 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)
3303 {
3304 PnvMachineState *pnv = PNV_MACHINE(obj);
3305 pnv->big_core = value;
3306 }
3307
3308 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp)
3309 {
3310 PnvMachineState *pnv = PNV_MACHINE(obj);
3311 return pnv->lpar_per_core;
3312 }
3313
3314 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp)
3315 {
3316 PnvMachineState *pnv = PNV_MACHINE(obj);
3317 pnv->lpar_per_core = value;
3318 }
3319
3320 static bool pnv_machine_get_hb(Object *obj, Error **errp)
3321 {
3322 PnvMachineState *pnv = PNV_MACHINE(obj);
3323
3324 return !!pnv->fw_load_addr;
3325 }
3326
3327 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
3328 {
3329 PnvMachineState *pnv = PNV_MACHINE(obj);
3330
3331 if (value) {
3332 pnv->fw_load_addr = 0x8000000;
3333 }
3334 }
3335
3336 static void pnv_machine_power8_class_init(ObjectClass *oc, const void *data)
3337 {
3338 MachineClass *mc = MACHINE_CLASS(oc);
3339 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3340 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
3341 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
3342
3343 static GlobalProperty phb_compat[] = {
3344 { TYPE_PNV_PHB, "version", "3" },
3345 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
3346 };
3347
3348 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
3349 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3350 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
3351
3352 xic->icp_get = pnv_icp_get;
3353 xic->ics_get = pnv_ics_get;
3354 xic->ics_resend = pnv_ics_resend;
3355
3356 pmc->compat = compat;
3357 pmc->compat_size = sizeof(compat);
3358 pmc->max_smt_threads = 8;
3359 /* POWER8 is always lpar-per-core mode */
3360 pmc->has_lpar_per_thread = false;
3361
3362 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
3363 }
3364
3365 static void pnv_machine_power9_class_init(ObjectClass *oc, const void *data)
3366 {
3367 MachineClass *mc = MACHINE_CLASS(oc);
3368 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
3369 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
3370 static const char compat[] = "qemu,powernv9\0ibm,powernv";
3371
3372 static GlobalProperty phb_compat[] = {
3373 { TYPE_PNV_PHB, "version", "4" },
3374 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
3375 };
3376
3377 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
3378 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
3379 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
3380
3381 xfc->match_nvt = pnv_match_nvt;
3382
3383 pmc->compat = compat;
3384 pmc->compat_size = sizeof(compat);
3385 pmc->max_smt_threads = 4;
3386 pmc->has_lpar_per_thread = true;
3387 pmc->dt_power_mgt = pnv_dt_power_mgt;
3388
3389 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
3390
3391 object_class_property_add_bool(oc, "big-core",
3392 pnv_machine_get_big_core,
3393 pnv_machine_set_big_core);
3394 object_class_property_set_description(oc, "big-core",
3395 "Use big-core (aka fused-core) mode");
3396
3397 object_class_property_add_bool(oc, "lpar-per-core",
3398 pnv_machine_get_lpar_per_core,
3399 pnv_machine_set_lpar_per_core);
3400 object_class_property_set_description(oc, "lpar-per-core",
3401 "Use 1 LPAR per core mode");
3402 }
3403
3404 static void pnv_machine_p10_common_class_init(ObjectClass *oc, const void *data)
3405 {
3406 MachineClass *mc = MACHINE_CLASS(oc);
3407 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
3408 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
3409 static const char compat[] = "qemu,powernv10\0ibm,powernv";
3410
3411 static GlobalProperty phb_compat[] = {
3412 { TYPE_PNV_PHB, "version", "5" },
3413 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
3414 };
3415
3416 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
3417 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
3418
3419 pmc->compat = compat;
3420 pmc->compat_size = sizeof(compat);
3421 pmc->max_smt_threads = 4;
3422 pmc->has_lpar_per_thread = true;
3423 pmc->quirk_tb_big_core = true;
3424 pmc->dt_power_mgt = pnv_dt_power_mgt;
3425
3426 xfc->match_nvt = pnv10_xive_match_nvt;
3427 xfc->broadcast = pnv10_xive_broadcast;
3428
3429 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
3430 }
3431
3432 static void pnv_machine_power10_class_init(ObjectClass *oc, const void *data)
3433 {
3434 MachineClass *mc = MACHINE_CLASS(oc);
3435
3436 pnv_machine_p10_common_class_init(oc, data);
3437 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
3438
3439 /*
3440 * This is the parent of POWER10 Rainier class, so properies go here
3441 * rather than common init (which would add them to both parent and
3442 * child which is invalid).
3443 */
3444 object_class_property_add_bool(oc, "big-core",
3445 pnv_machine_get_big_core,
3446 pnv_machine_set_big_core);
3447 object_class_property_set_description(oc, "big-core",
3448 "Use big-core (aka fused-core) mode");
3449
3450 object_class_property_add_bool(oc, "lpar-per-core",
3451 pnv_machine_get_lpar_per_core,
3452 pnv_machine_set_lpar_per_core);
3453 object_class_property_set_description(oc, "lpar-per-core",
3454 "Use 1 LPAR per core mode");
3455 }
3456
3457 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc,
3458 const void *data)
3459 {
3460 MachineClass *mc = MACHINE_CLASS(oc);
3461 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
3462
3463 pnv_machine_p10_common_class_init(oc, data);
3464 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier";
3465 pmc->i2c_init = pnv_rainier_i2c_init;
3466 }
3467
3468 static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
3469 {
3470 MachineClass *mc = MACHINE_CLASS(oc);
3471 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
3472 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
3473 static const char compat[] = "qemu,powernv11\0ibm,powernv";
3474
3475 static GlobalProperty phb_compat[] = {
3476 { TYPE_PNV_PHB, "version", "5" },
3477 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
3478 };
3479
3480 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
3481
3482 pmc->compat = compat;
3483 pmc->compat_size = sizeof(compat);
3484 pmc->max_smt_threads = 4;
3485 pmc->has_lpar_per_thread = true;
3486 pmc->quirk_tb_big_core = true;
3487 pmc->dt_power_mgt = pnv_dt_power_mgt;
3488
3489 xfc->match_nvt = pnv11_xive_match_nvt;
3490 xfc->broadcast = pnv11_xive_broadcast;
3491
3492 mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
3493 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
3494
3495 mc->alias = "powernv";
3496
3497 object_class_property_add_bool(oc, "big-core",
3498 pnv_machine_get_big_core,
3499 pnv_machine_set_big_core);
3500 object_class_property_set_description(oc, "big-core",
3501 "Use big-core (aka fused-core) mode");
3502
3503 object_class_property_add_bool(oc, "lpar-per-core",
3504 pnv_machine_get_lpar_per_core,
3505 pnv_machine_set_lpar_per_core);
3506 object_class_property_set_description(oc, "lpar-per-core",
3507 "Use 1 LPAR per core mode");
3508 }
3509
3510 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
3511 {
3512 CPUPPCState *env = cpu_env(cs);
3513
3514 cpu_synchronize_state(cs);
3515 ppc_cpu_do_system_reset(cs);
3516 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
3517 /*
3518 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
3519 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
3520 * (PPC_BIT(43)).
3521 */
3522 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
3523 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
3524 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
3525 }
3526 } else {
3527 /*
3528 * For non-powersave system resets, SRR1[42:45] are defined to be
3529 * implementation-dependent. The POWER9 User Manual specifies that
3530 * an external (SCOM driven, which may come from a BMC nmi command or
3531 * another CPU requesting a NMI IPI) system reset exception should be
3532 * 0b0010 (PPC_BIT(44)).
3533 */
3534 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
3535 }
3536 if (arg.host_int == 1) {
3537 cpu_resume(cs);
3538 }
3539 }
3540
3541 /*
3542 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was
3543 * paused.
3544 */
3545 void pnv_cpu_do_nmi_resume(CPUState *cs)
3546 {
3547 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1));
3548 }
3549
3550 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
3551 {
3552 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0));
3553 }
3554
3555 static void pnv_nmi(NMIState *ns)
3556 {
3557 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
3558 int i;
3559
3560 for (i = 0; i < pnv->num_chips; i++) {
3561 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL);
3562 }
3563 }
3564
3565 static void pnv_machine_class_init(ObjectClass *oc, const void *data)
3566 {
3567 MachineClass *mc = MACHINE_CLASS(oc);
3568 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3569 NMIClass *nc = NMI_CLASS(oc);
3570
3571 mc->desc = "IBM PowerNV (Non-Virtualized)";
3572 mc->init = pnv_init;
3573 mc->reset = pnv_reset;
3574 mc->max_cpus = MAX_CPUS;
3575 /* Pnv provides a AHCI device for storage */
3576 mc->block_default_type = IF_IDE;
3577 mc->no_parallel = 1;
3578 mc->default_boot_order = NULL;
3579 /*
3580 * RAM defaults to less than 2048 for 32-bit hosts, and large
3581 * enough to fit the maximum initrd size at it's load address
3582 */
3583 mc->default_ram_size = 1 * GiB;
3584 mc->default_ram_id = "pnv.ram";
3585 ispc->print_info = pnv_pic_print_info;
3586 nc->raise_nmi = pnv_nmi;
3587
3588 object_class_property_add_bool(oc, "hb-mode",
3589 pnv_machine_get_hb, pnv_machine_set_hb);
3590 object_class_property_set_description(oc, "hb-mode",
3591 "Use a hostboot like boot loader");
3592 }
3593
3594 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
3595 { \
3596 .name = type, \
3597 .class_init = class_initfn, \
3598 .parent = TYPE_PNV8_CHIP, \
3599 }
3600
3601 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
3602 { \
3603 .name = type, \
3604 .class_init = class_initfn, \
3605 .parent = TYPE_PNV9_CHIP, \
3606 }
3607
3608 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
3609 { \
3610 .name = type, \
3611 .class_init = class_initfn, \
3612 .parent = TYPE_PNV10_CHIP, \
3613 }
3614
3615 #define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
3616 { \
3617 .name = type, \
3618 .class_init = class_initfn, \
3619 .parent = TYPE_PNV11_CHIP, \
3620 }
3621
3622 static const TypeInfo types[] = {
3623 {
3624 .name = MACHINE_TYPE_NAME("powernv11"),
3625 .parent = TYPE_PNV_MACHINE,
3626 .class_init = pnv_machine_power11_class_init,
3627 .interfaces = (InterfaceInfo[]) {
3628 { TYPE_XIVE_FABRIC },
3629 { },
3630 },
3631 },
3632 {
3633 .name = MACHINE_TYPE_NAME("powernv10-rainier"),
3634 .parent = MACHINE_TYPE_NAME("powernv10"),
3635 .class_init = pnv_machine_p10_rainier_class_init,
3636 },
3637 {
3638 .name = MACHINE_TYPE_NAME("powernv10"),
3639 .parent = TYPE_PNV_MACHINE,
3640 .class_init = pnv_machine_power10_class_init,
3641 .interfaces = (const InterfaceInfo[]) {
3642 { TYPE_XIVE_FABRIC },
3643 { },
3644 },
3645 },
3646 {
3647 .name = MACHINE_TYPE_NAME("powernv9"),
3648 .parent = TYPE_PNV_MACHINE,
3649 .class_init = pnv_machine_power9_class_init,
3650 .interfaces = (const InterfaceInfo[]) {
3651 { TYPE_XIVE_FABRIC },
3652 { },
3653 },
3654 },
3655 {
3656 .name = MACHINE_TYPE_NAME("powernv8"),
3657 .parent = TYPE_PNV_MACHINE,
3658 .class_init = pnv_machine_power8_class_init,
3659 .interfaces = (const InterfaceInfo[]) {
3660 { TYPE_XICS_FABRIC },
3661 { },
3662 },
3663 },
3664 {
3665 .name = TYPE_PNV_MACHINE,
3666 .parent = TYPE_MACHINE,
3667 .abstract = true,
3668 .instance_size = sizeof(PnvMachineState),
3669 .class_init = pnv_machine_class_init,
3670 .class_size = sizeof(PnvMachineClass),
3671 .interfaces = (const InterfaceInfo[]) {
3672 { TYPE_INTERRUPT_STATS_PROVIDER },
3673 { TYPE_NMI },
3674 { },
3675 },
3676 },
3677 {
3678 .name = TYPE_PNV_CHIP,
3679 .parent = TYPE_SYS_BUS_DEVICE,
3680 .class_init = pnv_chip_class_init,
3681 .instance_size = sizeof(PnvChip),
3682 .class_size = sizeof(PnvChipClass),
3683 .abstract = true,
3684 },
3685
3686 /*
3687 * P11 chip and variants
3688 */
3689 {
3690 .name = TYPE_PNV11_CHIP,
3691 .parent = TYPE_PNV_CHIP,
3692 .instance_init = pnv_chip_power11_instance_init,
3693 .instance_size = sizeof(Pnv11Chip),
3694 },
3695 DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
3696
3697 /*
3698 * P10 chip and variants
3699 */
3700 {
3701 .name = TYPE_PNV10_CHIP,
3702 .parent = TYPE_PNV_CHIP,
3703 .instance_init = pnv_chip_power10_instance_init,
3704 .instance_size = sizeof(Pnv10Chip),
3705 },
3706 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
3707
3708 /*
3709 * P9 chip and variants
3710 */
3711 {
3712 .name = TYPE_PNV9_CHIP,
3713 .parent = TYPE_PNV_CHIP,
3714 .instance_init = pnv_chip_power9_instance_init,
3715 .instance_size = sizeof(Pnv9Chip),
3716 },
3717 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
3718
3719 /*
3720 * P8 chip and variants
3721 */
3722 {
3723 .name = TYPE_PNV8_CHIP,
3724 .parent = TYPE_PNV_CHIP,
3725 .instance_init = pnv_chip_power8_instance_init,
3726 .instance_size = sizeof(Pnv8Chip),
3727 },
3728 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
3729 };
3730
3731 DEFINE_TYPES(types)