| 1 | /* |
| 2 | * QEMU PowerPC PowerNV ADU unit |
| 3 | * |
| 4 | * The ADU unit actually implements XSCOM, which is the bridge between MMIO |
| 5 | * and PIB. However it also includes control and status registers and other |
| 6 | * functions that are exposed as PIB (xscom) registers. |
| 7 | * |
| 8 | * To keep things simple, pnv_xscom.c remains the XSCOM bridge |
| 9 | * implementation, and pnv_adu.c implements the ADU registers and other |
| 10 | * functions. |
| 11 | * |
| 12 | * Copyright (c) 2024, IBM Corporation. |
| 13 | * |
| 14 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "qemu/log.h" |
| 19 | |
| 20 | #include "hw/core/qdev-properties.h" |
| 21 | #include "hw/ppc/pnv.h" |
| 22 | #include "hw/ppc/pnv_adu.h" |
| 23 | #include "hw/ppc/pnv_chip.h" |
| 24 | #include "hw/ppc/pnv_lpc.h" |
| 25 | #include "hw/ppc/pnv_xscom.h" |
| 26 | #include "migration/vmstate.h" |
| 27 | #include "trace.h" |
| 28 | |
| 29 | #define ADU_LPC_BASE_REG 0x40 |
| 30 | #define ADU_LPC_CMD_REG 0x41 |
| 31 | #define ADU_LPC_DATA_REG 0x42 |
| 32 | #define ADU_LPC_STATUS_REG 0x43 |
| 33 | |
| 34 | static uint64_t pnv_adu_xscom_read(void *opaque, hwaddr addr, unsigned width) |
| 35 | { |
| 36 | PnvADU *adu = PNV_ADU(opaque); |
| 37 | uint32_t offset = addr >> 3; |
| 38 | uint64_t val = 0; |
| 39 | |
| 40 | switch (offset) { |
| 41 | case 0x18: /* Receive status reg */ |
| 42 | case 0x12: /* log register */ |
| 43 | case 0x13: /* error register */ |
| 44 | break; |
| 45 | case ADU_LPC_BASE_REG: |
| 46 | /* |
| 47 | * LPC Address Map in Pervasive ADU Workbook |
| 48 | * |
| 49 | * return PNV10_LPCM_BASE(chip) & PPC_BITMASK(8, 31); |
| 50 | * XXX: implement as class property, or get from LPC? |
| 51 | */ |
| 52 | qemu_log_mask(LOG_UNIMP, "ADU: LPC_BASE_REG is not implemented\n"); |
| 53 | break; |
| 54 | case ADU_LPC_CMD_REG: |
| 55 | val = adu->lpc_cmd_reg; |
| 56 | break; |
| 57 | case ADU_LPC_DATA_REG: |
| 58 | val = adu->lpc_data_reg; |
| 59 | break; |
| 60 | case ADU_LPC_STATUS_REG: |
| 61 | val = PPC_BIT(0); /* ack / done */ |
| 62 | break; |
| 63 | |
| 64 | default: |
| 65 | qemu_log_mask(LOG_UNIMP, "ADU Unimplemented read register: Ox%08x\n", |
| 66 | offset); |
| 67 | } |
| 68 | |
| 69 | trace_pnv_adu_xscom_read(addr, val); |
| 70 | |
| 71 | return val; |
| 72 | } |
| 73 | |
| 74 | static bool lpc_cmd_read(PnvADU *adu) |
| 75 | { |
| 76 | return !!(adu->lpc_cmd_reg & PPC_BIT(0)); |
| 77 | } |
| 78 | |
| 79 | static bool lpc_cmd_write(PnvADU *adu) |
| 80 | { |
| 81 | return !lpc_cmd_read(adu); |
| 82 | } |
| 83 | |
| 84 | static uint32_t lpc_cmd_addr(PnvADU *adu) |
| 85 | { |
| 86 | return (adu->lpc_cmd_reg & PPC_BITMASK(32, 63)) >> PPC_BIT_NR(63); |
| 87 | } |
| 88 | |
| 89 | static uint32_t lpc_cmd_size(PnvADU *adu) |
| 90 | { |
| 91 | return (adu->lpc_cmd_reg & PPC_BITMASK(5, 11)) >> PPC_BIT_NR(11); |
| 92 | } |
| 93 | |
| 94 | static void pnv_adu_xscom_write(void *opaque, hwaddr addr, uint64_t val, |
| 95 | unsigned width) |
| 96 | { |
| 97 | PnvADU *adu = PNV_ADU(opaque); |
| 98 | uint32_t offset = addr >> 3; |
| 99 | |
| 100 | trace_pnv_adu_xscom_write(addr, val); |
| 101 | |
| 102 | switch (offset) { |
| 103 | case 0x18: /* Receive status reg */ |
| 104 | case 0x12: /* log register */ |
| 105 | case 0x13: /* error register */ |
| 106 | break; |
| 107 | |
| 108 | case ADU_LPC_BASE_REG: |
| 109 | qemu_log_mask(LOG_UNIMP, |
| 110 | "ADU: Changing LPC_BASE_REG is not implemented\n"); |
| 111 | break; |
| 112 | |
| 113 | case ADU_LPC_CMD_REG: |
| 114 | adu->lpc_cmd_reg = val; |
| 115 | if (lpc_cmd_read(adu)) { |
| 116 | uint32_t lpc_addr = lpc_cmd_addr(adu); |
| 117 | uint32_t lpc_size = lpc_cmd_size(adu); |
| 118 | uint64_t data = 0; |
| 119 | |
| 120 | if (!is_power_of_2(lpc_size) || lpc_size > sizeof(data)) { |
| 121 | qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " |
| 122 | "size:%" PRId32 "\n", lpc_size); |
| 123 | break; |
| 124 | } |
| 125 | |
| 126 | pnv_lpc_opb_read(adu->lpc, lpc_addr, (void *)&data, lpc_size); |
| 127 | |
| 128 | /* |
| 129 | * ADU access is performed within 8-byte aligned sectors. Smaller |
| 130 | * access sizes don't get formatted to the least significant byte, |
| 131 | * but rather appear in the data reg at the same offset as the |
| 132 | * address in memory. This shifts them into that position. |
| 133 | */ |
| 134 | adu->lpc_data_reg = be64_to_cpu(data) >> ((lpc_addr & 7) * 8); |
| 135 | } |
| 136 | break; |
| 137 | |
| 138 | case ADU_LPC_DATA_REG: |
| 139 | adu->lpc_data_reg = val; |
| 140 | if (lpc_cmd_write(adu)) { |
| 141 | uint32_t lpc_addr = lpc_cmd_addr(adu); |
| 142 | uint32_t lpc_size = lpc_cmd_size(adu); |
| 143 | uint64_t data; |
| 144 | |
| 145 | if (!is_power_of_2(lpc_size) || lpc_size > sizeof(data)) { |
| 146 | qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " |
| 147 | "size:%" PRId32 "\n", lpc_size); |
| 148 | break; |
| 149 | } |
| 150 | |
| 151 | data = cpu_to_be64(val) >> ((lpc_addr & 7) * 8); /* See above */ |
| 152 | pnv_lpc_opb_write(adu->lpc, lpc_addr, (void *)&data, lpc_size); |
| 153 | } |
| 154 | break; |
| 155 | |
| 156 | case ADU_LPC_STATUS_REG: |
| 157 | qemu_log_mask(LOG_UNIMP, |
| 158 | "ADU: Changing LPC_STATUS_REG is not implemented\n"); |
| 159 | break; |
| 160 | |
| 161 | default: |
| 162 | qemu_log_mask(LOG_UNIMP, "ADU Unimplemented write register: Ox%08x\n", |
| 163 | offset); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | const MemoryRegionOps pnv_adu_xscom_ops = { |
| 168 | .read = pnv_adu_xscom_read, |
| 169 | .write = pnv_adu_xscom_write, |
| 170 | .valid.min_access_size = 8, |
| 171 | .valid.max_access_size = 8, |
| 172 | .impl.min_access_size = 8, |
| 173 | .impl.max_access_size = 8, |
| 174 | .endianness = DEVICE_BIG_ENDIAN, |
| 175 | }; |
| 176 | |
| 177 | static void pnv_adu_realize(DeviceState *dev, Error **errp) |
| 178 | { |
| 179 | PnvADU *adu = PNV_ADU(dev); |
| 180 | |
| 181 | assert(adu->lpc); |
| 182 | |
| 183 | /* XScom regions for ADU registers */ |
| 184 | pnv_xscom_region_init(&adu->xscom_regs, OBJECT(dev), |
| 185 | &pnv_adu_xscom_ops, adu, "xscom-adu", |
| 186 | PNV9_XSCOM_ADU_SIZE); |
| 187 | } |
| 188 | |
| 189 | static const Property pnv_adu_properties[] = { |
| 190 | DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *), |
| 191 | }; |
| 192 | |
| 193 | static const VMStateDescription pnv_adu_vmstate = { |
| 194 | .name = TYPE_PNV_ADU, |
| 195 | .version_id = 1, |
| 196 | .fields = (const VMStateField[]) { |
| 197 | VMSTATE_UINT64(lpc_cmd_reg, PnvADU), |
| 198 | VMSTATE_UINT64(lpc_data_reg, PnvADU), |
| 199 | VMSTATE_END_OF_LIST(), |
| 200 | }, |
| 201 | }; |
| 202 | |
| 203 | static void pnv_adu_class_init(ObjectClass *klass, const void *data) |
| 204 | { |
| 205 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 206 | |
| 207 | dc->realize = pnv_adu_realize; |
| 208 | dc->desc = "PowerNV ADU"; |
| 209 | device_class_set_props(dc, pnv_adu_properties); |
| 210 | dc->user_creatable = false; |
| 211 | dc->vmsd = &pnv_adu_vmstate; |
| 212 | } |
| 213 | |
| 214 | static const TypeInfo pnv_adu_type_info = { |
| 215 | .name = TYPE_PNV_ADU, |
| 216 | .parent = TYPE_DEVICE, |
| 217 | .instance_size = sizeof(PnvADU), |
| 218 | .class_init = pnv_adu_class_init, |
| 219 | .interfaces = (const InterfaceInfo[]) { |
| 220 | { TYPE_PNV_XSCOM_INTERFACE }, |
| 221 | { } }, |
| 222 | }; |
| 223 | |
| 224 | static void pnv_adu_register_types(void) |
| 225 | { |
| 226 | type_register_static(&pnv_adu_type_info); |
| 227 | } |
| 228 | |
| 229 | type_init(pnv_adu_register_types); |