| 1 | /* |
| 2 | * QEMU PowerPC PowerNV LPC controller |
| 3 | * |
| 4 | * Copyright (c) 2016, IBM Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "target/ppc/cpu.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "qemu/log.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "hw/isa/isa.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "hw/ppc/pnv.h" |
| 29 | #include "hw/ppc/pnv_chip.h" |
| 30 | #include "hw/ppc/pnv_lpc.h" |
| 31 | #include "hw/ppc/pnv_xscom.h" |
| 32 | #include "hw/ppc/fdt.h" |
| 33 | #include "migration/vmstate.h" |
| 34 | |
| 35 | #include <libfdt.h> |
| 36 | |
| 37 | enum { |
| 38 | ECCB_CTL = 0, |
| 39 | ECCB_RESET = 1, |
| 40 | ECCB_STAT = 2, |
| 41 | ECCB_DATA = 3, |
| 42 | }; |
| 43 | |
| 44 | /* OPB Master LS registers */ |
| 45 | #define OPB_MASTER_LS_ROUTE0 0x8 |
| 46 | #define OPB_MASTER_LS_ROUTE1 0xC |
| 47 | #define OPB_MASTER_LS_IRQ_STAT 0x50 |
| 48 | #define OPB_MASTER_IRQ_LPC 0x00000800 |
| 49 | #define OPB_MASTER_LS_IRQ_MASK 0x54 |
| 50 | #define OPB_MASTER_LS_IRQ_POL 0x58 |
| 51 | #define OPB_MASTER_LS_IRQ_INPUT 0x5c |
| 52 | |
| 53 | /* LPC HC registers */ |
| 54 | #define LPC_HC_FW_SEG_IDSEL 0x24 |
| 55 | #define LPC_HC_FW_RD_ACC_SIZE 0x28 |
| 56 | #define LPC_HC_FW_RD_1B 0x00000000 |
| 57 | #define LPC_HC_FW_RD_2B 0x01000000 |
| 58 | #define LPC_HC_FW_RD_4B 0x02000000 |
| 59 | #define LPC_HC_FW_RD_16B 0x04000000 |
| 60 | #define LPC_HC_FW_RD_128B 0x07000000 |
| 61 | #define LPC_HC_IRQSER_CTRL 0x30 |
| 62 | #define LPC_HC_IRQSER_EN 0x80000000 |
| 63 | #define LPC_HC_IRQSER_QMODE 0x40000000 |
| 64 | #define LPC_HC_IRQSER_START_MASK 0x03000000 |
| 65 | #define LPC_HC_IRQSER_START_4CLK 0x00000000 |
| 66 | #define LPC_HC_IRQSER_START_6CLK 0x01000000 |
| 67 | #define LPC_HC_IRQSER_START_8CLK 0x02000000 |
| 68 | #define LPC_HC_IRQSER_AUTO_CLEAR 0x00800000 |
| 69 | #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ |
| 70 | #define LPC_HC_IRQSTAT 0x38 |
| 71 | #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ |
| 72 | #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */ |
| 73 | #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000 |
| 74 | #define LPC_HC_IRQ_LRESET 0x00000400 |
| 75 | #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080 |
| 76 | #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040 |
| 77 | #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020 |
| 78 | #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010 |
| 79 | #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008 |
| 80 | #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004 |
| 81 | #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002 |
| 82 | #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001 |
| 83 | #define LPC_HC_ERROR_ADDRESS 0x40 |
| 84 | |
| 85 | #define LPC_OPB_SIZE 0x100000000ull |
| 86 | |
| 87 | #define ISA_IO_SIZE 0x00010000 |
| 88 | #define ISA_MEM_SIZE 0x10000000 |
| 89 | #define ISA_FW_SIZE 0x100000000 |
| 90 | #define LPC_IO_OPB_ADDR 0xd0010000 |
| 91 | #define LPC_IO_OPB_SIZE 0x00010000 |
| 92 | #define LPC_MEM_OPB_ADDR 0xe0000000 |
| 93 | #define LPC_MEM_OPB_SIZE 0x10000000 |
| 94 | #define LPC_FW_OPB_ADDR 0xf0000000 |
| 95 | #define LPC_FW_OPB_SIZE 0x10000000 |
| 96 | |
| 97 | #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 |
| 98 | #define LPC_OPB_REGS_OPB_SIZE 0x00000060 |
| 99 | #define LPC_OPB_REGS_OPBA_ADDR 0xc0011000 |
| 100 | #define LPC_OPB_REGS_OPBA_SIZE 0x00000008 |
| 101 | #define LPC_HC_REGS_OPB_ADDR 0xc0012000 |
| 102 | #define LPC_HC_REGS_OPB_SIZE 0x00000100 |
| 103 | |
| 104 | static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) |
| 105 | { |
| 106 | const char compat[] = "ibm,power8-lpc\0ibm,lpc"; |
| 107 | char *name; |
| 108 | int offset; |
| 109 | uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE; |
| 110 | uint32_t reg[] = { |
| 111 | cpu_to_be32(lpc_pcba), |
| 112 | cpu_to_be32(PNV_XSCOM_LPC_SIZE) |
| 113 | }; |
| 114 | |
| 115 | name = g_strdup_printf("isa@%x", lpc_pcba); |
| 116 | offset = fdt_add_subnode(fdt, xscom_offset, name); |
| 117 | _FDT(offset); |
| 118 | g_free(name); |
| 119 | |
| 120 | _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); |
| 121 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); |
| 122 | _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); |
| 123 | _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | /* POWER9 only */ |
| 128 | int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, |
| 129 | uint64_t lpcm_size) |
| 130 | { |
| 131 | const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; |
| 132 | const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; |
| 133 | char *name; |
| 134 | int offset, lpcm_offset; |
| 135 | uint32_t opb_ranges[8] = { 0, |
| 136 | cpu_to_be32(lpcm_addr >> 32), |
| 137 | cpu_to_be32((uint32_t)lpcm_addr), |
| 138 | cpu_to_be32(lpcm_size / 2), |
| 139 | cpu_to_be32(lpcm_size / 2), |
| 140 | cpu_to_be32(lpcm_addr >> 32), |
| 141 | cpu_to_be32(lpcm_size / 2), |
| 142 | cpu_to_be32(lpcm_size / 2), |
| 143 | }; |
| 144 | uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32), |
| 145 | cpu_to_be32((uint32_t)lpcm_addr), |
| 146 | cpu_to_be32(lpcm_size >> 32), |
| 147 | cpu_to_be32((uint32_t)lpcm_size), |
| 148 | }; |
| 149 | uint32_t lpc_ranges[12] = { 0, 0, |
| 150 | cpu_to_be32(LPC_MEM_OPB_ADDR), |
| 151 | cpu_to_be32(LPC_MEM_OPB_SIZE), |
| 152 | cpu_to_be32(1), 0, |
| 153 | cpu_to_be32(LPC_IO_OPB_ADDR), |
| 154 | cpu_to_be32(LPC_IO_OPB_SIZE), |
| 155 | cpu_to_be32(3), 0, |
| 156 | cpu_to_be32(LPC_FW_OPB_ADDR), |
| 157 | cpu_to_be32(LPC_FW_OPB_SIZE), |
| 158 | }; |
| 159 | uint32_t reg[2]; |
| 160 | |
| 161 | /* |
| 162 | * OPB bus |
| 163 | */ |
| 164 | name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); |
| 165 | lpcm_offset = fdt_add_subnode(fdt, root_offset, name); |
| 166 | _FDT(lpcm_offset); |
| 167 | g_free(name); |
| 168 | |
| 169 | _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg)))); |
| 170 | _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); |
| 171 | _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1))); |
| 172 | _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat)))); |
| 173 | _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id))); |
| 174 | _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges, |
| 175 | sizeof(opb_ranges)))); |
| 176 | |
| 177 | /* |
| 178 | * OPB Master registers |
| 179 | */ |
| 180 | name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR); |
| 181 | offset = fdt_add_subnode(fdt, lpcm_offset, name); |
| 182 | _FDT(offset); |
| 183 | g_free(name); |
| 184 | |
| 185 | reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR); |
| 186 | reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE); |
| 187 | _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); |
| 188 | _FDT((fdt_setprop_string(fdt, offset, "compatible", |
| 189 | "ibm,power9-lpcm-opb-master"))); |
| 190 | |
| 191 | /* |
| 192 | * OPB arbitrer registers |
| 193 | */ |
| 194 | name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR); |
| 195 | offset = fdt_add_subnode(fdt, lpcm_offset, name); |
| 196 | _FDT(offset); |
| 197 | g_free(name); |
| 198 | |
| 199 | reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR); |
| 200 | reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE); |
| 201 | _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); |
| 202 | _FDT((fdt_setprop_string(fdt, offset, "compatible", |
| 203 | "ibm,power9-lpcm-opb-arbiter"))); |
| 204 | |
| 205 | /* |
| 206 | * LPC Host Controller registers |
| 207 | */ |
| 208 | name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR); |
| 209 | offset = fdt_add_subnode(fdt, lpcm_offset, name); |
| 210 | _FDT(offset); |
| 211 | g_free(name); |
| 212 | |
| 213 | reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR); |
| 214 | reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE); |
| 215 | _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); |
| 216 | _FDT((fdt_setprop_string(fdt, offset, "compatible", |
| 217 | "ibm,power9-lpc-controller"))); |
| 218 | |
| 219 | name = g_strdup_printf("lpc@0"); |
| 220 | offset = fdt_add_subnode(fdt, lpcm_offset, name); |
| 221 | _FDT(offset); |
| 222 | g_free(name); |
| 223 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); |
| 224 | _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); |
| 225 | _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat, |
| 226 | sizeof(lpc_compat)))); |
| 227 | _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges, |
| 228 | sizeof(lpc_ranges)))); |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * These read/write handlers of the OPB address space should be common |
| 235 | * with the P9 LPC Controller which uses direct MMIOs. |
| 236 | * |
| 237 | * TODO: rework to use address_space_stq() and address_space_ldq() |
| 238 | * instead. |
| 239 | */ |
| 240 | bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr, |
| 241 | uint8_t *data, int sz) |
| 242 | { |
| 243 | /* XXX Handle access size limits and FW read caching here */ |
| 244 | return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, |
| 245 | data, sz); |
| 246 | } |
| 247 | |
| 248 | bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr, |
| 249 | uint8_t *data, int sz) |
| 250 | { |
| 251 | /* XXX Handle access size limits here */ |
| 252 | return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, |
| 253 | data, sz); |
| 254 | } |
| 255 | |
| 256 | #define ECCB_CTL_READ PPC_BIT(15) |
| 257 | #define ECCB_CTL_SZ_LSH (63 - 7) |
| 258 | #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7) |
| 259 | #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63) |
| 260 | |
| 261 | #define ECCB_STAT_OP_DONE PPC_BIT(52) |
| 262 | #define ECCB_STAT_OP_ERR PPC_BIT(52) |
| 263 | #define ECCB_STAT_RD_DATA_LSH (63 - 37) |
| 264 | #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) |
| 265 | |
| 266 | static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd) |
| 267 | { |
| 268 | /* XXX Check for magic bits at the top, addr size etc... */ |
| 269 | unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH; |
| 270 | uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK; |
| 271 | uint8_t data[8]; |
| 272 | bool success; |
| 273 | |
| 274 | if (sz > sizeof(data)) { |
| 275 | qemu_log_mask(LOG_GUEST_ERROR, |
| 276 | "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz); |
| 277 | return; |
| 278 | } |
| 279 | |
| 280 | if (cmd & ECCB_CTL_READ) { |
| 281 | success = pnv_lpc_opb_read(lpc, opb_addr, data, sz); |
| 282 | if (success) { |
| 283 | lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | |
| 284 | (((uint64_t)data[0]) << 24 | |
| 285 | ((uint64_t)data[1]) << 16 | |
| 286 | ((uint64_t)data[2]) << 8 | |
| 287 | ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH; |
| 288 | } else { |
| 289 | lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | |
| 290 | (0xffffffffull << ECCB_STAT_RD_DATA_LSH); |
| 291 | } |
| 292 | } else { |
| 293 | data[0] = lpc->eccb_data_reg >> 24; |
| 294 | data[1] = lpc->eccb_data_reg >> 16; |
| 295 | data[2] = lpc->eccb_data_reg >> 8; |
| 296 | data[3] = lpc->eccb_data_reg; |
| 297 | |
| 298 | success = pnv_lpc_opb_write(lpc, opb_addr, data, sz); |
| 299 | lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; |
| 300 | } |
| 301 | /* XXX Which error bit (if any) to signal OPB error ? */ |
| 302 | } |
| 303 | |
| 304 | static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size) |
| 305 | { |
| 306 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 307 | uint32_t offset = addr >> 3; |
| 308 | uint64_t val = 0; |
| 309 | |
| 310 | switch (offset & 3) { |
| 311 | case ECCB_CTL: |
| 312 | case ECCB_RESET: |
| 313 | val = 0; |
| 314 | break; |
| 315 | case ECCB_STAT: |
| 316 | val = lpc->eccb_stat_reg; |
| 317 | lpc->eccb_stat_reg = 0; |
| 318 | break; |
| 319 | case ECCB_DATA: |
| 320 | val = ((uint64_t)lpc->eccb_data_reg) << 32; |
| 321 | break; |
| 322 | } |
| 323 | return val; |
| 324 | } |
| 325 | |
| 326 | static void pnv_lpc_xscom_write(void *opaque, hwaddr addr, |
| 327 | uint64_t val, unsigned size) |
| 328 | { |
| 329 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 330 | uint32_t offset = addr >> 3; |
| 331 | |
| 332 | switch (offset & 3) { |
| 333 | case ECCB_CTL: |
| 334 | pnv_lpc_do_eccb(lpc, val); |
| 335 | break; |
| 336 | case ECCB_RESET: |
| 337 | /* XXXX */ |
| 338 | break; |
| 339 | case ECCB_STAT: |
| 340 | break; |
| 341 | case ECCB_DATA: |
| 342 | lpc->eccb_data_reg = val >> 32; |
| 343 | break; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | static const MemoryRegionOps pnv_lpc_xscom_ops = { |
| 348 | .read = pnv_lpc_xscom_read, |
| 349 | .write = pnv_lpc_xscom_write, |
| 350 | .valid.min_access_size = 8, |
| 351 | .valid.max_access_size = 8, |
| 352 | .impl.min_access_size = 8, |
| 353 | .impl.max_access_size = 8, |
| 354 | .endianness = DEVICE_BIG_ENDIAN, |
| 355 | }; |
| 356 | |
| 357 | static void pnv_lpc_opb_noresponse(PnvLpcController *lpc); |
| 358 | |
| 359 | static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size) |
| 360 | { |
| 361 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 362 | uint64_t val = 0; |
| 363 | uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK; |
| 364 | MemTxResult result; |
| 365 | |
| 366 | switch (size) { |
| 367 | case 4: |
| 368 | val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, |
| 369 | &result); |
| 370 | break; |
| 371 | case 1: |
| 372 | val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, |
| 373 | &result); |
| 374 | break; |
| 375 | default: |
| 376 | qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" |
| 377 | HWADDR_PRIx " invalid size %d\n", addr, size); |
| 378 | return 0; |
| 379 | } |
| 380 | |
| 381 | if (result != MEMTX_OK) { |
| 382 | pnv_lpc_opb_noresponse(lpc); |
| 383 | qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" |
| 384 | HWADDR_PRIx "\n", addr); |
| 385 | } |
| 386 | |
| 387 | return val; |
| 388 | } |
| 389 | |
| 390 | static void pnv_lpc_mmio_write(void *opaque, hwaddr addr, |
| 391 | uint64_t val, unsigned size) |
| 392 | { |
| 393 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 394 | uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK; |
| 395 | MemTxResult result; |
| 396 | |
| 397 | switch (size) { |
| 398 | case 4: |
| 399 | address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, |
| 400 | &result); |
| 401 | break; |
| 402 | case 1: |
| 403 | address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, |
| 404 | &result); |
| 405 | break; |
| 406 | default: |
| 407 | qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" |
| 408 | HWADDR_PRIx " invalid size %d\n", addr, size); |
| 409 | return; |
| 410 | } |
| 411 | |
| 412 | if (result != MEMTX_OK) { |
| 413 | pnv_lpc_opb_noresponse(lpc); |
| 414 | qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" |
| 415 | HWADDR_PRIx "\n", addr); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static const MemoryRegionOps pnv_lpc_mmio_ops = { |
| 420 | .read = pnv_lpc_mmio_read, |
| 421 | .write = pnv_lpc_mmio_write, |
| 422 | .impl = { |
| 423 | .min_access_size = 1, |
| 424 | .max_access_size = 4, |
| 425 | }, |
| 426 | .endianness = DEVICE_BIG_ENDIAN, |
| 427 | }; |
| 428 | |
| 429 | /* Program the POWER9 LPC irq to PSI serirq routing table */ |
| 430 | static void pnv_lpc_eval_serirq_routes(PnvLpcController *lpc) |
| 431 | { |
| 432 | int irq; |
| 433 | |
| 434 | if (!lpc->psi_has_serirq) { |
| 435 | if ((lpc->opb_irq_route0 & PPC_BITMASK32(8, 13)) || |
| 436 | (lpc->opb_irq_route1 & PPC_BITMASK32(4, 31))) { |
| 437 | qemu_log_mask(LOG_GUEST_ERROR, |
| 438 | "OPB: setting serirq routing on POWER8 system, ignoring.\n"); |
| 439 | } |
| 440 | return; |
| 441 | } |
| 442 | |
| 443 | /* |
| 444 | * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 |
| 445 | * bits, split across 2 OPB registers. |
| 446 | */ |
| 447 | for (irq = 0; irq <= 13; irq++) { |
| 448 | int serirq = extract32(lpc->opb_irq_route1, |
| 449 | PPC_BIT32_NR(5 + irq * 2), 2); |
| 450 | lpc->irq_to_serirq_route[irq] = serirq; |
| 451 | } |
| 452 | |
| 453 | for (irq = 14; irq < ISA_NUM_IRQS; irq++) { |
| 454 | int serirq = extract32(lpc->opb_irq_route0, |
| 455 | PPC_BIT32_NR(9 + (irq - 14) * 2), 2); |
| 456 | lpc->irq_to_serirq_route[irq] = serirq; |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | static void pnv_lpc_eval_irqs(PnvLpcController *lpc) |
| 461 | { |
| 462 | uint32_t active_irqs = 0; |
| 463 | |
| 464 | active_irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; |
| 465 | if (!(lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN)) { |
| 466 | active_irqs &= ~LPC_HC_IRQ_SERIRQ_ALL; |
| 467 | } |
| 468 | |
| 469 | /* Reflect the interrupt */ |
| 470 | if (lpc->psi_has_serirq) { |
| 471 | /* |
| 472 | * POWER9 and later have routing fields in OPB master registers that |
| 473 | * send LPC irqs to 4 output lines that raise the PSI SERIRQ irqs. |
| 474 | * These don't appear to get latched into an OPB register like the |
| 475 | * LPCHC irqs. |
| 476 | */ |
| 477 | bool serirq_out[4] = { false, false, false, false }; |
| 478 | int irq; |
| 479 | |
| 480 | for (irq = 0; irq < ISA_NUM_IRQS; irq++) { |
| 481 | if (active_irqs & (LPC_HC_IRQ_SERIRQ0 >> irq)) { |
| 482 | serirq_out[lpc->irq_to_serirq_route[irq]] = true; |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | qemu_set_irq(lpc->psi_irq_serirq[0], serirq_out[0]); |
| 487 | qemu_set_irq(lpc->psi_irq_serirq[1], serirq_out[1]); |
| 488 | qemu_set_irq(lpc->psi_irq_serirq[2], serirq_out[2]); |
| 489 | qemu_set_irq(lpc->psi_irq_serirq[3], serirq_out[3]); |
| 490 | |
| 491 | /* |
| 492 | * POWER9 and later LPC controller internal irqs still go via the OPB |
| 493 | * and LPCHC PSI irqs like P8, so take the SERIRQs out and continue. |
| 494 | */ |
| 495 | active_irqs &= ~LPC_HC_IRQ_SERIRQ_ALL; |
| 496 | } |
| 497 | |
| 498 | /* |
| 499 | * POWER8 ORs all irqs together (also with LPCHC internal interrupt |
| 500 | * sources) and outputs a single line that raises the PSI LPCHC irq |
| 501 | * which then latches an OPB IRQ status register that sends the irq |
| 502 | * to PSI. |
| 503 | * |
| 504 | * We don't honor the polarity register, it's pointless and unused |
| 505 | * anyway |
| 506 | */ |
| 507 | if (active_irqs) { |
| 508 | lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; |
| 509 | } else { |
| 510 | lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; |
| 511 | } |
| 512 | |
| 513 | /* Update OPB internal latch */ |
| 514 | lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; |
| 515 | |
| 516 | qemu_set_irq(lpc->psi_irq_lpchc, lpc->opb_irq_stat != 0); |
| 517 | } |
| 518 | |
| 519 | static void pnv_lpc_opb_noresponse(PnvLpcController *lpc) |
| 520 | { |
| 521 | lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SYNC_NORESP_ERR; |
| 522 | pnv_lpc_eval_irqs(lpc); |
| 523 | } |
| 524 | |
| 525 | static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) |
| 526 | { |
| 527 | PnvLpcController *lpc = opaque; |
| 528 | uint64_t val = 0xfffffffffffffffful; |
| 529 | |
| 530 | switch (addr) { |
| 531 | case LPC_HC_FW_SEG_IDSEL: |
| 532 | val = lpc->lpc_hc_fw_seg_idsel; |
| 533 | break; |
| 534 | case LPC_HC_FW_RD_ACC_SIZE: |
| 535 | val = lpc->lpc_hc_fw_rd_acc_size; |
| 536 | break; |
| 537 | case LPC_HC_IRQSER_CTRL: |
| 538 | val = lpc->lpc_hc_irqser_ctrl; |
| 539 | break; |
| 540 | case LPC_HC_IRQMASK: |
| 541 | val = lpc->lpc_hc_irqmask; |
| 542 | break; |
| 543 | case LPC_HC_IRQSTAT: |
| 544 | val = lpc->lpc_hc_irqstat; |
| 545 | break; |
| 546 | case LPC_HC_ERROR_ADDRESS: |
| 547 | val = lpc->lpc_hc_error_addr; |
| 548 | break; |
| 549 | default: |
| 550 | qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" |
| 551 | HWADDR_PRIx "\n", addr); |
| 552 | } |
| 553 | return val; |
| 554 | } |
| 555 | |
| 556 | static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, |
| 557 | unsigned size) |
| 558 | { |
| 559 | PnvLpcController *lpc = opaque; |
| 560 | |
| 561 | /* XXX Filter out reserved bits */ |
| 562 | |
| 563 | switch (addr) { |
| 564 | case LPC_HC_FW_SEG_IDSEL: |
| 565 | /* |
| 566 | * ISA FW "devices" are modeled as 16x256MB windows into a |
| 567 | * 4GB LPC FW address space. |
| 568 | */ |
| 569 | val &= 0xf; /* Selects device 0-15 */ |
| 570 | lpc->lpc_hc_fw_seg_idsel = val; |
| 571 | memory_region_set_alias_offset(&lpc->opb_isa_fw, val * LPC_FW_OPB_SIZE); |
| 572 | break; |
| 573 | case LPC_HC_FW_RD_ACC_SIZE: |
| 574 | lpc->lpc_hc_fw_rd_acc_size = val; |
| 575 | break; |
| 576 | case LPC_HC_IRQSER_CTRL: |
| 577 | lpc->lpc_hc_irqser_ctrl = val; |
| 578 | pnv_lpc_eval_irqs(lpc); |
| 579 | break; |
| 580 | case LPC_HC_IRQMASK: |
| 581 | lpc->lpc_hc_irqmask = val; |
| 582 | pnv_lpc_eval_irqs(lpc); |
| 583 | break; |
| 584 | case LPC_HC_IRQSTAT: |
| 585 | /* |
| 586 | * This register is write-to-clear for the IRQSER (LPC device IRQ) |
| 587 | * status. However if the device has not de-asserted its interrupt |
| 588 | * that will just raise this IRQ status bit again. Model this by |
| 589 | * keeping track of the inputs and only clearing if the inputs are |
| 590 | * deasserted. |
| 591 | */ |
| 592 | lpc->lpc_hc_irqstat &= ~(val & ~lpc->lpc_hc_irq_inputs); |
| 593 | pnv_lpc_eval_irqs(lpc); |
| 594 | break; |
| 595 | case LPC_HC_ERROR_ADDRESS: |
| 596 | break; |
| 597 | default: |
| 598 | qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" |
| 599 | HWADDR_PRIx "\n", addr); |
| 600 | } |
| 601 | } |
| 602 | |
| 603 | static const MemoryRegionOps lpc_hc_ops = { |
| 604 | .read = lpc_hc_read, |
| 605 | .write = lpc_hc_write, |
| 606 | .endianness = DEVICE_BIG_ENDIAN, |
| 607 | .valid = { |
| 608 | .min_access_size = 4, |
| 609 | .max_access_size = 4, |
| 610 | }, |
| 611 | .impl = { |
| 612 | .min_access_size = 4, |
| 613 | .max_access_size = 4, |
| 614 | }, |
| 615 | }; |
| 616 | |
| 617 | static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) |
| 618 | { |
| 619 | PnvLpcController *lpc = opaque; |
| 620 | uint64_t val = 0xfffffffffffffffful; |
| 621 | |
| 622 | switch (addr) { |
| 623 | case OPB_MASTER_LS_ROUTE0: |
| 624 | val = lpc->opb_irq_route0; |
| 625 | break; |
| 626 | case OPB_MASTER_LS_ROUTE1: |
| 627 | val = lpc->opb_irq_route1; |
| 628 | break; |
| 629 | case OPB_MASTER_LS_IRQ_STAT: |
| 630 | val = lpc->opb_irq_stat; |
| 631 | break; |
| 632 | case OPB_MASTER_LS_IRQ_MASK: |
| 633 | val = lpc->opb_irq_mask; |
| 634 | break; |
| 635 | case OPB_MASTER_LS_IRQ_POL: |
| 636 | val = lpc->opb_irq_pol; |
| 637 | break; |
| 638 | case OPB_MASTER_LS_IRQ_INPUT: |
| 639 | val = lpc->opb_irq_input; |
| 640 | break; |
| 641 | default: |
| 642 | qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%" |
| 643 | HWADDR_PRIx "\n", addr); |
| 644 | } |
| 645 | |
| 646 | return val; |
| 647 | } |
| 648 | |
| 649 | static void opb_master_write(void *opaque, hwaddr addr, |
| 650 | uint64_t val, unsigned size) |
| 651 | { |
| 652 | PnvLpcController *lpc = opaque; |
| 653 | |
| 654 | switch (addr) { |
| 655 | case OPB_MASTER_LS_ROUTE0: |
| 656 | lpc->opb_irq_route0 = val; |
| 657 | pnv_lpc_eval_serirq_routes(lpc); |
| 658 | pnv_lpc_eval_irqs(lpc); |
| 659 | break; |
| 660 | case OPB_MASTER_LS_ROUTE1: |
| 661 | lpc->opb_irq_route1 = val; |
| 662 | pnv_lpc_eval_serirq_routes(lpc); |
| 663 | pnv_lpc_eval_irqs(lpc); |
| 664 | break; |
| 665 | case OPB_MASTER_LS_IRQ_STAT: |
| 666 | lpc->opb_irq_stat &= ~val; |
| 667 | pnv_lpc_eval_irqs(lpc); |
| 668 | break; |
| 669 | case OPB_MASTER_LS_IRQ_MASK: |
| 670 | lpc->opb_irq_mask = val; |
| 671 | pnv_lpc_eval_irqs(lpc); |
| 672 | break; |
| 673 | case OPB_MASTER_LS_IRQ_POL: |
| 674 | lpc->opb_irq_pol = val; |
| 675 | pnv_lpc_eval_irqs(lpc); |
| 676 | break; |
| 677 | case OPB_MASTER_LS_IRQ_INPUT: |
| 678 | /* Read only */ |
| 679 | break; |
| 680 | default: |
| 681 | qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%" |
| 682 | HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | static const MemoryRegionOps opb_master_ops = { |
| 687 | .read = opb_master_read, |
| 688 | .write = opb_master_write, |
| 689 | .endianness = DEVICE_BIG_ENDIAN, |
| 690 | .valid = { |
| 691 | .min_access_size = 4, |
| 692 | .max_access_size = 4, |
| 693 | }, |
| 694 | .impl = { |
| 695 | .min_access_size = 4, |
| 696 | .max_access_size = 4, |
| 697 | }, |
| 698 | }; |
| 699 | |
| 700 | static int vmstate_pnv_lpc_post_load(void *opaque, int version_id) |
| 701 | { |
| 702 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 703 | |
| 704 | memory_region_set_alias_offset(&lpc->opb_isa_fw, |
| 705 | lpc->lpc_hc_fw_seg_idsel * LPC_FW_OPB_SIZE); |
| 706 | pnv_lpc_eval_serirq_routes(lpc); |
| 707 | |
| 708 | pnv_lpc_eval_irqs(lpc); |
| 709 | return 0; |
| 710 | } |
| 711 | |
| 712 | static const VMStateDescription vmstate_pnv_lpc = { |
| 713 | .name = TYPE_PNV_LPC, |
| 714 | .version_id = 1, |
| 715 | .minimum_version_id = 1, |
| 716 | .post_load = vmstate_pnv_lpc_post_load, |
| 717 | .fields = (const VMStateField[]) { |
| 718 | VMSTATE_UINT64(eccb_stat_reg, PnvLpcController), |
| 719 | VMSTATE_UINT32(eccb_data_reg, PnvLpcController), |
| 720 | VMSTATE_UINT32(opb_irq_route0, PnvLpcController), |
| 721 | VMSTATE_UINT32(opb_irq_route1, PnvLpcController), |
| 722 | VMSTATE_UINT32(opb_irq_stat, PnvLpcController), |
| 723 | VMSTATE_UINT32(opb_irq_mask, PnvLpcController), |
| 724 | VMSTATE_UINT32(opb_irq_pol, PnvLpcController), |
| 725 | VMSTATE_UINT32(opb_irq_input, PnvLpcController), |
| 726 | VMSTATE_UINT32(lpc_hc_irq_inputs, PnvLpcController), |
| 727 | VMSTATE_UINT32(lpc_hc_fw_seg_idsel, PnvLpcController), |
| 728 | VMSTATE_UINT32(lpc_hc_irqser_ctrl, PnvLpcController), |
| 729 | VMSTATE_UINT32(lpc_hc_irqmask, PnvLpcController), |
| 730 | VMSTATE_UINT32(lpc_hc_irqstat, PnvLpcController), |
| 731 | VMSTATE_UINT32(lpc_hc_error_addr, PnvLpcController), |
| 732 | VMSTATE_UINT32(lpc_hc_fw_rd_acc_size, PnvLpcController), |
| 733 | VMSTATE_END_OF_LIST() |
| 734 | } |
| 735 | }; |
| 736 | |
| 737 | static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp) |
| 738 | { |
| 739 | PnvLpcController *lpc = PNV_LPC(dev); |
| 740 | PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev); |
| 741 | Error *local_err = NULL; |
| 742 | |
| 743 | plc->parent_realize(dev, &local_err); |
| 744 | if (local_err) { |
| 745 | error_propagate(errp, local_err); |
| 746 | return; |
| 747 | } |
| 748 | |
| 749 | /* P8 uses a XSCOM region for LPC registers */ |
| 750 | pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc), |
| 751 | &pnv_lpc_xscom_ops, lpc, "xscom-lpc", |
| 752 | PNV_XSCOM_LPC_SIZE); |
| 753 | } |
| 754 | |
| 755 | static void pnv_lpc_power8_class_init(ObjectClass *klass, const void *data) |
| 756 | { |
| 757 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 758 | PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); |
| 759 | PnvLpcClass *plc = PNV_LPC_CLASS(klass); |
| 760 | |
| 761 | dc->desc = "PowerNV LPC Controller POWER8"; |
| 762 | dc->vmsd = &vmstate_pnv_lpc; |
| 763 | |
| 764 | xdc->dt_xscom = pnv_lpc_dt_xscom; |
| 765 | |
| 766 | device_class_set_parent_realize(dc, pnv_lpc_power8_realize, |
| 767 | &plc->parent_realize); |
| 768 | } |
| 769 | |
| 770 | static const TypeInfo pnv_lpc_power8_info = { |
| 771 | .name = TYPE_PNV8_LPC, |
| 772 | .parent = TYPE_PNV_LPC, |
| 773 | .class_init = pnv_lpc_power8_class_init, |
| 774 | .interfaces = (const InterfaceInfo[]) { |
| 775 | { TYPE_PNV_XSCOM_INTERFACE }, |
| 776 | { } |
| 777 | } |
| 778 | }; |
| 779 | |
| 780 | static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp) |
| 781 | { |
| 782 | PnvLpcController *lpc = PNV_LPC(dev); |
| 783 | PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev); |
| 784 | Error *local_err = NULL; |
| 785 | |
| 786 | object_property_set_bool(OBJECT(lpc), "psi-serirq", true, &error_abort); |
| 787 | |
| 788 | plc->parent_realize(dev, &local_err); |
| 789 | if (local_err) { |
| 790 | error_propagate(errp, local_err); |
| 791 | return; |
| 792 | } |
| 793 | |
| 794 | /* P9 uses a MMIO region */ |
| 795 | memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, |
| 796 | lpc, "lpcm", PNV9_LPCM_SIZE); |
| 797 | |
| 798 | /* P9 LPC routes ISA irqs to 4 PSI SERIRQ lines */ |
| 799 | qdev_init_gpio_out_named(dev, lpc->psi_irq_serirq, "SERIRQ", 4); |
| 800 | } |
| 801 | |
| 802 | static void pnv_lpc_power9_class_init(ObjectClass *klass, const void *data) |
| 803 | { |
| 804 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 805 | PnvLpcClass *plc = PNV_LPC_CLASS(klass); |
| 806 | |
| 807 | dc->desc = "PowerNV LPC Controller POWER9"; |
| 808 | dc->vmsd = &vmstate_pnv_lpc; |
| 809 | |
| 810 | device_class_set_parent_realize(dc, pnv_lpc_power9_realize, |
| 811 | &plc->parent_realize); |
| 812 | } |
| 813 | |
| 814 | static const TypeInfo pnv_lpc_power9_info = { |
| 815 | .name = TYPE_PNV9_LPC, |
| 816 | .parent = TYPE_PNV_LPC, |
| 817 | .class_init = pnv_lpc_power9_class_init, |
| 818 | }; |
| 819 | |
| 820 | static void pnv_lpc_power10_class_init(ObjectClass *klass, const void *data) |
| 821 | { |
| 822 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 823 | |
| 824 | dc->desc = "PowerNV LPC Controller POWER10"; |
| 825 | dc->vmsd = &vmstate_pnv_lpc; |
| 826 | } |
| 827 | |
| 828 | static const TypeInfo pnv_lpc_power10_info = { |
| 829 | .name = TYPE_PNV10_LPC, |
| 830 | .parent = TYPE_PNV9_LPC, |
| 831 | .class_init = pnv_lpc_power10_class_init, |
| 832 | }; |
| 833 | |
| 834 | static void pnv_lpc_realize(DeviceState *dev, Error **errp) |
| 835 | { |
| 836 | PnvLpcController *lpc = PNV_LPC(dev); |
| 837 | |
| 838 | /* Reg inits */ |
| 839 | lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; |
| 840 | |
| 841 | /* Create address space and backing MR for the OPB bus */ |
| 842 | memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); |
| 843 | address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); |
| 844 | |
| 845 | /* |
| 846 | * Create ISA IO, Mem, and FW space regions which are the root of |
| 847 | * the ISA bus (ie, ISA address spaces). |
| 848 | */ |
| 849 | memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); |
| 850 | memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); |
| 851 | memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE); |
| 852 | |
| 853 | /* Create windows from the OPB space to the ISA space */ |
| 854 | memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", |
| 855 | &lpc->isa_io, 0, LPC_IO_OPB_SIZE); |
| 856 | memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, |
| 857 | &lpc->opb_isa_io); |
| 858 | memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", |
| 859 | &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); |
| 860 | memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, |
| 861 | &lpc->opb_isa_mem); |
| 862 | memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", |
| 863 | &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); |
| 864 | memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, |
| 865 | &lpc->opb_isa_fw); |
| 866 | |
| 867 | /* Create MMIO regions for LPC HC and OPB registers */ |
| 868 | memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, |
| 869 | lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); |
| 870 | lpc->opb_master_regs.disable_reentrancy_guard = true; |
| 871 | memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, |
| 872 | &lpc->opb_master_regs); |
| 873 | memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, |
| 874 | "lpc-hc", LPC_HC_REGS_OPB_SIZE); |
| 875 | /* xscom writes to lpc-hc. As such mark lpc-hc re-entrancy safe */ |
| 876 | lpc->lpc_hc_regs.disable_reentrancy_guard = true; |
| 877 | memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, |
| 878 | &lpc->lpc_hc_regs); |
| 879 | |
| 880 | qdev_init_gpio_out_named(dev, &lpc->psi_irq_lpchc, "LPCHC", 1); |
| 881 | } |
| 882 | |
| 883 | static const Property pnv_lpc_properties[] = { |
| 884 | DEFINE_PROP_BOOL("psi-serirq", PnvLpcController, psi_has_serirq, false), |
| 885 | }; |
| 886 | |
| 887 | static void pnv_lpc_class_init(ObjectClass *klass, const void *data) |
| 888 | { |
| 889 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 890 | |
| 891 | device_class_set_props(dc, pnv_lpc_properties); |
| 892 | dc->realize = pnv_lpc_realize; |
| 893 | dc->desc = "PowerNV LPC Controller"; |
| 894 | dc->user_creatable = false; |
| 895 | } |
| 896 | |
| 897 | static const TypeInfo pnv_lpc_info = { |
| 898 | .name = TYPE_PNV_LPC, |
| 899 | .parent = TYPE_DEVICE, |
| 900 | .instance_size = sizeof(PnvLpcController), |
| 901 | .class_init = pnv_lpc_class_init, |
| 902 | .class_size = sizeof(PnvLpcClass), |
| 903 | .abstract = true, |
| 904 | }; |
| 905 | |
| 906 | static void pnv_lpc_register_types(void) |
| 907 | { |
| 908 | type_register_static(&pnv_lpc_info); |
| 909 | type_register_static(&pnv_lpc_power8_info); |
| 910 | type_register_static(&pnv_lpc_power9_info); |
| 911 | type_register_static(&pnv_lpc_power10_info); |
| 912 | } |
| 913 | |
| 914 | type_init(pnv_lpc_register_types) |
| 915 | |
| 916 | /* If we don't use the built-in LPC interrupt deserializer, we need |
| 917 | * to provide a set of qirqs for the ISA bus or things will go bad. |
| 918 | * |
| 919 | * Most machines using pre-Naples chips (without said deserializer) |
| 920 | * have a CPLD that will collect the SerIRQ and shoot them as a |
| 921 | * single level interrupt to the P8 chip. So let's setup a hook |
| 922 | * for doing just that. |
| 923 | */ |
| 924 | static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) |
| 925 | { |
| 926 | PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); |
| 927 | uint32_t old_state = pnv->cpld_irqstate; |
| 928 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 929 | |
| 930 | if (level) { |
| 931 | pnv->cpld_irqstate |= 1u << n; |
| 932 | } else { |
| 933 | pnv->cpld_irqstate &= ~(1u << n); |
| 934 | } |
| 935 | |
| 936 | if (pnv->cpld_irqstate != old_state) { |
| 937 | qemu_set_irq(lpc->psi_irq_lpchc, pnv->cpld_irqstate != 0); |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) |
| 942 | { |
| 943 | PnvLpcController *lpc = PNV_LPC(opaque); |
| 944 | uint32_t irq_bit = LPC_HC_IRQ_SERIRQ0 >> n; |
| 945 | |
| 946 | if (level) { |
| 947 | lpc->lpc_hc_irq_inputs |= irq_bit; |
| 948 | |
| 949 | /* |
| 950 | * The LPC HC in Naples and later latches LPC IRQ into a bit field in |
| 951 | * the IRQSTAT register, and that drives the PSI IRQ to the IC. |
| 952 | * Software clears this bit manually (see LPC_HC_IRQSTAT handler). |
| 953 | */ |
| 954 | lpc->lpc_hc_irqstat |= irq_bit; |
| 955 | pnv_lpc_eval_irqs(lpc); |
| 956 | } else { |
| 957 | lpc->lpc_hc_irq_inputs &= ~irq_bit; |
| 958 | |
| 959 | /* POWER9 adds an auto-clear mode that clears IRQSTAT bits on EOI */ |
| 960 | if (lpc->psi_has_serirq && |
| 961 | (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_AUTO_CLEAR)) { |
| 962 | lpc->lpc_hc_irqstat &= ~irq_bit; |
| 963 | pnv_lpc_eval_irqs(lpc); |
| 964 | } |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp) |
| 969 | { |
| 970 | Error *local_err = NULL; |
| 971 | ISABus *isa_bus; |
| 972 | qemu_irq *irqs; |
| 973 | qemu_irq_handler handler; |
| 974 | |
| 975 | /* let isa_bus_new() create its own bridge on SysBus otherwise |
| 976 | * devices specified on the command line won't find the bus and |
| 977 | * will fail to create. |
| 978 | */ |
| 979 | isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err); |
| 980 | if (local_err) { |
| 981 | error_propagate(errp, local_err); |
| 982 | return NULL; |
| 983 | } |
| 984 | |
| 985 | /* Not all variants have a working serial irq decoder. If not, |
| 986 | * handling of LPC interrupts becomes a platform issue (some |
| 987 | * platforms have a CPLD to do it). |
| 988 | */ |
| 989 | if (use_cpld) { |
| 990 | handler = pnv_lpc_isa_irq_handler_cpld; |
| 991 | } else { |
| 992 | handler = pnv_lpc_isa_irq_handler; |
| 993 | } |
| 994 | |
| 995 | /* POWER has a 17th irq, QEMU only implements the 16 regular device irqs */ |
| 996 | irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); |
| 997 | |
| 998 | isa_bus_register_input_irqs(isa_bus, irqs); |
| 999 | |
| 1000 | return isa_bus; |
| 1001 | } |