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1 /*
2 * QEMU PowerPC PowerNV XSCOM bus
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "system/hw_accel.h"
24 #include "target/ppc/cpu.h"
25 #include "hw/core/sysbus.h"
26
27 #include "hw/ppc/fdt.h"
28 #include "hw/ppc/pnv.h"
29 #include "hw/ppc/pnv_chip.h"
30 #include "hw/ppc/pnv_xscom.h"
31
32 #include <libfdt.h>
33
34 /* PRD registers */
35 #define PRD_P8_IPOLL_REG_MASK 0x01020013
36 #define PRD_P8_IPOLL_REG_STATUS 0x01020014
37 #define PRD_P9_IPOLL_REG_MASK 0x000F0033
38 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034
39
40 static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
41 {
42 /*
43 * TODO: When the read/write comes from the monitor, NULL is
44 * passed for the cpu, and no CPU completion is generated.
45 */
46 if (cs) {
47 /*
48 * TODO: Need a CPU helper to set HMER, also handle generation
49 * of HMIs
50 */
51 cpu_synchronize_state(cs);
52 cpu_env(cs)->spr[SPR_HMER] |= hmer_bits;
53 }
54 }
55
56 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
57 {
58 return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr);
59 }
60
61 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
62 {
63 switch (pcba) {
64 case 0x10005: /* SECURITY SWITCH */
65 return 0;
66 case 0xf000f:
67 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
68 case 0x18002: /* ECID2 */
69 return 0;
70
71 case 0x1010c00: /* PIBAM FIR */
72 case 0x1010c03: /* PIBAM FIR MASK */
73
74 /* PRD registers */
75 case PRD_P8_IPOLL_REG_MASK:
76 case PRD_P8_IPOLL_REG_STATUS:
77 case PRD_P9_IPOLL_REG_MASK:
78 case PRD_P9_IPOLL_REG_STATUS:
79
80 /* P8 xscom reset */
81 case 0x2020007: /* ADU stuff, log register */
82 case 0x2020009: /* ADU stuff, error register */
83 case 0x202000f: /* ADU stuff, receive status register*/
84 return 0;
85 case 0x2013f01: /* PBA stuff */
86 case 0x2013f05: /* PBA stuff */
87 return 0;
88 case 0x2013028: /* CAPP stuff */
89 case 0x201302a: /* CAPP stuff */
90 case 0x2013801: /* CAPP stuff */
91 case 0x2013802: /* CAPP stuff */
92
93 /* P9 CAPP regs */
94 case 0x2010841:
95 case 0x2010842:
96 case 0x201082a:
97 case 0x2010828:
98 case 0x4010841:
99 case 0x4010842:
100 case 0x401082a:
101 case 0x4010828:
102 return 0;
103 default:
104 return -1;
105 }
106 }
107
108 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
109 {
110 /* We ignore writes to these */
111 switch (pcba) {
112 case 0xf000f: /* chip id is RO */
113 case 0x1010c00: /* PIBAM FIR */
114 case 0x1010c01: /* PIBAM FIR */
115 case 0x1010c02: /* PIBAM FIR */
116 case 0x1010c03: /* PIBAM FIR MASK */
117 case 0x1010c04: /* PIBAM FIR MASK */
118 case 0x1010c05: /* PIBAM FIR MASK */
119
120 /* P8 xscom reset */
121 case 0x2020007: /* ADU stuff, log register */
122 case 0x2020009: /* ADU stuff, error register */
123 case 0x202000f: /* ADU stuff, receive status register*/
124
125 case 0x2013028: /* CAPP stuff */
126 case 0x201302a: /* CAPP stuff */
127 case 0x2013801: /* CAPP stuff */
128 case 0x2013802: /* CAPP stuff */
129
130 /* P9 CAPP regs */
131 case 0x2010841:
132 case 0x2010842:
133 case 0x201082a:
134 case 0x2010828:
135 case 0x4010841:
136 case 0x4010842:
137 case 0x401082a:
138 case 0x4010828:
139
140 /* P8 PRD registers */
141 case PRD_P8_IPOLL_REG_MASK:
142 case PRD_P8_IPOLL_REG_STATUS:
143 case PRD_P9_IPOLL_REG_MASK:
144 case PRD_P9_IPOLL_REG_STATUS:
145 return true;
146 default:
147 return false;
148 }
149 }
150
151 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
152 {
153 PnvChip *chip = opaque;
154 uint32_t pcba = pnv_xscom_pcba(chip, addr);
155 uint64_t val = 0;
156 MemTxResult result;
157
158 /* Handle some SCOMs here before dispatch */
159 val = xscom_read_default(chip, pcba);
160 if (val != -1) {
161 goto complete;
162 }
163
164 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
165 MEMTXATTRS_UNSPECIFIED, &result);
166 if (result != MEMTX_OK) {
167 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
168 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
169 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
170 return 0;
171 }
172
173 complete:
174 xscom_complete(current_cpu, HMER_XSCOM_DONE);
175 return val;
176 }
177
178 static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
179 unsigned width)
180 {
181 PnvChip *chip = opaque;
182 uint32_t pcba = pnv_xscom_pcba(chip, addr);
183 MemTxResult result;
184
185 /* Handle some SCOMs here before dispatch */
186 if (xscom_write_default(chip, pcba, val)) {
187 goto complete;
188 }
189
190 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
191 MEMTXATTRS_UNSPECIFIED, &result);
192 if (result != MEMTX_OK) {
193 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
194 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
195 addr, pcba, val);
196 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
197 return;
198 }
199
200 complete:
201 xscom_complete(current_cpu, HMER_XSCOM_DONE);
202 }
203
204 const MemoryRegionOps pnv_xscom_ops = {
205 .read = xscom_read,
206 .write = xscom_write,
207 .valid.min_access_size = 8,
208 .valid.max_access_size = 8,
209 .impl.min_access_size = 8,
210 .impl.max_access_size = 8,
211 .endianness = DEVICE_BIG_ENDIAN,
212 };
213
214 void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr)
215 {
216 char *name;
217
218 name = g_strdup_printf("xscom-%x", chip->chip_id);
219 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
220 chip, name, size);
221 memory_region_add_subregion(get_system_memory(), addr, &chip->xscom_mmio);
222
223 memory_region_init(&chip->xscom, OBJECT(chip), name, size);
224 address_space_init(&chip->xscom_as, &chip->xscom, name);
225 g_free(name);
226 }
227
228 static const TypeInfo pnv_xscom_interface_info = {
229 .name = TYPE_PNV_XSCOM_INTERFACE,
230 .parent = TYPE_INTERFACE,
231 .class_size = sizeof(PnvXScomInterfaceClass),
232 };
233
234 static void pnv_xscom_register_types(void)
235 {
236 type_register_static(&pnv_xscom_interface_info);
237 }
238
239 type_init(pnv_xscom_register_types)
240
241 typedef struct ForeachPopulateArgs {
242 void *fdt;
243 int xscom_offset;
244 } ForeachPopulateArgs;
245
246 static int xscom_dt_child(Object *child, void *opaque)
247 {
248 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
249 ForeachPopulateArgs *args = opaque;
250 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
251 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
252
253 /*
254 * Only "realized" devices should be configured in the DT
255 */
256 if (xc->dt_xscom && qdev_is_realized(DEVICE(child))) {
257 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
258 }
259 }
260 return 0;
261 }
262
263 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
264 uint64_t xscom_base, uint64_t xscom_size,
265 const char *compat, int compat_size)
266 {
267 uint64_t reg[] = { xscom_base, xscom_size };
268 int xscom_offset;
269 ForeachPopulateArgs args;
270 char *name;
271
272 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
273 xscom_offset = fdt_add_subnode(fdt, root_offset, name);
274 _FDT(xscom_offset);
275 g_free(name);
276 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
277 /*
278 * On P10, the xscom bus id has been deprecated and the chip id is
279 * calculated from the "Primary topology table index". See skiboot.
280 */
281 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,primary-topology-index",
282 chip->chip_id)));
283 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
284 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
285 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
286 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
287 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
288 if (chip->chip_id == 0) {
289 _FDT((fdt_setprop(fdt, xscom_offset, "primary", NULL, 0)));
290 }
291
292 args.fdt = fdt;
293 args.xscom_offset = xscom_offset;
294
295 /*
296 * Loop on the whole object hierarchy to catch all
297 * PnvXScomInterface objects which can lie a bit deeper than the
298 * first layer.
299 */
300 object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
301 return 0;
302 }
303
304 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
305 {
306 memory_region_add_subregion(&chip->xscom, offset << 3, mr);
307 }
308
309 void pnv_xscom_region_init(MemoryRegion *mr,
310 Object *owner,
311 const MemoryRegionOps *ops,
312 void *opaque,
313 const char *name,
314 uint64_t size)
315 {
316 memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
317 }