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1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/core/irq.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc_e500.h"
29 #include "qemu/timer.h"
30 #include "exec/cpu-interrupt.h"
31 #include "system/cpus.h"
32 #include "qemu/log.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/error-report.h"
35 #include "system/kvm.h"
36 #include "system/replay.h"
37 #include "system/runstate.h"
38 #include "kvm_ppc.h"
39 #include "migration/vmstate.h"
40 #include "trace.h"
41
42 static void cpu_ppc_tb_stop (CPUPPCState *env);
43 static void cpu_ppc_tb_start (CPUPPCState *env);
44
45 void ppc_set_irq(PowerPCCPU *cpu, int irq, int level)
46 {
47 CPUPPCState *env = &cpu->env;
48 unsigned int old_pending;
49
50 /* We may already have the BQL if coming from the reset path */
51 BQL_LOCK_GUARD();
52
53 old_pending = env->pending_interrupts;
54
55 if (level) {
56 env->pending_interrupts |= irq;
57 } else {
58 env->pending_interrupts &= ~irq;
59 }
60
61 if (old_pending != env->pending_interrupts) {
62 ppc_maybe_interrupt(env);
63 if (kvm_enabled()) {
64 kvmppc_set_interrupt(cpu, irq, level);
65 }
66 }
67
68 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts,
69 CPU(cpu)->interrupt_request);
70 }
71
72 /* PowerPC 6xx / 7xx internal IRQ controller */
73 static void ppc6xx_set_irq(void *opaque, int pin, int level)
74 {
75 PowerPCCPU *cpu = opaque;
76 CPUPPCState *env = &cpu->env;
77 int cur_level;
78
79 trace_ppc_irq_set(env, pin, level);
80
81 cur_level = (env->irq_input_state >> pin) & 1;
82 /* Don't generate spurious events */
83 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
84 CPUState *cs = CPU(cpu);
85
86 switch (pin) {
87 case PPC6xx_INPUT_TBEN:
88 /* Level sensitive - active high */
89 trace_ppc_irq_set_state("time base", level);
90 if (level) {
91 cpu_ppc_tb_start(env);
92 } else {
93 cpu_ppc_tb_stop(env);
94 }
95 break;
96 case PPC6xx_INPUT_INT:
97 /* Level sensitive - active high */
98 trace_ppc_irq_set_state("external IRQ", level);
99 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
100 break;
101 case PPC6xx_INPUT_SMI:
102 /* Level sensitive - active high */
103 trace_ppc_irq_set_state("SMI IRQ", level);
104 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
105 break;
106 case PPC6xx_INPUT_MCP:
107 /* Negative edge sensitive */
108 /* XXX: TODO: actual reaction may depends on HID0 status
109 * 603/604/740/750: check HID0[EMCP]
110 */
111 if (cur_level == 1 && level == 0) {
112 trace_ppc_irq_set_state("machine check", 1);
113 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
114 }
115 break;
116 case PPC6xx_INPUT_CKSTP_IN:
117 /* Level sensitive - active low */
118 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
119 /* XXX: Note that the only way to restart the CPU is to reset it */
120 if (level) {
121 trace_ppc_irq_cpu("stop");
122 cs->halted = 1;
123 }
124 break;
125 case PPC6xx_INPUT_HRESET:
126 /* Level sensitive - active low */
127 if (level) {
128 trace_ppc_irq_reset("CPU");
129 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
130 }
131 break;
132 case PPC6xx_INPUT_SRESET:
133 trace_ppc_irq_set_state("RESET IRQ", level);
134 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
135 break;
136 default:
137 g_assert_not_reached();
138 }
139 if (level)
140 env->irq_input_state |= 1 << pin;
141 else
142 env->irq_input_state &= ~(1 << pin);
143 }
144 }
145
146 void ppc6xx_irq_init(PowerPCCPU *cpu)
147 {
148 qdev_init_gpio_in(DEVICE(cpu), ppc6xx_set_irq, PPC6xx_INPUT_NB);
149 }
150
151 #if defined(TARGET_PPC64)
152 /* PowerPC 970 internal IRQ controller */
153 static void ppc970_set_irq(void *opaque, int pin, int level)
154 {
155 PowerPCCPU *cpu = opaque;
156 CPUPPCState *env = &cpu->env;
157 int cur_level;
158
159 trace_ppc_irq_set(env, pin, level);
160
161 cur_level = (env->irq_input_state >> pin) & 1;
162 /* Don't generate spurious events */
163 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
164 CPUState *cs = CPU(cpu);
165
166 switch (pin) {
167 case PPC970_INPUT_INT:
168 /* Level sensitive - active high */
169 trace_ppc_irq_set_state("external IRQ", level);
170 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
171 break;
172 case PPC970_INPUT_THINT:
173 /* Level sensitive - active high */
174 trace_ppc_irq_set_state("SMI IRQ", level);
175 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
176 break;
177 case PPC970_INPUT_MCP:
178 /* Negative edge sensitive */
179 /* XXX: TODO: actual reaction may depends on HID0 status
180 * 603/604/740/750: check HID0[EMCP]
181 */
182 if (cur_level == 1 && level == 0) {
183 trace_ppc_irq_set_state("machine check", 1);
184 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
185 }
186 break;
187 case PPC970_INPUT_CKSTP:
188 /* Level sensitive - active low */
189 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
190 if (level) {
191 trace_ppc_irq_cpu("stop");
192 cs->halted = 1;
193 cpu_exit(cs);
194 } else {
195 trace_ppc_irq_cpu("restart");
196 cs->halted = 0;
197 qemu_cpu_kick(cs);
198 }
199 break;
200 case PPC970_INPUT_HRESET:
201 /* Level sensitive - active low */
202 if (level) {
203 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
204 }
205 break;
206 case PPC970_INPUT_SRESET:
207 trace_ppc_irq_set_state("RESET IRQ", level);
208 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
209 break;
210 case PPC970_INPUT_TBEN:
211 trace_ppc_irq_set_state("TBEN IRQ", level);
212 /* XXX: TODO */
213 break;
214 default:
215 g_assert_not_reached();
216 }
217 if (level)
218 env->irq_input_state |= 1 << pin;
219 else
220 env->irq_input_state &= ~(1 << pin);
221 }
222 }
223
224 void ppc970_irq_init(PowerPCCPU *cpu)
225 {
226 qdev_init_gpio_in(DEVICE(cpu), ppc970_set_irq, PPC970_INPUT_NB);
227 }
228
229 /* POWER7 internal IRQ controller */
230 static void power7_set_irq(void *opaque, int pin, int level)
231 {
232 PowerPCCPU *cpu = opaque;
233
234 trace_ppc_irq_set(&cpu->env, pin, level);
235
236 switch (pin) {
237 case POWER7_INPUT_INT:
238 /* Level sensitive - active high */
239 trace_ppc_irq_set_state("external IRQ", level);
240 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
241 break;
242 default:
243 g_assert_not_reached();
244 }
245 }
246
247 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
248 {
249 qdev_init_gpio_in(DEVICE(cpu), power7_set_irq, POWER7_INPUT_NB);
250 }
251
252 /* POWER9 internal IRQ controller */
253 static void power9_set_irq(void *opaque, int pin, int level)
254 {
255 PowerPCCPU *cpu = opaque;
256
257 trace_ppc_irq_set(&cpu->env, pin, level);
258
259 switch (pin) {
260 case POWER9_INPUT_INT:
261 /* Level sensitive - active high */
262 trace_ppc_irq_set_state("external IRQ", level);
263 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
264 break;
265 case POWER9_INPUT_HINT:
266 /* Level sensitive - active high */
267 trace_ppc_irq_set_state("HV external IRQ", level);
268 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
269 break;
270 default:
271 g_assert_not_reached();
272 }
273 }
274
275 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
276 {
277 qdev_init_gpio_in(DEVICE(cpu), power9_set_irq, POWER9_INPUT_NB);
278 }
279 #endif /* defined(TARGET_PPC64) */
280
281 void ppc40x_core_reset(PowerPCCPU *cpu)
282 {
283 CPUPPCState *env = &cpu->env;
284 target_ulong dbsr;
285
286 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n");
287 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
288 dbsr = env->spr[SPR_40x_DBSR];
289 dbsr &= ~0x00000300;
290 dbsr |= 0x00000100;
291 env->spr[SPR_40x_DBSR] = dbsr;
292 }
293
294 void ppc40x_chip_reset(PowerPCCPU *cpu)
295 {
296 CPUPPCState *env = &cpu->env;
297 target_ulong dbsr;
298
299 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n");
300 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
301 /* XXX: TODO reset all internal peripherals */
302 dbsr = env->spr[SPR_40x_DBSR];
303 dbsr &= ~0x00000300;
304 dbsr |= 0x00000200;
305 env->spr[SPR_40x_DBSR] = dbsr;
306 }
307
308 void ppc40x_system_reset(PowerPCCPU *cpu)
309 {
310 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n");
311 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
312 }
313
314 void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
315 {
316 PowerPCCPU *cpu = env_archcpu(env);
317
318 bql_lock();
319
320 switch ((val >> 28) & 0x3) {
321 case 0x0:
322 /* No action */
323 break;
324 case 0x1:
325 /* Core reset */
326 ppc40x_core_reset(cpu);
327 break;
328 case 0x2:
329 /* Chip reset */
330 ppc40x_chip_reset(cpu);
331 break;
332 case 0x3:
333 /* System reset */
334 ppc40x_system_reset(cpu);
335 break;
336 }
337
338 bql_unlock();
339 }
340
341 /* PowerPC 40x internal IRQ controller */
342 static void ppc40x_set_irq(void *opaque, int pin, int level)
343 {
344 PowerPCCPU *cpu = opaque;
345 CPUPPCState *env = &cpu->env;
346 int cur_level;
347
348 trace_ppc_irq_set(env, pin, level);
349
350 cur_level = (env->irq_input_state >> pin) & 1;
351 /* Don't generate spurious events */
352 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
353 CPUState *cs = CPU(cpu);
354
355 switch (pin) {
356 case PPC40x_INPUT_RESET_SYS:
357 if (level) {
358 trace_ppc_irq_reset("system");
359 ppc40x_system_reset(cpu);
360 }
361 break;
362 case PPC40x_INPUT_RESET_CHIP:
363 if (level) {
364 trace_ppc_irq_reset("chip");
365 ppc40x_chip_reset(cpu);
366 }
367 break;
368 case PPC40x_INPUT_RESET_CORE:
369 /* XXX: TODO: update DBSR[MRR] */
370 if (level) {
371 trace_ppc_irq_reset("core");
372 ppc40x_core_reset(cpu);
373 }
374 break;
375 case PPC40x_INPUT_CINT:
376 /* Level sensitive - active high */
377 trace_ppc_irq_set_state("critical IRQ", level);
378 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
379 break;
380 case PPC40x_INPUT_INT:
381 /* Level sensitive - active high */
382 trace_ppc_irq_set_state("external IRQ", level);
383 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
384 break;
385 case PPC40x_INPUT_HALT:
386 /* Level sensitive - active low */
387 if (level) {
388 trace_ppc_irq_cpu("stop");
389 cs->halted = 1;
390 cpu_exit(cs);
391 } else {
392 trace_ppc_irq_cpu("restart");
393 cs->halted = 0;
394 qemu_cpu_kick(cs);
395 }
396 break;
397 case PPC40x_INPUT_DEBUG:
398 /* Level sensitive - active high */
399 trace_ppc_irq_set_state("debug pin", level);
400 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
401 break;
402 default:
403 g_assert_not_reached();
404 }
405 if (level)
406 env->irq_input_state |= 1 << pin;
407 else
408 env->irq_input_state &= ~(1 << pin);
409 }
410 }
411
412 void ppc40x_irq_init(PowerPCCPU *cpu)
413 {
414 qdev_init_gpio_in(DEVICE(cpu), ppc40x_set_irq, PPC40x_INPUT_NB);
415 }
416
417 /* PowerPC E500 internal IRQ controller */
418 static void ppce500_set_irq(void *opaque, int pin, int level)
419 {
420 PowerPCCPU *cpu = opaque;
421 CPUPPCState *env = &cpu->env;
422 int cur_level;
423
424 trace_ppc_irq_set(env, pin, level);
425
426 cur_level = (env->irq_input_state >> pin) & 1;
427 /* Don't generate spurious events */
428 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
429 switch (pin) {
430 case PPCE500_INPUT_MCK:
431 if (level) {
432 trace_ppc_irq_reset("system");
433 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
434 }
435 break;
436 case PPCE500_INPUT_RESET_CORE:
437 if (level) {
438 trace_ppc_irq_reset("core");
439 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
440 }
441 break;
442 case PPCE500_INPUT_CINT:
443 /* Level sensitive - active high */
444 trace_ppc_irq_set_state("critical IRQ", level);
445 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
446 break;
447 case PPCE500_INPUT_INT:
448 /* Level sensitive - active high */
449 trace_ppc_irq_set_state("core IRQ", level);
450 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
451 break;
452 case PPCE500_INPUT_DEBUG:
453 /* Level sensitive - active high */
454 trace_ppc_irq_set_state("debug pin", level);
455 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
456 break;
457 default:
458 g_assert_not_reached();
459 }
460 if (level)
461 env->irq_input_state |= 1 << pin;
462 else
463 env->irq_input_state &= ~(1 << pin);
464 }
465 }
466
467 void ppce500_irq_init(PowerPCCPU *cpu)
468 {
469 qdev_init_gpio_in(DEVICE(cpu), ppce500_set_irq, PPCE500_INPUT_NB);
470 }
471
472 /* Enable or Disable the E500 EPR capability */
473 void ppce500_set_mpic_proxy(bool enabled)
474 {
475 CPUState *cs;
476
477 CPU_FOREACH(cs) {
478 PowerPCCPU *cpu = POWERPC_CPU(cs);
479
480 cpu->env.mpic_proxy = enabled;
481 if (kvm_enabled()) {
482 kvmppc_set_mpic_proxy(cpu, enabled);
483 }
484 }
485 }
486
487 /*****************************************************************************/
488 /* PowerPC time base and decrementer emulation */
489
490 /*
491 * Conversion between QEMU_CLOCK_VIRTUAL ns and timebase (TB) ticks:
492 * TB ticks are arrived at by multiplying tb_freq then dividing by
493 * ns per second, and rounding down. TB ticks drive all clocks and
494 * timers in the target machine.
495 *
496 * Converting TB intervals to ns for the purpose of setting a
497 * QEMU_CLOCK_VIRTUAL timer should go the other way, but rounding
498 * up. Rounding down could cause the timer to fire before the TB
499 * value has been reached.
500 */
501 static uint64_t ns_to_tb(uint32_t freq, int64_t clock)
502 {
503 return muldiv64(clock, freq, NANOSECONDS_PER_SECOND);
504 }
505
506 /* virtual clock in TB ticks, not adjusted by TB offset */
507 static int64_t tb_to_ns_round_up(uint32_t freq, uint64_t tb)
508 {
509 return muldiv64_round_up(tb, NANOSECONDS_PER_SECOND, freq);
510 }
511
512 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
513 {
514 /* TB time in tb periods */
515 return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset;
516 }
517
518 int64_t cpu_ppc_load_tb_offset(CPUPPCState *env)
519 {
520 return env->tb_env->tb_offset;
521 }
522
523 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
524 {
525 ppc_tb_t *tb_env = env->tb_env;
526 uint64_t tb;
527
528 if (kvm_enabled()) {
529 return env->spr[SPR_TBL];
530 }
531
532 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
533 tb_env->tb_offset);
534 trace_ppc_tb_load(tb);
535
536 return tb;
537 }
538
539 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
540 {
541 ppc_tb_t *tb_env = env->tb_env;
542 uint64_t tb;
543
544 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
545 tb_env->tb_offset);
546 trace_ppc_tb_load(tb);
547
548 return tb >> 32;
549 }
550
551 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
552 {
553 if (kvm_enabled()) {
554 return env->spr[SPR_TBU];
555 }
556
557 return _cpu_ppc_load_tbu(env);
558 }
559
560 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
561 int64_t *tb_offsetp, uint64_t value)
562 {
563 *tb_offsetp = value - ns_to_tb(tb_env->tb_freq, vmclk);
564
565 trace_ppc_tb_store(value, *tb_offsetp);
566 }
567
568 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
569 {
570 ppc_tb_t *tb_env = env->tb_env;
571 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
572 uint64_t tb;
573
574 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
575 tb &= 0xFFFFFFFF00000000ULL;
576 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb | (uint64_t)value);
577 }
578
579 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
580 {
581 ppc_tb_t *tb_env = env->tb_env;
582 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
583 uint64_t tb;
584
585 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
586 tb &= 0x00000000FFFFFFFFULL;
587 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset,
588 ((uint64_t)value << 32) | tb);
589 }
590
591 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
592 {
593 _cpu_ppc_store_tbu(env, value);
594 }
595
596 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
597 {
598 ppc_tb_t *tb_env = env->tb_env;
599 uint64_t tb;
600
601 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
602 tb_env->atb_offset);
603 trace_ppc_tb_load(tb);
604
605 return tb;
606 }
607
608 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
609 {
610 ppc_tb_t *tb_env = env->tb_env;
611 uint64_t tb;
612
613 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
614 tb_env->atb_offset);
615 trace_ppc_tb_load(tb);
616
617 return tb >> 32;
618 }
619
620 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
621 {
622 ppc_tb_t *tb_env = env->tb_env;
623 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
624 uint64_t tb;
625
626 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset);
627 tb &= 0xFFFFFFFF00000000ULL;
628 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, tb | (uint64_t)value);
629 }
630
631 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
632 {
633 ppc_tb_t *tb_env = env->tb_env;
634 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
635 uint64_t tb;
636
637 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset);
638 tb &= 0x00000000FFFFFFFFULL;
639 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset,
640 ((uint64_t)value << 32) | tb);
641 }
642
643 void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset)
644 {
645 env->tb_env->tb_offset += offset;
646 }
647
648 void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset)
649 {
650 env->tb_env->tb_offset -= offset;
651 }
652
653 uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
654 {
655 ppc_tb_t *tb_env = env->tb_env;
656
657 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
658 tb_env->vtb_offset);
659 }
660
661 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
662 {
663 ppc_tb_t *tb_env = env->tb_env;
664
665 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
666 &tb_env->vtb_offset, value);
667 }
668
669 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
670 {
671 ppc_tb_t *tb_env = env->tb_env;
672 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
673 uint64_t tb;
674
675 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
676 tb &= 0xFFFFFFUL;
677 tb |= (value & ~0xFFFFFFUL);
678 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb);
679 }
680
681 static void cpu_ppc_tb_stop (CPUPPCState *env)
682 {
683 ppc_tb_t *tb_env = env->tb_env;
684 uint64_t tb, atb, vmclk;
685
686 /* If the time base is already frozen, do nothing */
687 if (tb_env->tb_freq != 0) {
688 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
689 /* Get the time base */
690 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
691 /* Get the alternate time base */
692 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
693 /* Store the time base value (ie compute the current offset) */
694 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
695 /* Store the alternate time base value (compute the current offset) */
696 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
697 /* Set the time base frequency to zero */
698 tb_env->tb_freq = 0;
699 /* Now, the time bases are frozen to tb_offset / atb_offset value */
700 }
701 }
702
703 static void cpu_ppc_tb_start (CPUPPCState *env)
704 {
705 ppc_tb_t *tb_env = env->tb_env;
706 uint64_t tb, atb, vmclk;
707
708 /* If the time base is not frozen, do nothing */
709 if (tb_env->tb_freq == 0) {
710 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
711 /* Get the time base from tb_offset */
712 tb = tb_env->tb_offset;
713 /* Get the alternate time base from atb_offset */
714 atb = tb_env->atb_offset;
715 /* Restore the tb frequency from the decrementer frequency */
716 tb_env->tb_freq = tb_env->decr_freq;
717 /* Store the time base value */
718 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
719 /* Store the alternate time base value */
720 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
721 }
722 }
723
724 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
725 {
726 ppc_tb_t *tb_env = env->tb_env;
727 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
728 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
729 }
730
731 static inline int64_t __cpu_ppc_load_decr(CPUPPCState *env, int64_t now,
732 uint64_t next)
733 {
734 ppc_tb_t *tb_env = env->tb_env;
735 uint64_t n;
736 int64_t decr;
737
738 n = ns_to_tb(tb_env->decr_freq, now);
739
740 /* BookE timers stop when reaching 0. */
741 if (next < n && tb_env->flags & PPC_TIMER_BOOKE) {
742 decr = 0;
743 } else {
744 decr = next - n;
745 }
746
747 trace_ppc_decr_load(decr);
748
749 return decr;
750 }
751
752 static target_ulong _cpu_ppc_load_decr(CPUPPCState *env, int64_t now)
753 {
754 ppc_tb_t *tb_env = env->tb_env;
755 uint64_t decr;
756
757 decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next);
758
759 /*
760 * If large decrementer is enabled then the decrementer is signed extended
761 * to 64 bits, otherwise it is a 32 bit value.
762 */
763 if (env->spr[SPR_LPCR] & LPCR_LD) {
764 PowerPCCPU *cpu = env_archcpu(env);
765 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
766 return sextract64(decr, 0, pcc->lrg_decr_bits);
767 }
768 return (uint32_t) decr;
769 }
770
771 target_ulong cpu_ppc_load_decr(CPUPPCState *env)
772 {
773 if (kvm_enabled()) {
774 return env->spr[SPR_DECR];
775 } else {
776 return _cpu_ppc_load_decr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
777 }
778 }
779
780 static target_ulong _cpu_ppc_load_hdecr(CPUPPCState *env, int64_t now)
781 {
782 PowerPCCPU *cpu = env_archcpu(env);
783 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
784 ppc_tb_t *tb_env = env->tb_env;
785 uint64_t hdecr;
786
787 hdecr = __cpu_ppc_load_decr(env, now, tb_env->hdecr_next);
788
789 /*
790 * If we have a large decrementer (POWER9 or later) then hdecr is sign
791 * extended to 64 bits, otherwise it is 32 bits.
792 */
793 if (pcc->lrg_decr_bits > 32) {
794 return sextract64(hdecr, 0, pcc->lrg_decr_bits);
795 }
796 return (uint32_t) hdecr;
797 }
798
799 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
800 {
801 return _cpu_ppc_load_hdecr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
802 }
803
804 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
805 {
806 ppc_tb_t *tb_env = env->tb_env;
807
808 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
809 tb_env->purr_offset);
810 }
811
812 /* When decrementer expires,
813 * all we need to do is generate or queue a CPU exception
814 */
815 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
816 {
817 /* Raise it */
818 trace_ppc_decr_excp("raise");
819 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
820 }
821
822 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
823 {
824 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
825 }
826
827 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
828 {
829 CPUPPCState *env = &cpu->env;
830
831 /* Raise it */
832 trace_ppc_decr_excp("raise HV");
833
834 /* The architecture specifies that we don't deliver HDEC
835 * interrupts in a PM state. Not only they don't cause a
836 * wakeup but they also get effectively discarded.
837 */
838 if (!env->resume_as_sreset) {
839 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
840 }
841 }
842
843 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
844 {
845 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
846 }
847
848 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, uint64_t *nextp,
849 QEMUTimer *timer,
850 void (*raise_excp)(void *),
851 void (*lower_excp)(PowerPCCPU *),
852 uint32_t flags, target_ulong decr,
853 target_ulong value, int nr_bits)
854 {
855 CPUPPCState *env = &cpu->env;
856 ppc_tb_t *tb_env = env->tb_env;
857 uint64_t next;
858 int64_t signed_value;
859 int64_t signed_decr;
860
861 /* Truncate value to decr_width and sign extend for simplicity */
862 value = extract64(value, 0, nr_bits);
863 decr = extract64(decr, 0, nr_bits);
864 signed_value = sextract64(value, 0, nr_bits);
865 signed_decr = sextract64(decr, 0, nr_bits);
866
867 trace_ppc_decr_store(nr_bits, decr, value);
868
869 /*
870 * Calculate the next decrementer event and set a timer.
871 * decr_next is in timebase units to keep rounding simple. Note it is
872 * not adjusted by tb_offset because if TB changes via tb_offset changing,
873 * decrementer does not change, so not directly comparable with TB.
874 */
875 next = ns_to_tb(tb_env->decr_freq, now) + value;
876 *nextp = next; /* nextp is in timebase units */
877
878 /*
879 * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt.
880 *
881 * On MSB level based DEC implementations the MSB always means the interrupt
882 * is pending, so raise it on those.
883 *
884 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
885 * an edge interrupt, so raise it here too.
886 */
887 if (((flags & PPC_DECR_UNDERFLOW_LEVEL) && signed_value < 0) ||
888 ((flags & PPC_DECR_UNDERFLOW_TRIGGERED) && signed_value < 0
889 && signed_decr >= 0)) {
890 (*raise_excp)(cpu);
891 return;
892 }
893
894 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
895 if (signed_value >= 0 && (flags & PPC_DECR_UNDERFLOW_LEVEL)) {
896 (*lower_excp)(cpu);
897 }
898
899 /* Adjust timer */
900 timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next));
901 }
902
903 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now,
904 target_ulong decr, target_ulong value,
905 int nr_bits)
906 {
907 ppc_tb_t *tb_env = cpu->env.tb_env;
908
909 __cpu_ppc_store_decr(cpu, now, &tb_env->decr_next, tb_env->decr_timer,
910 tb_env->decr_timer->cb, &cpu_ppc_decr_lower,
911 tb_env->flags, decr, value, nr_bits);
912 }
913
914 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
915 {
916 PowerPCCPU *cpu = env_archcpu(env);
917 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
918 int64_t now;
919 target_ulong decr;
920 int nr_bits = 32;
921
922 if (kvm_enabled()) {
923 /* KVM handles decrementer exceptions, we don't need our own timer */
924 return;
925 }
926
927 if (env->spr[SPR_LPCR] & LPCR_LD) {
928 nr_bits = pcc->lrg_decr_bits;
929 }
930
931 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
932 decr = _cpu_ppc_load_decr(env, now);
933 _cpu_ppc_store_decr(cpu, now, decr, value, nr_bits);
934 }
935
936 static void cpu_ppc_decr_cb(void *opaque)
937 {
938 PowerPCCPU *cpu = opaque;
939
940 cpu_ppc_decr_excp(cpu);
941 }
942
943 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, int64_t now,
944 target_ulong hdecr, target_ulong value,
945 int nr_bits)
946 {
947 ppc_tb_t *tb_env = cpu->env.tb_env;
948
949 if (tb_env->hdecr_timer != NULL) {
950 /* HDECR (Book3S 64bit) is edge-based, not level like DECR */
951 __cpu_ppc_store_decr(cpu, now, &tb_env->hdecr_next, tb_env->hdecr_timer,
952 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
953 PPC_DECR_UNDERFLOW_TRIGGERED,
954 hdecr, value, nr_bits);
955 }
956 }
957
958 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
959 {
960 PowerPCCPU *cpu = env_archcpu(env);
961 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
962 int64_t now;
963 target_ulong hdecr;
964
965 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
966 hdecr = _cpu_ppc_load_hdecr(env, now);
967 _cpu_ppc_store_hdecr(cpu, now, hdecr, value, pcc->lrg_decr_bits);
968 }
969
970 static void cpu_ppc_hdecr_cb(void *opaque)
971 {
972 PowerPCCPU *cpu = opaque;
973
974 cpu_ppc_hdecr_excp(cpu);
975 }
976
977 static void _cpu_ppc_store_purr(CPUPPCState *env, int64_t now, uint64_t value)
978 {
979 ppc_tb_t *tb_env = env->tb_env;
980
981 cpu_ppc_store_tb(tb_env, now, &tb_env->purr_offset, value);
982 }
983
984 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
985 {
986 _cpu_ppc_store_purr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), value);
987 }
988
989 static void timebase_save(PPCTimebase *tb)
990 {
991 uint64_t ticks = cpu_get_host_ticks();
992 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
993
994 if (!first_ppc_cpu->env.tb_env) {
995 error_report("No timebase object");
996 return;
997 }
998
999 if (replay_mode == REPLAY_MODE_NONE) {
1000 /* not used anymore, we keep it for compatibility */
1001 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
1002 } else {
1003 /* simpler for record-replay to avoid this event, compat not needed */
1004 tb->time_of_the_day_ns = 0;
1005 }
1006
1007 /*
1008 * tb_offset is only expected to be changed by QEMU so
1009 * there is no need to update it from KVM here
1010 */
1011 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
1012
1013 tb->runstate_paused =
1014 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM);
1015 }
1016
1017 static void timebase_load(PPCTimebase *tb)
1018 {
1019 CPUState *cpu;
1020 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1021 int64_t tb_off_adj, tb_off;
1022 unsigned long freq;
1023
1024 if (!first_ppc_cpu->env.tb_env) {
1025 error_report("No timebase object");
1026 return;
1027 }
1028
1029 freq = first_ppc_cpu->env.tb_env->tb_freq;
1030
1031 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
1032
1033 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
1034 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
1035 (tb_off_adj - tb_off) / freq);
1036
1037 /* Set new offset to all CPUs */
1038 CPU_FOREACH(cpu) {
1039 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
1040 pcpu->env.tb_env->tb_offset = tb_off_adj;
1041 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset);
1042 }
1043 }
1044
1045 void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
1046 RunState state)
1047 {
1048 PPCTimebase *tb = opaque;
1049
1050 if (running) {
1051 timebase_load(tb);
1052 } else {
1053 timebase_save(tb);
1054 }
1055 }
1056
1057 /*
1058 * When migrating a running guest, read the clock just
1059 * before migration, so that the guest clock counts
1060 * during the events between:
1061 *
1062 * * vm_stop()
1063 * *
1064 * * pre_save()
1065 *
1066 * This reduces clock difference on migration from 5s
1067 * to 0.1s (when max_downtime == 5s), because sending the
1068 * final pages of memory (which happens between vm_stop()
1069 * and pre_save()) takes max_downtime.
1070 */
1071 static int timebase_pre_save(void *opaque)
1072 {
1073 PPCTimebase *tb = opaque;
1074
1075 /* guest_timebase won't be overridden in case of paused guest or savevm */
1076 if (!tb->runstate_paused) {
1077 timebase_save(tb);
1078 }
1079
1080 return 0;
1081 }
1082
1083 const VMStateDescription vmstate_ppc_timebase = {
1084 .name = "timebase",
1085 .version_id = 1,
1086 .minimum_version_id = 1,
1087 .pre_save = timebase_pre_save,
1088 .fields = (const VMStateField []) {
1089 VMSTATE_UINT64(guest_timebase, PPCTimebase),
1090 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
1091 VMSTATE_END_OF_LIST()
1092 },
1093 };
1094
1095 /* Set up (once) timebase frequency (in Hz) */
1096 void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq)
1097 {
1098 PowerPCCPU *cpu = env_archcpu(env);
1099 ppc_tb_t *tb_env;
1100
1101 tb_env = g_new0(ppc_tb_t, 1);
1102 env->tb_env = tb_env;
1103 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1104 if (is_book3s_arch2x(env)) {
1105 /* All Book3S 64bit CPUs implement level based DEC logic */
1106 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1107 }
1108 /* Create new timer */
1109 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1110 &cpu_ppc_decr_cb, cpu);
1111 if (env->has_hv_mode && !cpu->vhyp) {
1112 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1113 &cpu_ppc_hdecr_cb, cpu);
1114 } else {
1115 tb_env->hdecr_timer = NULL;
1116 }
1117
1118 tb_env->tb_freq = freq;
1119 tb_env->decr_freq = freq;
1120 }
1121
1122 void cpu_ppc_tb_reset(CPUPPCState *env)
1123 {
1124 PowerPCCPU *cpu = env_archcpu(env);
1125 ppc_tb_t *tb_env = env->tb_env;
1126
1127 timer_del(tb_env->decr_timer);
1128 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
1129 tb_env->decr_next = 0;
1130 if (tb_env->hdecr_timer != NULL) {
1131 timer_del(tb_env->hdecr_timer);
1132 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
1133 tb_env->hdecr_next = 0;
1134 _cpu_ppc_store_hdecr(cpu, 0, 0, 0, 64);
1135 }
1136
1137 /*
1138 * There is a bug in Linux 2.4 kernels:
1139 * if a decrementer exception is pending when it enables msr_ee at startup,
1140 * it's not ready to handle it...
1141 *
1142 * On machine reset, this is called before icount is reset, so for
1143 * icount-mode, setting TB registers using now == qemu_clock_get_ns()
1144 * results in them being garbage after icount is reset. Use an
1145 * explicit now == 0 to get a consistent reset state.
1146 */
1147 _cpu_ppc_store_decr(cpu, 0, 0, -1, 64);
1148 _cpu_ppc_store_purr(env, 0, 0);
1149 }
1150
1151 void cpu_ppc_tb_free(CPUPPCState *env)
1152 {
1153 timer_free(env->tb_env->decr_timer);
1154 timer_free(env->tb_env->hdecr_timer);
1155 g_free(env->tb_env);
1156 }
1157
1158 /* cpu_ppc_hdecr_init may be used if the timer is not used by HDEC emulation */
1159 void cpu_ppc_hdecr_init(CPUPPCState *env)
1160 {
1161 PowerPCCPU *cpu = env_archcpu(env);
1162
1163 assert(env->tb_env->hdecr_timer == NULL);
1164
1165 env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1166 &cpu_ppc_hdecr_cb, cpu);
1167 }
1168
1169 void cpu_ppc_hdecr_exit(CPUPPCState *env)
1170 {
1171 PowerPCCPU *cpu = env_archcpu(env);
1172
1173 timer_free(env->tb_env->hdecr_timer);
1174 env->tb_env->hdecr_timer = NULL;
1175
1176 cpu_ppc_hdecr_lower(cpu);
1177 }
1178
1179 /*****************************************************************************/
1180 /* PowerPC 40x timers */
1181
1182 /* PIT, FIT & WDT */
1183 typedef struct ppc40x_timer_t ppc40x_timer_t;
1184 struct ppc40x_timer_t {
1185 uint64_t pit_reload; /* PIT auto-reload value */
1186 uint64_t fit_next; /* Tick for next FIT interrupt */
1187 QEMUTimer *fit_timer;
1188 uint64_t wdt_next; /* Tick for next WDT interrupt */
1189 QEMUTimer *wdt_timer;
1190
1191 /* 405 have the PIT, 440 have a DECR. */
1192 unsigned int decr_excp;
1193 };
1194
1195 /* Fixed interval timer */
1196 static void cpu_4xx_fit_cb (void *opaque)
1197 {
1198 PowerPCCPU *cpu = opaque;
1199 CPUPPCState *env = &cpu->env;
1200 ppc_tb_t *tb_env;
1201 ppc40x_timer_t *ppc40x_timer;
1202 uint64_t now, next;
1203
1204 tb_env = env->tb_env;
1205 ppc40x_timer = tb_env->opaque;
1206 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1207 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1208 case 0:
1209 next = 1 << 9;
1210 break;
1211 case 1:
1212 next = 1 << 13;
1213 break;
1214 case 2:
1215 next = 1 << 17;
1216 break;
1217 case 3:
1218 next = 1 << 21;
1219 break;
1220 default:
1221 /* Cannot occur, but makes gcc happy */
1222 return;
1223 }
1224 next = now + tb_to_ns_round_up(tb_env->tb_freq, next);
1225 timer_mod(ppc40x_timer->fit_timer, next);
1226 env->spr[SPR_40x_TSR] |= 1 << 26;
1227 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1228 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1229 }
1230 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1231 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1232 }
1233
1234 /* Programmable interval timer */
1235 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1236 {
1237 ppc40x_timer_t *ppc40x_timer;
1238 uint64_t now, next;
1239
1240 ppc40x_timer = tb_env->opaque;
1241 if (ppc40x_timer->pit_reload <= 1 ||
1242 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1243 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1244 /* Stop PIT */
1245 trace_ppc4xx_pit_stop();
1246 timer_del(tb_env->decr_timer);
1247 } else {
1248 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
1249 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1250
1251 if (is_excp) {
1252 tb_env->decr_next += ppc40x_timer->pit_reload;
1253 } else {
1254 tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now)
1255 + ppc40x_timer->pit_reload;
1256 }
1257 next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next);
1258 timer_mod(tb_env->decr_timer, next);
1259 }
1260 }
1261
1262 static void cpu_4xx_pit_cb (void *opaque)
1263 {
1264 PowerPCCPU *cpu = opaque;
1265 CPUPPCState *env = &cpu->env;
1266 ppc_tb_t *tb_env;
1267 ppc40x_timer_t *ppc40x_timer;
1268
1269 tb_env = env->tb_env;
1270 ppc40x_timer = tb_env->opaque;
1271 env->spr[SPR_40x_TSR] |= 1 << 27;
1272 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1273 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1274 }
1275 start_stop_pit(env, tb_env, 1);
1276 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1277 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1278 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1279 ppc40x_timer->pit_reload);
1280 }
1281
1282 /* Watchdog timer */
1283 static void cpu_4xx_wdt_cb (void *opaque)
1284 {
1285 PowerPCCPU *cpu = opaque;
1286 CPUPPCState *env = &cpu->env;
1287 ppc_tb_t *tb_env;
1288 ppc40x_timer_t *ppc40x_timer;
1289 uint64_t now, next;
1290
1291 tb_env = env->tb_env;
1292 ppc40x_timer = tb_env->opaque;
1293 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1294 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1295 case 0:
1296 next = 1 << 17;
1297 break;
1298 case 1:
1299 next = 1 << 21;
1300 break;
1301 case 2:
1302 next = 1 << 25;
1303 break;
1304 case 3:
1305 next = 1 << 29;
1306 break;
1307 default:
1308 /* Cannot occur, but makes gcc happy */
1309 return;
1310 }
1311 next = now + tb_to_ns_round_up(tb_env->decr_freq, next);
1312 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1313 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1314 case 0x0:
1315 case 0x1:
1316 timer_mod(ppc40x_timer->wdt_timer, next);
1317 ppc40x_timer->wdt_next = next;
1318 env->spr[SPR_40x_TSR] |= 1U << 31;
1319 break;
1320 case 0x2:
1321 timer_mod(ppc40x_timer->wdt_timer, next);
1322 ppc40x_timer->wdt_next = next;
1323 env->spr[SPR_40x_TSR] |= 1 << 30;
1324 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1325 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1326 }
1327 break;
1328 case 0x3:
1329 env->spr[SPR_40x_TSR] &= ~0x30000000;
1330 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1331 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1332 case 0x0:
1333 /* No reset */
1334 break;
1335 case 0x1: /* Core reset */
1336 ppc40x_core_reset(cpu);
1337 break;
1338 case 0x2: /* Chip reset */
1339 ppc40x_chip_reset(cpu);
1340 break;
1341 case 0x3: /* System reset */
1342 ppc40x_system_reset(cpu);
1343 break;
1344 }
1345 }
1346 }
1347
1348 void store_40x_pit (CPUPPCState *env, target_ulong val)
1349 {
1350 ppc_tb_t *tb_env;
1351 ppc40x_timer_t *ppc40x_timer;
1352
1353 tb_env = env->tb_env;
1354 ppc40x_timer = tb_env->opaque;
1355 trace_ppc40x_store_pit(val);
1356 ppc40x_timer->pit_reload = val;
1357 start_stop_pit(env, tb_env, 0);
1358 }
1359
1360 target_ulong load_40x_pit (CPUPPCState *env)
1361 {
1362 return cpu_ppc_load_decr(env);
1363 }
1364
1365 void store_40x_tsr(CPUPPCState *env, target_ulong val)
1366 {
1367 PowerPCCPU *cpu = env_archcpu(env);
1368
1369 trace_ppc40x_store_tcr(val);
1370
1371 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
1372 if (val & 0x80000000) {
1373 ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
1374 }
1375 }
1376
1377 void store_40x_tcr(CPUPPCState *env, target_ulong val)
1378 {
1379 PowerPCCPU *cpu = env_archcpu(env);
1380 ppc_tb_t *tb_env;
1381
1382 trace_ppc40x_store_tsr(val);
1383
1384 tb_env = env->tb_env;
1385 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1386 start_stop_pit(env, tb_env, 1);
1387 cpu_4xx_wdt_cb(cpu);
1388 }
1389
1390 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1391 {
1392 CPUPPCState *env = opaque;
1393 ppc_tb_t *tb_env = env->tb_env;
1394
1395 trace_ppc40x_set_tb_clk(freq);
1396 tb_env->tb_freq = freq;
1397 tb_env->decr_freq = freq;
1398 /* XXX: we should also update all timers */
1399 }
1400
1401 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1402 unsigned int decr_excp)
1403 {
1404 ppc_tb_t *tb_env;
1405 ppc40x_timer_t *ppc40x_timer;
1406 PowerPCCPU *cpu = env_archcpu(env);
1407
1408 trace_ppc40x_timers_init(freq);
1409
1410 tb_env = g_new0(ppc_tb_t, 1);
1411 ppc40x_timer = g_new0(ppc40x_timer_t, 1);
1412
1413 env->tb_env = tb_env;
1414 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1415 tb_env->tb_freq = freq;
1416 tb_env->decr_freq = freq;
1417 tb_env->opaque = ppc40x_timer;
1418
1419 /* We use decr timer for PIT */
1420 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu);
1421 ppc40x_timer->fit_timer =
1422 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, cpu);
1423 ppc40x_timer->wdt_timer =
1424 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, cpu);
1425 ppc40x_timer->decr_excp = decr_excp;
1426
1427 return &ppc_40x_set_tb_clk;
1428 }
1429
1430 /*****************************************************************************/
1431 /* Embedded PowerPC Device Control Registers */
1432 typedef struct ppc_dcrn_t ppc_dcrn_t;
1433 struct ppc_dcrn_t {
1434 dcr_read_cb dcr_read;
1435 dcr_write_cb dcr_write;
1436 void *opaque;
1437 };
1438
1439 /* XXX: on 460, DCR addresses are 32 bits wide,
1440 * using DCRIPR to get the 22 upper bits of the DCR address
1441 */
1442 #define DCRN_NB 1024
1443 struct ppc_dcr_t {
1444 ppc_dcrn_t dcrn[DCRN_NB];
1445 int (*read_error)(int dcrn);
1446 int (*write_error)(int dcrn);
1447 };
1448
1449 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1450 {
1451 ppc_dcrn_t *dcr;
1452
1453 if (dcrn < 0 || dcrn >= DCRN_NB)
1454 goto error;
1455 dcr = &dcr_env->dcrn[dcrn];
1456 if (dcr->dcr_read == NULL)
1457 goto error;
1458 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1459 trace_ppc_dcr_read(dcrn, *valp);
1460
1461 return 0;
1462
1463 error:
1464 if (dcr_env->read_error != NULL)
1465 return (*dcr_env->read_error)(dcrn);
1466
1467 return -1;
1468 }
1469
1470 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1471 {
1472 ppc_dcrn_t *dcr;
1473
1474 if (dcrn < 0 || dcrn >= DCRN_NB)
1475 goto error;
1476 dcr = &dcr_env->dcrn[dcrn];
1477 if (dcr->dcr_write == NULL)
1478 goto error;
1479 trace_ppc_dcr_write(dcrn, val);
1480 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1481
1482 return 0;
1483
1484 error:
1485 if (dcr_env->write_error != NULL)
1486 return (*dcr_env->write_error)(dcrn);
1487
1488 return -1;
1489 }
1490
1491 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1492 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1493 {
1494 ppc_dcr_t *dcr_env;
1495 ppc_dcrn_t *dcr;
1496
1497 dcr_env = env->dcr_env;
1498 if (dcr_env == NULL)
1499 return -1;
1500 if (dcrn < 0 || dcrn >= DCRN_NB)
1501 return -1;
1502 dcr = &dcr_env->dcrn[dcrn];
1503 if (dcr->opaque != NULL ||
1504 dcr->dcr_read != NULL ||
1505 dcr->dcr_write != NULL)
1506 return -1;
1507 dcr->opaque = opaque;
1508 dcr->dcr_read = dcr_read;
1509 dcr->dcr_write = dcr_write;
1510
1511 return 0;
1512 }
1513
1514 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1515 int (*write_error)(int dcrn))
1516 {
1517 ppc_dcr_t *dcr_env;
1518
1519 dcr_env = g_new0(ppc_dcr_t, 1);
1520 dcr_env->read_error = read_error;
1521 dcr_env->write_error = write_error;
1522 env->dcr_env = dcr_env;
1523
1524 return 0;
1525 }
1526
1527 /*****************************************************************************/
1528
1529 int ppc_cpu_pir(PowerPCCPU *cpu)
1530 {
1531 CPUPPCState *env = &cpu->env;
1532 return env->spr_cb[SPR_PIR].default_value;
1533 }
1534
1535 int ppc_cpu_tir(PowerPCCPU *cpu)
1536 {
1537 CPUPPCState *env = &cpu->env;
1538 return env->spr_cb[SPR_TIR].default_value;
1539 }
1540
1541 PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1542 {
1543 CPUState *cs;
1544
1545 CPU_FOREACH(cs) {
1546 PowerPCCPU *cpu = POWERPC_CPU(cs);
1547
1548 if (ppc_cpu_pir(cpu) == pir) {
1549 return cpu;
1550 }
1551 }
1552
1553 return NULL;
1554 }
1555
1556 void ppc_irq_reset(PowerPCCPU *cpu)
1557 {
1558 CPUPPCState *env = &cpu->env;
1559
1560 env->irq_input_state = 0;
1561 if (kvm_enabled()) {
1562 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
1563 }
1564 }