@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 1,054 lines 28.4 KB
Raw
1 /*
2 * QEMU PowerPC 440 embedded processors emulation
3 *
4 * Copyright (c) 2012 François Revol
5 * Copyright (c) 2016-2019 BALATON Zoltan
6 *
7 * This work is licensed under the GNU GPL license version 2 or later.
8 *
9 */
10
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
14 #include "qemu/log.h"
15 #include "hw/core/irq.h"
16 #include "hw/ppc/ppc4xx.h"
17 #include "hw/pci-host/ppc4xx.h"
18 #include "hw/core/qdev-properties.h"
19 #include "hw/pci/pci.h"
20 #include "exec/cpu-common.h"
21 #include "system/physmem.h"
22 #include "system/reset.h"
23 #include "target/ppc/cpu.h"
24 #include "ppc440.h"
25
26 /*****************************************************************************/
27 /* L2 Cache as SRAM */
28 /* FIXME:fix names */
29 enum {
30 DCR_L2CACHE_BASE = 0x30,
31 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE,
32 DCR_L2CACHE_CMD,
33 DCR_L2CACHE_ADDR,
34 DCR_L2CACHE_DATA,
35 DCR_L2CACHE_STAT,
36 DCR_L2CACHE_CVER,
37 DCR_L2CACHE_SNP0,
38 DCR_L2CACHE_SNP1,
39 DCR_L2CACHE_END = DCR_L2CACHE_SNP1,
40 };
41
42 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
43 enum {
44 DCR_ISRAM0_BASE = 0x20,
45 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE,
46 DCR_ISRAM0_SB1CR,
47 DCR_ISRAM0_SB2CR,
48 DCR_ISRAM0_SB3CR,
49 DCR_ISRAM0_BEAR,
50 DCR_ISRAM0_BESR0,
51 DCR_ISRAM0_BESR1,
52 DCR_ISRAM0_PMEG,
53 DCR_ISRAM0_CID,
54 DCR_ISRAM0_REVID,
55 DCR_ISRAM0_DPC,
56 DCR_ISRAM0_END = DCR_ISRAM0_DPC
57 };
58
59 enum {
60 DCR_ISRAM1_BASE = 0xb0,
61 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE,
62 /* single bank */
63 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04,
64 DCR_ISRAM1_BESR0,
65 DCR_ISRAM1_BESR1,
66 DCR_ISRAM1_PMEG,
67 DCR_ISRAM1_CID,
68 DCR_ISRAM1_REVID,
69 DCR_ISRAM1_DPC,
70 DCR_ISRAM1_END = DCR_ISRAM1_DPC
71 };
72
73 typedef struct ppc4xx_l2sram_t {
74 MemoryRegion bank[4];
75 uint32_t l2cache[8];
76 uint32_t isram0[11];
77 } ppc4xx_l2sram_t;
78
79 static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
80 {
81 ppc4xx_l2sram_t *l2sram = opaque;
82 uint32_t ret = 0;
83
84 switch (dcrn) {
85 case DCR_L2CACHE_CFG:
86 case DCR_L2CACHE_CMD:
87 case DCR_L2CACHE_ADDR:
88 case DCR_L2CACHE_DATA:
89 case DCR_L2CACHE_STAT:
90 case DCR_L2CACHE_CVER:
91 case DCR_L2CACHE_SNP0:
92 case DCR_L2CACHE_SNP1:
93 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
94 break;
95
96 case DCR_ISRAM0_SB0CR:
97 case DCR_ISRAM0_SB1CR:
98 case DCR_ISRAM0_SB2CR:
99 case DCR_ISRAM0_SB3CR:
100 case DCR_ISRAM0_BEAR:
101 case DCR_ISRAM0_BESR0:
102 case DCR_ISRAM0_BESR1:
103 case DCR_ISRAM0_PMEG:
104 case DCR_ISRAM0_CID:
105 case DCR_ISRAM0_REVID:
106 case DCR_ISRAM0_DPC:
107 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
108 break;
109
110 default:
111 break;
112 }
113
114 return ret;
115 }
116
117 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
118 {
119 /*ppc4xx_l2sram_t *l2sram = opaque;*/
120 /* FIXME: Actually handle L2 cache mapping */
121
122 switch (dcrn) {
123 case DCR_L2CACHE_CFG:
124 case DCR_L2CACHE_CMD:
125 case DCR_L2CACHE_ADDR:
126 case DCR_L2CACHE_DATA:
127 case DCR_L2CACHE_STAT:
128 case DCR_L2CACHE_CVER:
129 case DCR_L2CACHE_SNP0:
130 case DCR_L2CACHE_SNP1:
131 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
132 break;
133
134 case DCR_ISRAM0_SB0CR:
135 case DCR_ISRAM0_SB1CR:
136 case DCR_ISRAM0_SB2CR:
137 case DCR_ISRAM0_SB3CR:
138 case DCR_ISRAM0_BEAR:
139 case DCR_ISRAM0_BESR0:
140 case DCR_ISRAM0_BESR1:
141 case DCR_ISRAM0_PMEG:
142 case DCR_ISRAM0_CID:
143 case DCR_ISRAM0_REVID:
144 case DCR_ISRAM0_DPC:
145 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
146 break;
147
148 case DCR_ISRAM1_SB0CR:
149 case DCR_ISRAM1_BEAR:
150 case DCR_ISRAM1_BESR0:
151 case DCR_ISRAM1_BESR1:
152 case DCR_ISRAM1_PMEG:
153 case DCR_ISRAM1_CID:
154 case DCR_ISRAM1_REVID:
155 case DCR_ISRAM1_DPC:
156 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
157 break;
158 }
159 }
160
161 static void l2sram_reset(void *opaque)
162 {
163 ppc4xx_l2sram_t *l2sram = opaque;
164
165 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
166 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
167 memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
168 }
169
170 void ppc4xx_l2sram_init(CPUPPCState *env)
171 {
172 ppc4xx_l2sram_t *l2sram;
173
174 l2sram = g_malloc0(sizeof(*l2sram));
175 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
176 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
177 64 * KiB, &error_abort);
178 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
179 64 * KiB, &error_abort);
180 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
181 64 * KiB, &error_abort);
182 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
183 64 * KiB, &error_abort);
184 qemu_register_reset(&l2sram_reset, l2sram);
185 ppc_dcr_register(env, DCR_L2CACHE_CFG,
186 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
187 ppc_dcr_register(env, DCR_L2CACHE_CMD,
188 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
189 ppc_dcr_register(env, DCR_L2CACHE_ADDR,
190 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
191 ppc_dcr_register(env, DCR_L2CACHE_DATA,
192 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
193 ppc_dcr_register(env, DCR_L2CACHE_STAT,
194 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
195 ppc_dcr_register(env, DCR_L2CACHE_CVER,
196 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
197 ppc_dcr_register(env, DCR_L2CACHE_SNP0,
198 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
199 ppc_dcr_register(env, DCR_L2CACHE_SNP1,
200 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
201
202 ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
203 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
204 ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
205 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
206 ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
207 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
208 ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
209 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
210 ppc_dcr_register(env, DCR_ISRAM0_PMEG,
211 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
212 ppc_dcr_register(env, DCR_ISRAM0_DPC,
213 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
214
215 ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
216 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
217 ppc_dcr_register(env, DCR_ISRAM1_PMEG,
218 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
219 ppc_dcr_register(env, DCR_ISRAM1_DPC,
220 l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
221 }
222
223 /*****************************************************************************/
224 /* Clocking Power on Reset */
225 enum {
226 CPR0_CFGADDR = 0xC,
227 CPR0_CFGDATA = 0xD,
228
229 CPR0_PLLD = 0x060,
230 CPR0_PLBED = 0x080,
231 CPR0_OPBD = 0x0C0,
232 CPR0_PERD = 0x0E0,
233 CPR0_AHBD = 0x100,
234 };
235
236 typedef struct ppc4xx_cpr_t {
237 uint32_t addr;
238 } ppc4xx_cpr_t;
239
240 static uint32_t dcr_read_cpr(void *opaque, int dcrn)
241 {
242 ppc4xx_cpr_t *cpr = opaque;
243 uint32_t ret = 0;
244
245 switch (dcrn) {
246 case CPR0_CFGADDR:
247 ret = cpr->addr;
248 break;
249 case CPR0_CFGDATA:
250 switch (cpr->addr) {
251 case CPR0_PLLD:
252 ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
253 break;
254 case CPR0_PLBED:
255 ret = (5 << 24);
256 break;
257 case CPR0_OPBD:
258 ret = (2 << 24);
259 break;
260 case CPR0_PERD:
261 case CPR0_AHBD:
262 ret = (1 << 24);
263 break;
264 default:
265 break;
266 }
267 break;
268 default:
269 break;
270 }
271
272 return ret;
273 }
274
275 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
276 {
277 ppc4xx_cpr_t *cpr = opaque;
278
279 switch (dcrn) {
280 case CPR0_CFGADDR:
281 cpr->addr = val;
282 break;
283 case CPR0_CFGDATA:
284 break;
285 default:
286 break;
287 }
288 }
289
290 static void ppc4xx_cpr_reset(void *opaque)
291 {
292 ppc4xx_cpr_t *cpr = opaque;
293
294 cpr->addr = 0;
295 }
296
297 void ppc4xx_cpr_init(CPUPPCState *env)
298 {
299 ppc4xx_cpr_t *cpr;
300
301 cpr = g_malloc0(sizeof(*cpr));
302 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
303 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
304 qemu_register_reset(ppc4xx_cpr_reset, cpr);
305 }
306
307 /*****************************************************************************/
308 /* System DCRs */
309 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
310 struct ppc4xx_sdr_t {
311 uint32_t addr;
312 };
313
314 enum {
315 SDR0_CFGADDR = 0x00e,
316 SDR0_CFGDATA,
317 SDR0_STRP0 = 0x020,
318 SDR0_STRP1,
319 SDR0_102 = 0x66,
320 SDR0_103,
321 SDR0_128 = 0x80,
322 SDR0_ECID3 = 0x083,
323 SDR0_DDR0 = 0x0e1,
324 SDR0_USB0 = 0x320,
325 };
326
327 enum {
328 PESDR0_LOOP = 0x303,
329 PESDR0_RCSSET,
330 PESDR0_RCSSTS,
331 PESDR0_RSTSTA = 0x310,
332 PESDR1_LOOP = 0x343,
333 PESDR1_RCSSET,
334 PESDR1_RCSSTS,
335 PESDR1_RSTSTA = 0x365,
336 };
337
338 static uint32_t dcr_read_sdr(void *opaque, int dcrn)
339 {
340 ppc4xx_sdr_t *sdr = opaque;
341 uint32_t ret = 0;
342
343 switch (dcrn) {
344 case SDR0_CFGADDR:
345 ret = sdr->addr;
346 break;
347 case SDR0_CFGDATA:
348 switch (sdr->addr) {
349 case SDR0_STRP0:
350 ret = (0xb5 << 8) | (1 << 4) | 9;
351 break;
352 case SDR0_STRP1:
353 ret = (5 << 29) | (2 << 26) | (1 << 24);
354 break;
355 case SDR0_ECID3:
356 ret = 1 << 20; /* No Security/Kasumi support */
357 break;
358 case SDR0_DDR0:
359 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
360 break;
361 case PESDR0_RCSSET:
362 case PESDR1_RCSSET:
363 ret = (1 << 24) | (1 << 16);
364 break;
365 case PESDR0_RCSSTS:
366 case PESDR1_RCSSTS:
367 ret = (1 << 16) | (1 << 12);
368 break;
369 case PESDR0_RSTSTA:
370 case PESDR1_RSTSTA:
371 ret = 1;
372 break;
373 case PESDR0_LOOP:
374 case PESDR1_LOOP:
375 ret = 1 << 12;
376 break;
377 default:
378 break;
379 }
380 break;
381 default:
382 break;
383 }
384
385 return ret;
386 }
387
388 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
389 {
390 ppc4xx_sdr_t *sdr = opaque;
391
392 switch (dcrn) {
393 case SDR0_CFGADDR:
394 sdr->addr = val;
395 break;
396 case SDR0_CFGDATA:
397 switch (sdr->addr) {
398 case 0x00: /* B0CR */
399 break;
400 default:
401 break;
402 }
403 break;
404 default:
405 break;
406 }
407 }
408
409 static void sdr_reset(void *opaque)
410 {
411 ppc4xx_sdr_t *sdr = opaque;
412
413 sdr->addr = 0;
414 }
415
416 void ppc4xx_sdr_init(CPUPPCState *env)
417 {
418 ppc4xx_sdr_t *sdr;
419
420 sdr = g_malloc0(sizeof(*sdr));
421 qemu_register_reset(&sdr_reset, sdr);
422 ppc_dcr_register(env, SDR0_CFGADDR,
423 sdr, &dcr_read_sdr, &dcr_write_sdr);
424 ppc_dcr_register(env, SDR0_CFGDATA,
425 sdr, &dcr_read_sdr, &dcr_write_sdr);
426 ppc_dcr_register(env, SDR0_102,
427 sdr, &dcr_read_sdr, &dcr_write_sdr);
428 ppc_dcr_register(env, SDR0_103,
429 sdr, &dcr_read_sdr, &dcr_write_sdr);
430 ppc_dcr_register(env, SDR0_128,
431 sdr, &dcr_read_sdr, &dcr_write_sdr);
432 ppc_dcr_register(env, SDR0_USB0,
433 sdr, &dcr_read_sdr, &dcr_write_sdr);
434 }
435
436 /*****************************************************************************/
437 /* PLB to AHB bridge */
438 enum {
439 AHB_TOP = 0xA4,
440 AHB_BOT = 0xA5,
441 };
442
443 typedef struct ppc4xx_ahb_t {
444 uint32_t top;
445 uint32_t bot;
446 } ppc4xx_ahb_t;
447
448 static uint32_t dcr_read_ahb(void *opaque, int dcrn)
449 {
450 ppc4xx_ahb_t *ahb = opaque;
451 uint32_t ret = 0;
452
453 switch (dcrn) {
454 case AHB_TOP:
455 ret = ahb->top;
456 break;
457 case AHB_BOT:
458 ret = ahb->bot;
459 break;
460 default:
461 break;
462 }
463
464 return ret;
465 }
466
467 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
468 {
469 ppc4xx_ahb_t *ahb = opaque;
470
471 switch (dcrn) {
472 case AHB_TOP:
473 ahb->top = val;
474 break;
475 case AHB_BOT:
476 ahb->bot = val;
477 break;
478 }
479 }
480
481 static void ppc4xx_ahb_reset(void *opaque)
482 {
483 ppc4xx_ahb_t *ahb = opaque;
484
485 /* No error */
486 ahb->top = 0;
487 ahb->bot = 0;
488 }
489
490 void ppc4xx_ahb_init(CPUPPCState *env)
491 {
492 ppc4xx_ahb_t *ahb;
493
494 ahb = g_malloc0(sizeof(*ahb));
495 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
496 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
497 qemu_register_reset(ppc4xx_ahb_reset, ahb);
498 }
499
500 /*****************************************************************************/
501 /* DMA controller */
502
503 #define DMA0_CR_CE (1 << 31)
504 #define DMA0_CR_PW (1 << 26 | 1 << 25)
505 #define DMA0_CR_DAI (1 << 24)
506 #define DMA0_CR_SAI (1 << 23)
507 #define DMA0_CR_DEC (1 << 2)
508
509 enum {
510 DMA0_CR = 0x00,
511 DMA0_CT,
512 DMA0_SAH,
513 DMA0_SAL,
514 DMA0_DAH,
515 DMA0_DAL,
516 DMA0_SGH,
517 DMA0_SGL,
518
519 DMA0_SR = 0x20,
520 DMA0_SGC = 0x23,
521 DMA0_SLP = 0x25,
522 DMA0_POL = 0x26,
523 };
524
525 typedef struct {
526 uint32_t cr;
527 uint32_t ct;
528 uint64_t sa;
529 uint64_t da;
530 uint64_t sg;
531 } PPC4xxDmaChnl;
532
533 typedef struct {
534 int base;
535 PPC4xxDmaChnl ch[4];
536 uint32_t sr;
537 } PPC4xxDmaState;
538
539 static uint32_t dcr_read_dma(void *opaque, int dcrn)
540 {
541 PPC4xxDmaState *dma = opaque;
542 uint32_t val = 0;
543 int addr = dcrn - dma->base;
544 int chnl = addr / 8;
545
546 switch (addr) {
547 case 0x00 ... 0x1f:
548 switch (addr % 8) {
549 case DMA0_CR:
550 val = dma->ch[chnl].cr;
551 break;
552 case DMA0_CT:
553 val = dma->ch[chnl].ct;
554 break;
555 case DMA0_SAH:
556 val = dma->ch[chnl].sa >> 32;
557 break;
558 case DMA0_SAL:
559 val = dma->ch[chnl].sa;
560 break;
561 case DMA0_DAH:
562 val = dma->ch[chnl].da >> 32;
563 break;
564 case DMA0_DAL:
565 val = dma->ch[chnl].da;
566 break;
567 case DMA0_SGH:
568 val = dma->ch[chnl].sg >> 32;
569 break;
570 case DMA0_SGL:
571 val = dma->ch[chnl].sg;
572 break;
573 }
574 break;
575 case DMA0_SR:
576 val = dma->sr;
577 break;
578 default:
579 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
580 __func__, dcrn, chnl, addr);
581 }
582
583 return val;
584 }
585
586 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
587 {
588 PPC4xxDmaState *dma = opaque;
589 int addr = dcrn - dma->base;
590 int chnl = addr / 8;
591
592 switch (addr) {
593 case 0x00 ... 0x1f:
594 switch (addr % 8) {
595 case DMA0_CR:
596 dma->ch[chnl].cr = val;
597 if (val & DMA0_CR_CE) {
598 int count = dma->ch[chnl].ct & 0xffff;
599
600 if (count) {
601 int width, i, sidx, didx;
602 uint8_t *rptr, *wptr;
603 hwaddr rlen, wlen;
604 hwaddr xferlen;
605
606 sidx = didx = 0;
607 width = 1 << ((val & DMA0_CR_PW) >> 25);
608 xferlen = count * width;
609 wlen = rlen = xferlen;
610 rptr = physical_memory_map(dma->ch[chnl].sa, &rlen,
611 false);
612 wptr = physical_memory_map(dma->ch[chnl].da, &wlen,
613 true);
614 if (rptr && rlen == xferlen && wptr && wlen == xferlen) {
615 if (!(val & DMA0_CR_DEC) &&
616 val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
617 /* optimise common case */
618 memmove(wptr, rptr, count * width);
619 sidx = didx = count * width;
620 } else {
621 /* do it the slow way */
622 for (sidx = didx = i = 0; i < count; i++) {
623 uint64_t v = ldn_le_p(rptr + sidx, width);
624 stn_le_p(wptr + didx, width, v);
625 if (val & DMA0_CR_SAI) {
626 sidx += width;
627 }
628 if (val & DMA0_CR_DAI) {
629 didx += width;
630 }
631 }
632 }
633 }
634 if (wptr) {
635 physical_memory_unmap(wptr, wlen, 1, didx);
636 }
637 if (rptr) {
638 physical_memory_unmap(rptr, rlen, 0, sidx);
639 }
640 }
641 }
642 break;
643 case DMA0_CT:
644 dma->ch[chnl].ct = val;
645 break;
646 case DMA0_SAH:
647 dma->ch[chnl].sa &= 0xffffffffULL;
648 dma->ch[chnl].sa |= (uint64_t)val << 32;
649 break;
650 case DMA0_SAL:
651 dma->ch[chnl].sa &= 0xffffffff00000000ULL;
652 dma->ch[chnl].sa |= val;
653 break;
654 case DMA0_DAH:
655 dma->ch[chnl].da &= 0xffffffffULL;
656 dma->ch[chnl].da |= (uint64_t)val << 32;
657 break;
658 case DMA0_DAL:
659 dma->ch[chnl].da &= 0xffffffff00000000ULL;
660 dma->ch[chnl].da |= val;
661 break;
662 case DMA0_SGH:
663 dma->ch[chnl].sg &= 0xffffffffULL;
664 dma->ch[chnl].sg |= (uint64_t)val << 32;
665 break;
666 case DMA0_SGL:
667 dma->ch[chnl].sg &= 0xffffffff00000000ULL;
668 dma->ch[chnl].sg |= val;
669 break;
670 }
671 break;
672 case DMA0_SR:
673 dma->sr &= ~val;
674 break;
675 default:
676 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
677 __func__, dcrn, chnl, addr);
678 }
679 }
680
681 static void ppc4xx_dma_reset(void *opaque)
682 {
683 PPC4xxDmaState *dma = opaque;
684 int dma_base = dma->base;
685
686 memset(dma, 0, sizeof(*dma));
687 dma->base = dma_base;
688 }
689
690 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
691 {
692 PPC4xxDmaState *dma;
693 int i;
694
695 dma = g_malloc0(sizeof(*dma));
696 dma->base = dcr_base;
697 qemu_register_reset(&ppc4xx_dma_reset, dma);
698 for (i = 0; i < 4; i++) {
699 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 }
716 ppc_dcr_register(env, dcr_base + DMA0_SR,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, dcr_base + DMA0_SGC,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 ppc_dcr_register(env, dcr_base + DMA0_SLP,
721 dma, &dcr_read_dma, &dcr_write_dma);
722 ppc_dcr_register(env, dcr_base + DMA0_POL,
723 dma, &dcr_read_dma, &dcr_write_dma);
724 }
725
726 /*****************************************************************************/
727 /* PCI Express controller */
728 /*
729 * FIXME: This is not complete and does not work, only implemented partially
730 * to allow firmware and guests to find an empty bus. Cards should use PCI.
731 */
732 #include "hw/pci/pcie_host.h"
733
734 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
735
736 struct PPC460EXPCIEState {
737 PCIExpressHost parent_obj;
738
739 MemoryRegion busmem;
740 MemoryRegion iomem;
741 qemu_irq irq[4];
742 int32_t num;
743 int32_t dcrn_base;
744 PowerPCCPU *cpu;
745
746 uint64_t cfg_base;
747 uint32_t cfg_mask;
748 uint64_t msg_base;
749 uint32_t msg_mask;
750 uint64_t omr1_base;
751 uint64_t omr1_mask;
752 uint64_t omr2_base;
753 uint64_t omr2_mask;
754 uint64_t omr3_base;
755 uint64_t omr3_mask;
756 uint64_t reg_base;
757 uint32_t reg_mask;
758 uint32_t special;
759 uint32_t cfg;
760 };
761
762 enum {
763 PEGPL_CFGBAH = 0x0,
764 PEGPL_CFGBAL,
765 PEGPL_CFGMSK,
766 PEGPL_MSGBAH,
767 PEGPL_MSGBAL,
768 PEGPL_MSGMSK,
769 PEGPL_OMR1BAH,
770 PEGPL_OMR1BAL,
771 PEGPL_OMR1MSKH,
772 PEGPL_OMR1MSKL,
773 PEGPL_OMR2BAH,
774 PEGPL_OMR2BAL,
775 PEGPL_OMR2MSKH,
776 PEGPL_OMR2MSKL,
777 PEGPL_OMR3BAH,
778 PEGPL_OMR3BAL,
779 PEGPL_OMR3MSKH,
780 PEGPL_OMR3MSKL,
781 PEGPL_REGBAH,
782 PEGPL_REGBAL,
783 PEGPL_REGMSK,
784 PEGPL_SPECIAL,
785 PEGPL_CFG,
786 };
787
788 static uint32_t dcr_read_pcie(void *opaque, int dcrn)
789 {
790 PPC460EXPCIEState *s = opaque;
791 uint32_t ret = 0;
792
793 switch (dcrn - s->dcrn_base) {
794 case PEGPL_CFGBAH:
795 ret = s->cfg_base >> 32;
796 break;
797 case PEGPL_CFGBAL:
798 ret = s->cfg_base;
799 break;
800 case PEGPL_CFGMSK:
801 ret = s->cfg_mask;
802 break;
803 case PEGPL_MSGBAH:
804 ret = s->msg_base >> 32;
805 break;
806 case PEGPL_MSGBAL:
807 ret = s->msg_base;
808 break;
809 case PEGPL_MSGMSK:
810 ret = s->msg_mask;
811 break;
812 case PEGPL_OMR1BAH:
813 ret = s->omr1_base >> 32;
814 break;
815 case PEGPL_OMR1BAL:
816 ret = s->omr1_base;
817 break;
818 case PEGPL_OMR1MSKH:
819 ret = s->omr1_mask >> 32;
820 break;
821 case PEGPL_OMR1MSKL:
822 ret = s->omr1_mask;
823 break;
824 case PEGPL_OMR2BAH:
825 ret = s->omr2_base >> 32;
826 break;
827 case PEGPL_OMR2BAL:
828 ret = s->omr2_base;
829 break;
830 case PEGPL_OMR2MSKH:
831 ret = s->omr2_mask >> 32;
832 break;
833 case PEGPL_OMR2MSKL:
834 ret = s->omr3_mask;
835 break;
836 case PEGPL_OMR3BAH:
837 ret = s->omr3_base >> 32;
838 break;
839 case PEGPL_OMR3BAL:
840 ret = s->omr3_base;
841 break;
842 case PEGPL_OMR3MSKH:
843 ret = s->omr3_mask >> 32;
844 break;
845 case PEGPL_OMR3MSKL:
846 ret = s->omr3_mask;
847 break;
848 case PEGPL_REGBAH:
849 ret = s->reg_base >> 32;
850 break;
851 case PEGPL_REGBAL:
852 ret = s->reg_base;
853 break;
854 case PEGPL_REGMSK:
855 ret = s->reg_mask;
856 break;
857 case PEGPL_SPECIAL:
858 ret = s->special;
859 break;
860 case PEGPL_CFG:
861 ret = s->cfg;
862 break;
863 }
864
865 return ret;
866 }
867
868 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
869 {
870 PPC460EXPCIEState *s = opaque;
871 uint64_t size;
872
873 switch (dcrn - s->dcrn_base) {
874 case PEGPL_CFGBAH:
875 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
876 break;
877 case PEGPL_CFGBAL:
878 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
879 break;
880 case PEGPL_CFGMSK:
881 s->cfg_mask = val;
882 size = ~(val & 0xfffffffe) + 1;
883 /*
884 * Firmware sets this register to E0000001. Why we are not sure,
885 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
886 * ignored.
887 */
888 if (size > PCIE_MMCFG_SIZE_MAX) {
889 size = PCIE_MMCFG_SIZE_MAX;
890 }
891 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
892 break;
893 case PEGPL_MSGBAH:
894 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
895 break;
896 case PEGPL_MSGBAL:
897 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
898 break;
899 case PEGPL_MSGMSK:
900 s->msg_mask = val;
901 break;
902 case PEGPL_OMR1BAH:
903 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
904 break;
905 case PEGPL_OMR1BAL:
906 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
907 break;
908 case PEGPL_OMR1MSKH:
909 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
910 break;
911 case PEGPL_OMR1MSKL:
912 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
913 break;
914 case PEGPL_OMR2BAH:
915 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
916 break;
917 case PEGPL_OMR2BAL:
918 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
919 break;
920 case PEGPL_OMR2MSKH:
921 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
922 break;
923 case PEGPL_OMR2MSKL:
924 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
925 break;
926 case PEGPL_OMR3BAH:
927 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
928 break;
929 case PEGPL_OMR3BAL:
930 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
931 break;
932 case PEGPL_OMR3MSKH:
933 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
934 break;
935 case PEGPL_OMR3MSKL:
936 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
937 break;
938 case PEGPL_REGBAH:
939 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
940 break;
941 case PEGPL_REGBAL:
942 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
943 break;
944 case PEGPL_REGMSK:
945 s->reg_mask = val;
946 /* FIXME: how is size encoded? */
947 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
948 break;
949 case PEGPL_SPECIAL:
950 s->special = val;
951 break;
952 case PEGPL_CFG:
953 s->cfg = val;
954 break;
955 }
956 }
957
958 static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
959 {
960 PPC460EXPCIEState *s = opaque;
961 qemu_set_irq(s->irq[irq_num], level);
962 }
963
964 #define PPC440_PCIE_DCR(s, dcrn) \
965 ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
966 &dcr_read_pcie, &dcr_write_pcie)
967
968
969 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s)
970 {
971 PPC440_PCIE_DCR(s, PEGPL_CFGBAH);
972 PPC440_PCIE_DCR(s, PEGPL_CFGBAL);
973 PPC440_PCIE_DCR(s, PEGPL_CFGMSK);
974 PPC440_PCIE_DCR(s, PEGPL_MSGBAH);
975 PPC440_PCIE_DCR(s, PEGPL_MSGBAL);
976 PPC440_PCIE_DCR(s, PEGPL_MSGMSK);
977 PPC440_PCIE_DCR(s, PEGPL_OMR1BAH);
978 PPC440_PCIE_DCR(s, PEGPL_OMR1BAL);
979 PPC440_PCIE_DCR(s, PEGPL_OMR1MSKH);
980 PPC440_PCIE_DCR(s, PEGPL_OMR1MSKL);
981 PPC440_PCIE_DCR(s, PEGPL_OMR2BAH);
982 PPC440_PCIE_DCR(s, PEGPL_OMR2BAL);
983 PPC440_PCIE_DCR(s, PEGPL_OMR2MSKH);
984 PPC440_PCIE_DCR(s, PEGPL_OMR2MSKL);
985 PPC440_PCIE_DCR(s, PEGPL_OMR3BAH);
986 PPC440_PCIE_DCR(s, PEGPL_OMR3BAL);
987 PPC440_PCIE_DCR(s, PEGPL_OMR3MSKH);
988 PPC440_PCIE_DCR(s, PEGPL_OMR3MSKL);
989 PPC440_PCIE_DCR(s, PEGPL_REGBAH);
990 PPC440_PCIE_DCR(s, PEGPL_REGBAL);
991 PPC440_PCIE_DCR(s, PEGPL_REGMSK);
992 PPC440_PCIE_DCR(s, PEGPL_SPECIAL);
993 PPC440_PCIE_DCR(s, PEGPL_CFG);
994 }
995
996 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
997 {
998 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
999 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1000 int i;
1001 char buf[20];
1002
1003 if (!s->cpu) {
1004 error_setg(errp, "cpu link property must be set");
1005 return;
1006 }
1007 if (s->num < 0 || s->dcrn_base < 0) {
1008 error_setg(errp, "busnum and dcrn-base properties must be set");
1009 return;
1010 }
1011 snprintf(buf, sizeof(buf), "pcie%d-mem", s->num);
1012 memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX);
1013 snprintf(buf, sizeof(buf), "pcie%d-io", s->num);
1014 memory_region_init(&s->iomem, OBJECT(s), buf, 64 * KiB);
1015 for (i = 0; i < 4; i++) {
1016 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1017 }
1018 snprintf(buf, sizeof(buf), "pcie.%d", s->num);
1019 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
1020 pci_swizzle_map_irq_fn, s, &s->busmem,
1021 &s->iomem, 0, 4, TYPE_PCIE_BUS);
1022 ppc460ex_pcie_register_dcrs(s);
1023 }
1024
1025 static const Property ppc460ex_pcie_props[] = {
1026 DEFINE_PROP_INT32("busnum", PPC460EXPCIEState, num, -1),
1027 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
1028 DEFINE_PROP_LINK("cpu", PPC460EXPCIEState, cpu, TYPE_POWERPC_CPU,
1029 PowerPCCPU *),
1030 };
1031
1032 static void ppc460ex_pcie_class_init(ObjectClass *klass, const void *data)
1033 {
1034 DeviceClass *dc = DEVICE_CLASS(klass);
1035
1036 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1037 dc->realize = ppc460ex_pcie_realize;
1038 device_class_set_props(dc, ppc460ex_pcie_props);
1039 dc->hotpluggable = false;
1040 }
1041
1042 static const TypeInfo ppc460ex_pcie_host_info = {
1043 .name = TYPE_PPC460EX_PCIE_HOST,
1044 .parent = TYPE_PCIE_HOST_BRIDGE,
1045 .instance_size = sizeof(PPC460EXPCIEState),
1046 .class_init = ppc460ex_pcie_class_init,
1047 };
1048
1049 static void ppc460ex_pcie_register(void)
1050 {
1051 type_register_static(&ppc460ex_pcie_host_info);
1052 }
1053
1054 type_init(ppc460ex_pcie_register)