| 1 | /* |
| 2 | * QEMU PowerPC Booke hardware System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2011 AdaCore |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "target/ppc/cpu.h" |
| 27 | #include "exec/page-protection.h" |
| 28 | #include "exec/target_page.h" |
| 29 | #include "hw/ppc/ppc.h" |
| 30 | #include "qemu/timer.h" |
| 31 | #include "system/reset.h" |
| 32 | #include "system/runstate.h" |
| 33 | #include "hw/core/loader.h" |
| 34 | #include "kvm_ppc.h" |
| 35 | |
| 36 | void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa, |
| 37 | target_ulong size) |
| 38 | { |
| 39 | tlb->attr = 0; |
| 40 | tlb->prot = PAGE_RWX << 4 | PAGE_VALID; |
| 41 | tlb->size = size; |
| 42 | tlb->EPN = va & TARGET_PAGE_MASK; |
| 43 | tlb->RPN = pa & TARGET_PAGE_MASK; |
| 44 | tlb->PID = 0; |
| 45 | } |
| 46 | |
| 47 | /* Timer Control Register */ |
| 48 | |
| 49 | #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ |
| 50 | #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) |
| 51 | #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ |
| 52 | #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT) |
| 53 | #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */ |
| 54 | #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */ |
| 55 | #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ |
| 56 | #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT) |
| 57 | #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */ |
| 58 | #define TCR_ARE (1U << 22) /* Auto-Reload Enable */ |
| 59 | |
| 60 | /* Timer Control Register (e500 specific fields) */ |
| 61 | |
| 62 | #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ |
| 63 | #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) |
| 64 | #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ |
| 65 | #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) |
| 66 | |
| 67 | /* Timer Status Register */ |
| 68 | |
| 69 | #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */ |
| 70 | #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */ |
| 71 | #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ |
| 72 | #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT) |
| 73 | #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ |
| 74 | #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ |
| 75 | |
| 76 | typedef struct booke_timer_t booke_timer_t; |
| 77 | struct booke_timer_t { |
| 78 | |
| 79 | uint64_t fit_next; |
| 80 | QEMUTimer *fit_timer; |
| 81 | |
| 82 | uint64_t wdt_next; |
| 83 | QEMUTimer *wdt_timer; |
| 84 | |
| 85 | uint32_t flags; |
| 86 | }; |
| 87 | |
| 88 | static void booke_update_irq(PowerPCCPU *cpu) |
| 89 | { |
| 90 | CPUPPCState *env = &cpu->env; |
| 91 | |
| 92 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, |
| 93 | (env->spr[SPR_BOOKE_TSR] & TSR_DIS |
| 94 | && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); |
| 95 | |
| 96 | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, |
| 97 | (env->spr[SPR_BOOKE_TSR] & TSR_WIS |
| 98 | && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); |
| 99 | |
| 100 | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, |
| 101 | (env->spr[SPR_BOOKE_TSR] & TSR_FIS |
| 102 | && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); |
| 103 | } |
| 104 | |
| 105 | /* Return the location of the bit of time base at which the FIT will raise an |
| 106 | interrupt */ |
| 107 | static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) |
| 108 | { |
| 109 | uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; |
| 110 | |
| 111 | if (tb_env->flags & PPC_TIMER_E500) { |
| 112 | /* e500 Fixed-interval timer period extension */ |
| 113 | uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) |
| 114 | >> TCR_E500_FPEXT_SHIFT; |
| 115 | fp = 63 - (fp | fpext << 2); |
| 116 | } else { |
| 117 | fp = env->fit_period[fp]; |
| 118 | } |
| 119 | |
| 120 | return fp; |
| 121 | } |
| 122 | |
| 123 | /* Return the location of the bit of time base at which the WDT will raise an |
| 124 | interrupt */ |
| 125 | static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) |
| 126 | { |
| 127 | uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; |
| 128 | |
| 129 | if (tb_env->flags & PPC_TIMER_E500) { |
| 130 | /* e500 Watchdog timer period extension */ |
| 131 | uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) |
| 132 | >> TCR_E500_WPEXT_SHIFT; |
| 133 | wp = 63 - (wp | wpext << 2); |
| 134 | } else { |
| 135 | wp = env->wdt_period[wp]; |
| 136 | } |
| 137 | |
| 138 | return wp; |
| 139 | } |
| 140 | |
| 141 | static void booke_update_fixed_timer(CPUPPCState *env, |
| 142 | uint8_t target_bit, |
| 143 | uint64_t *next, |
| 144 | QEMUTimer *timer, |
| 145 | int tsr_bit) |
| 146 | { |
| 147 | ppc_tb_t *tb_env = env->tb_env; |
| 148 | uint64_t delta_tick, ticks = 0; |
| 149 | uint64_t tb; |
| 150 | uint64_t period; |
| 151 | uint64_t now; |
| 152 | |
| 153 | if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) { |
| 154 | /* |
| 155 | * Don't arm the timer again when the guest has the current |
| 156 | * interrupt still pending. Wait for it to ack it. |
| 157 | */ |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 162 | tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); |
| 163 | period = 1ULL << target_bit; |
| 164 | delta_tick = period - (tb & (period - 1)); |
| 165 | |
| 166 | /* the timer triggers only when the selected bit toggles from 0 to 1 */ |
| 167 | if (tb & period) { |
| 168 | ticks = period; |
| 169 | } |
| 170 | |
| 171 | if (ticks + delta_tick < ticks) { |
| 172 | /* Overflow, so assume the biggest number we can express. */ |
| 173 | ticks = UINT64_MAX; |
| 174 | } else { |
| 175 | ticks += delta_tick; |
| 176 | } |
| 177 | |
| 178 | *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq); |
| 179 | if ((*next < now) || (*next > INT64_MAX)) { |
| 180 | /* Overflow, so assume the biggest number the qemu timer supports. */ |
| 181 | *next = INT64_MAX; |
| 182 | } |
| 183 | |
| 184 | /* XXX: If expire time is now. We can't run the callback because we don't |
| 185 | * have access to it. So we just set the timer one nanosecond later. |
| 186 | */ |
| 187 | |
| 188 | if (*next == now) { |
| 189 | (*next)++; |
| 190 | } else { |
| 191 | /* |
| 192 | * There's no point to fake any granularity that's more fine grained |
| 193 | * than milliseconds. Anything beyond that just overloads the system. |
| 194 | */ |
| 195 | *next = MAX(*next, now + SCALE_MS); |
| 196 | } |
| 197 | |
| 198 | /* Fire the next timer */ |
| 199 | timer_mod(timer, *next); |
| 200 | } |
| 201 | |
| 202 | static void booke_decr_cb(void *opaque) |
| 203 | { |
| 204 | PowerPCCPU *cpu = opaque; |
| 205 | CPUPPCState *env = &cpu->env; |
| 206 | |
| 207 | env->spr[SPR_BOOKE_TSR] |= TSR_DIS; |
| 208 | booke_update_irq(cpu); |
| 209 | |
| 210 | if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { |
| 211 | /* Do not reload 0, it is already there. It would just trigger |
| 212 | * the timer again and lead to infinite loop */ |
| 213 | if (env->spr[SPR_BOOKE_DECAR] != 0) { |
| 214 | /* Auto Reload */ |
| 215 | cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); |
| 216 | } |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | static void booke_fit_cb(void *opaque) |
| 221 | { |
| 222 | PowerPCCPU *cpu = opaque; |
| 223 | CPUPPCState *env = &cpu->env; |
| 224 | ppc_tb_t *tb_env; |
| 225 | booke_timer_t *booke_timer; |
| 226 | |
| 227 | tb_env = env->tb_env; |
| 228 | booke_timer = tb_env->opaque; |
| 229 | env->spr[SPR_BOOKE_TSR] |= TSR_FIS; |
| 230 | |
| 231 | booke_update_irq(cpu); |
| 232 | |
| 233 | booke_update_fixed_timer(env, |
| 234 | booke_get_fit_target(env, tb_env), |
| 235 | &booke_timer->fit_next, |
| 236 | booke_timer->fit_timer, |
| 237 | TSR_FIS); |
| 238 | } |
| 239 | |
| 240 | static void booke_wdt_cb(void *opaque) |
| 241 | { |
| 242 | PowerPCCPU *cpu = opaque; |
| 243 | CPUPPCState *env = &cpu->env; |
| 244 | ppc_tb_t *tb_env; |
| 245 | booke_timer_t *booke_timer; |
| 246 | |
| 247 | tb_env = env->tb_env; |
| 248 | booke_timer = tb_env->opaque; |
| 249 | |
| 250 | /* TODO: There's lots of complicated stuff to do here */ |
| 251 | |
| 252 | booke_update_irq(cpu); |
| 253 | |
| 254 | booke_update_fixed_timer(env, |
| 255 | booke_get_wdt_target(env, tb_env), |
| 256 | &booke_timer->wdt_next, |
| 257 | booke_timer->wdt_timer, |
| 258 | TSR_WIS); |
| 259 | } |
| 260 | |
| 261 | void store_booke_tsr(CPUPPCState *env, target_ulong val) |
| 262 | { |
| 263 | PowerPCCPU *cpu = env_archcpu(env); |
| 264 | ppc_tb_t *tb_env = env->tb_env; |
| 265 | booke_timer_t *booke_timer = tb_env->opaque; |
| 266 | |
| 267 | env->spr[SPR_BOOKE_TSR] &= ~val; |
| 268 | kvmppc_clear_tsr_bits(cpu, val); |
| 269 | |
| 270 | if (val & TSR_FIS) { |
| 271 | booke_update_fixed_timer(env, |
| 272 | booke_get_fit_target(env, tb_env), |
| 273 | &booke_timer->fit_next, |
| 274 | booke_timer->fit_timer, |
| 275 | TSR_FIS); |
| 276 | } |
| 277 | |
| 278 | if (val & TSR_WIS) { |
| 279 | booke_update_fixed_timer(env, |
| 280 | booke_get_wdt_target(env, tb_env), |
| 281 | &booke_timer->wdt_next, |
| 282 | booke_timer->wdt_timer, |
| 283 | TSR_WIS); |
| 284 | } |
| 285 | |
| 286 | booke_update_irq(cpu); |
| 287 | } |
| 288 | |
| 289 | void store_booke_tcr(CPUPPCState *env, target_ulong val) |
| 290 | { |
| 291 | PowerPCCPU *cpu = env_archcpu(env); |
| 292 | ppc_tb_t *tb_env = env->tb_env; |
| 293 | booke_timer_t *booke_timer = tb_env->opaque; |
| 294 | |
| 295 | env->spr[SPR_BOOKE_TCR] = val; |
| 296 | kvmppc_set_tcr(cpu); |
| 297 | |
| 298 | booke_update_irq(cpu); |
| 299 | |
| 300 | booke_update_fixed_timer(env, |
| 301 | booke_get_fit_target(env, tb_env), |
| 302 | &booke_timer->fit_next, |
| 303 | booke_timer->fit_timer, |
| 304 | TSR_FIS); |
| 305 | |
| 306 | booke_update_fixed_timer(env, |
| 307 | booke_get_wdt_target(env, tb_env), |
| 308 | &booke_timer->wdt_next, |
| 309 | booke_timer->wdt_timer, |
| 310 | TSR_WIS); |
| 311 | } |
| 312 | |
| 313 | static void ppc_booke_timer_reset_handle(void *opaque) |
| 314 | { |
| 315 | PowerPCCPU *cpu = opaque; |
| 316 | CPUPPCState *env = &cpu->env; |
| 317 | |
| 318 | store_booke_tcr(env, 0); |
| 319 | store_booke_tsr(env, -1); |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * This function will be called whenever the CPU state changes. |
| 324 | * CPU states are defined "typedef enum RunState". |
| 325 | * Regarding timer, When CPU state changes to running after debug halt |
| 326 | * or similar cases which takes time then in between final watchdog |
| 327 | * expiry happenes. This will cause exit to QEMU and configured watchdog |
| 328 | * action will be taken. To avoid this we always clear the watchdog state when |
| 329 | * state changes to running. |
| 330 | */ |
| 331 | static void cpu_state_change_handler(void *opaque, bool running, RunState state) |
| 332 | { |
| 333 | PowerPCCPU *cpu = opaque; |
| 334 | CPUPPCState *env = &cpu->env; |
| 335 | |
| 336 | if (!running) { |
| 337 | return; |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * Clear watchdog interrupt condition by clearing TSR. |
| 342 | */ |
| 343 | store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); |
| 344 | } |
| 345 | |
| 346 | void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) |
| 347 | { |
| 348 | ppc_tb_t *tb_env; |
| 349 | booke_timer_t *booke_timer; |
| 350 | int ret = 0; |
| 351 | |
| 352 | tb_env = g_new0(ppc_tb_t, 1); |
| 353 | booke_timer = g_new0(booke_timer_t, 1); |
| 354 | |
| 355 | cpu->env.tb_env = tb_env; |
| 356 | if (flags & PPC_TIMER_PPE) { |
| 357 | /* PPE's use a modified version of the booke behavior */ |
| 358 | tb_env->flags = flags | PPC_DECR_UNDERFLOW_TRIGGERED; |
| 359 | } else { |
| 360 | tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; |
| 361 | } |
| 362 | |
| 363 | tb_env->tb_freq = freq; |
| 364 | tb_env->decr_freq = freq; |
| 365 | tb_env->opaque = booke_timer; |
| 366 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu); |
| 367 | |
| 368 | booke_timer->fit_timer = |
| 369 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu); |
| 370 | booke_timer->wdt_timer = |
| 371 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu); |
| 372 | |
| 373 | ret = kvmppc_booke_watchdog_enable(cpu); |
| 374 | |
| 375 | if (ret) { |
| 376 | /* TODO: Start the QEMU emulated watchdog if not running on KVM. |
| 377 | * Also start the QEMU emulated watchdog if KVM does not support |
| 378 | * emulated watchdog or somehow it is not enabled (supported but |
| 379 | * not enabled is though some bug and requires debugging :)). |
| 380 | */ |
| 381 | } |
| 382 | |
| 383 | qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); |
| 384 | |
| 385 | qemu_register_reset(ppc_booke_timer_reset_handle, cpu); |
| 386 | } |