| 1 | /* |
| 2 | * Test Machine for the IBM PPE42 processor |
| 3 | * |
| 4 | * Copyright (c) 2025, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "qemu/units.h" |
| 11 | #include "qemu/error-report.h" |
| 12 | #include "system/address-spaces.h" |
| 13 | #include "hw/core/boards.h" |
| 14 | #include "hw/ppc/ppc.h" |
| 15 | #include "system/system.h" |
| 16 | #include "system/reset.h" |
| 17 | #include "system/kvm.h" |
| 18 | #include "qapi/error.h" |
| 19 | |
| 20 | #define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine") |
| 21 | typedef MachineClass Ppe42MachineClass; |
| 22 | typedef struct Ppe42MachineState Ppe42MachineState; |
| 23 | DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass, |
| 24 | PPE42_MACHINE, TYPE_PPE42_MACHINE) |
| 25 | |
| 26 | struct Ppe42MachineState { |
| 27 | MachineState parent_obj; |
| 28 | |
| 29 | PowerPCCPU cpu; |
| 30 | }; |
| 31 | |
| 32 | static void main_cpu_reset(void *opaque) |
| 33 | { |
| 34 | PowerPCCPU *cpu = opaque; |
| 35 | |
| 36 | cpu_reset(CPU(cpu)); |
| 37 | } |
| 38 | |
| 39 | static void ppe42_machine_init(MachineState *machine) |
| 40 | { |
| 41 | Ppe42MachineState *pms = PPE42_MACHINE(machine); |
| 42 | PowerPCCPU *cpu = &pms->cpu; |
| 43 | |
| 44 | if (kvm_enabled()) { |
| 45 | error_report("machine %s does not support the KVM accelerator", |
| 46 | MACHINE_GET_CLASS(machine)->name); |
| 47 | exit(EXIT_FAILURE); |
| 48 | } |
| 49 | if (machine->ram_size > 512 * KiB) { |
| 50 | error_report("RAM size more than 512 KiB is not supported"); |
| 51 | exit(1); |
| 52 | } |
| 53 | |
| 54 | /* init CPU */ |
| 55 | object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type); |
| 56 | if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) { |
| 57 | return; |
| 58 | } |
| 59 | |
| 60 | qemu_register_reset(main_cpu_reset, cpu); |
| 61 | |
| 62 | /* This sets the decrementer timebase */ |
| 63 | ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE); |
| 64 | |
| 65 | /* RAM */ |
| 66 | memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram); |
| 67 | } |
| 68 | |
| 69 | |
| 70 | static void ppe42_machine_class_init(ObjectClass *oc, const void *data) |
| 71 | { |
| 72 | MachineClass *mc = MACHINE_CLASS(oc); |
| 73 | static const char * const valid_cpu_types[] = { |
| 74 | POWERPC_CPU_TYPE_NAME("PPE42"), |
| 75 | POWERPC_CPU_TYPE_NAME("PPE42X"), |
| 76 | POWERPC_CPU_TYPE_NAME("PPE42XM"), |
| 77 | NULL, |
| 78 | }; |
| 79 | |
| 80 | mc->desc = "PPE42 Test Machine"; |
| 81 | mc->init = ppe42_machine_init; |
| 82 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM"); |
| 83 | mc->valid_cpu_types = valid_cpu_types; |
| 84 | mc->default_ram_id = "ram"; |
| 85 | mc->default_ram_size = 512 * KiB; |
| 86 | } |
| 87 | |
| 88 | static const TypeInfo ppe42_machine_info = { |
| 89 | .name = TYPE_PPE42_MACHINE, |
| 90 | .parent = TYPE_MACHINE, |
| 91 | .instance_size = sizeof(Ppe42MachineState), |
| 92 | .class_init = ppe42_machine_class_init, |
| 93 | .class_size = sizeof(Ppe42MachineClass), |
| 94 | }; |
| 95 | |
| 96 | static void ppe42_machine_register_types(void) |
| 97 | { |
| 98 | type_register_static(&ppe42_machine_info); |
| 99 | } |
| 100 | |
| 101 | type_init(ppe42_machine_register_types); |