| 1 | /* |
| 2 | * QEMU PPC PREP hardware System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 5 | * Copyright (c) 2017 Hervé Poussineau |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "hw/rtc/m48t59.h" |
| 28 | #include "hw/block/fdc.h" |
| 29 | #include "net/net.h" |
| 30 | #include "hw/isa/isa.h" |
| 31 | #include "hw/pci/pci.h" |
| 32 | #include "hw/pci/pci_host.h" |
| 33 | #include "hw/ppc/ppc.h" |
| 34 | #include "hw/core/boards.h" |
| 35 | #include "qapi/error.h" |
| 36 | #include "qemu/error-report.h" |
| 37 | #include "qemu/log.h" |
| 38 | #include "qemu/datadir.h" |
| 39 | #include "hw/core/loader.h" |
| 40 | #include "hw/rtc/mc146818rtc.h" |
| 41 | #include "hw/isa/pc87312.h" |
| 42 | #include "hw/core/qdev-properties.h" |
| 43 | #include "exec/target_page.h" |
| 44 | #include "system/kvm.h" |
| 45 | #include "system/reset.h" |
| 46 | #include "trace.h" |
| 47 | #include "elf.h" |
| 48 | #include "qemu/units.h" |
| 49 | |
| 50 | /* SMP is not enabled, for now */ |
| 51 | #define MAX_CPUS 1 |
| 52 | |
| 53 | #define CFG_ADDR 0xf0000510 |
| 54 | |
| 55 | #define KERNEL_LOAD_ADDR 0x01000000 |
| 56 | #define INITRD_LOAD_ADDR 0x01800000 |
| 57 | |
| 58 | #define BIOS_ADDR 0xfff00000 |
| 59 | #define BIOS_SIZE (1 * MiB) |
| 60 | #define NVRAM_SIZE 0x2000 |
| 61 | |
| 62 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 63 | Error **errp) |
| 64 | { |
| 65 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 66 | } |
| 67 | |
| 68 | static void ppc_prep_reset(void *opaque) |
| 69 | { |
| 70 | PowerPCCPU *cpu = opaque; |
| 71 | |
| 72 | cpu_reset(CPU(cpu)); |
| 73 | cpu_ppc_tb_reset(&cpu->env); |
| 74 | } |
| 75 | |
| 76 | |
| 77 | /*****************************************************************************/ |
| 78 | /* NVRAM helpers */ |
| 79 | static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) |
| 80 | { |
| 81 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
| 82 | return (k->read)(nvram, addr); |
| 83 | } |
| 84 | |
| 85 | static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) |
| 86 | { |
| 87 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
| 88 | (k->write)(nvram, addr, val); |
| 89 | } |
| 90 | |
| 91 | static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) |
| 92 | { |
| 93 | nvram_write(nvram, addr, value); |
| 94 | } |
| 95 | |
| 96 | static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) |
| 97 | { |
| 98 | return nvram_read(nvram, addr); |
| 99 | } |
| 100 | |
| 101 | static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) |
| 102 | { |
| 103 | nvram_write(nvram, addr, value >> 8); |
| 104 | nvram_write(nvram, addr + 1, value & 0xFF); |
| 105 | } |
| 106 | |
| 107 | static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) |
| 108 | { |
| 109 | uint16_t tmp; |
| 110 | |
| 111 | tmp = nvram_read(nvram, addr) << 8; |
| 112 | tmp |= nvram_read(nvram, addr + 1); |
| 113 | |
| 114 | return tmp; |
| 115 | } |
| 116 | |
| 117 | static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) |
| 118 | { |
| 119 | nvram_write(nvram, addr, value >> 24); |
| 120 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| 121 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
| 122 | nvram_write(nvram, addr + 3, value & 0xFF); |
| 123 | } |
| 124 | |
| 125 | static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, |
| 126 | uint32_t max) |
| 127 | { |
| 128 | int i; |
| 129 | |
| 130 | for (i = 0; i < max && str[i] != '\0'; i++) { |
| 131 | nvram_write(nvram, addr + i, str[i]); |
| 132 | } |
| 133 | nvram_write(nvram, addr + i, str[i]); |
| 134 | nvram_write(nvram, addr + max - 1, '\0'); |
| 135 | } |
| 136 | |
| 137 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) |
| 138 | { |
| 139 | uint16_t tmp; |
| 140 | uint16_t pd, pd1, pd2; |
| 141 | |
| 142 | tmp = prev >> 8; |
| 143 | pd = prev ^ value; |
| 144 | pd1 = pd & 0x000F; |
| 145 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
| 146 | tmp ^= (pd1 << 3) | (pd1 << 8); |
| 147 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
| 148 | |
| 149 | return tmp; |
| 150 | } |
| 151 | |
| 152 | static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) |
| 153 | { |
| 154 | uint32_t i; |
| 155 | uint16_t crc = 0xFFFF; |
| 156 | int odd; |
| 157 | |
| 158 | odd = count & 1; |
| 159 | count &= ~1; |
| 160 | for (i = 0; i != count; i++) { |
| 161 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
| 162 | } |
| 163 | if (odd) { |
| 164 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
| 165 | } |
| 166 | |
| 167 | return crc; |
| 168 | } |
| 169 | |
| 170 | #define CMDLINE_ADDR 0x017ff000 |
| 171 | |
| 172 | static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, |
| 173 | const char *arch, |
| 174 | uint32_t RAM_size, int boot_device, |
| 175 | uint32_t kernel_image, uint32_t kernel_size, |
| 176 | const char *cmdline, |
| 177 | uint32_t initrd_image, uint32_t initrd_size, |
| 178 | uint32_t NVRAM_image, |
| 179 | int width, int height, int depth) |
| 180 | { |
| 181 | uint16_t crc; |
| 182 | |
| 183 | /* Set parameters for Open Hack'Ware BIOS */ |
| 184 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 185 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
| 186 | NVRAM_set_word(nvram, 0x14, NVRAM_size); |
| 187 | NVRAM_set_string(nvram, 0x20, arch, 16); |
| 188 | NVRAM_set_lword(nvram, 0x30, RAM_size); |
| 189 | NVRAM_set_byte(nvram, 0x34, boot_device); |
| 190 | NVRAM_set_lword(nvram, 0x38, kernel_image); |
| 191 | NVRAM_set_lword(nvram, 0x3C, kernel_size); |
| 192 | if (cmdline) { |
| 193 | /* XXX: put the cmdline in NVRAM too ? */ |
| 194 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, |
| 195 | cmdline); |
| 196 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
| 197 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); |
| 198 | } else { |
| 199 | NVRAM_set_lword(nvram, 0x40, 0); |
| 200 | NVRAM_set_lword(nvram, 0x44, 0); |
| 201 | } |
| 202 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
| 203 | NVRAM_set_lword(nvram, 0x4C, initrd_size); |
| 204 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); |
| 205 | |
| 206 | NVRAM_set_word(nvram, 0x54, width); |
| 207 | NVRAM_set_word(nvram, 0x56, height); |
| 208 | NVRAM_set_word(nvram, 0x58, depth); |
| 209 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
| 210 | NVRAM_set_word(nvram, 0xFC, crc); |
| 211 | |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) |
| 216 | { |
| 217 | uint16_t checksum = *(uint16_t *)opaque; |
| 218 | |
| 219 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { |
| 220 | MC146818RtcState *rtc = MC146818_RTC(dev); |
| 221 | mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff); |
| 222 | mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff); |
| 223 | mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8); |
| 224 | mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8); |
| 225 | |
| 226 | object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), |
| 227 | "date"); |
| 228 | } |
| 229 | return 0; |
| 230 | } |
| 231 | |
| 232 | static void ibm_40p_init(MachineState *machine) |
| 233 | { |
| 234 | const char *bios_name = machine->firmware ?: "openbios-ppc"; |
| 235 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 236 | CPUPPCState *env = NULL; |
| 237 | uint16_t cmos_checksum; |
| 238 | PowerPCCPU *cpu; |
| 239 | DeviceState *dev, *i82378_dev; |
| 240 | SysBusDevice *pcihost, *s; |
| 241 | Nvram *m48t59 = NULL; |
| 242 | PCIBus *pci_bus; |
| 243 | ISADevice *isa_dev; |
| 244 | ISABus *isa_bus; |
| 245 | void *fw_cfg; |
| 246 | MemoryRegion *bios = g_new(MemoryRegion, 1); |
| 247 | char *filename; |
| 248 | ssize_t bios_size = -1; |
| 249 | uint32_t kernel_base = 0, initrd_base = 0; |
| 250 | long kernel_size = 0, initrd_size = 0; |
| 251 | char boot_device; |
| 252 | |
| 253 | if (kvm_enabled()) { |
| 254 | error_report("machine %s does not support the KVM accelerator", |
| 255 | MACHINE_GET_CLASS(machine)->name); |
| 256 | exit(EXIT_FAILURE); |
| 257 | } |
| 258 | |
| 259 | /* init CPU */ |
| 260 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
| 261 | env = &cpu->env; |
| 262 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
| 263 | error_report("only 6xx bus is supported on this machine"); |
| 264 | exit(1); |
| 265 | } |
| 266 | |
| 267 | /* Set time-base frequency to 100 Mhz */ |
| 268 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 269 | qemu_register_reset(ppc_prep_reset, cpu); |
| 270 | |
| 271 | /* allocate and load firmware */ |
| 272 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 273 | if (!filename) { |
| 274 | error_report("Could not find bios image '%s'", bios_name); |
| 275 | exit(1); |
| 276 | } |
| 277 | memory_region_init_rom(bios, NULL, "bios", BIOS_SIZE, &error_fatal); |
| 278 | memory_region_add_subregion(get_system_memory(), BIOS_ADDR, bios); |
| 279 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
| 280 | ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 281 | if (bios_size < 0) { |
| 282 | bios_size = load_image_targphys(filename, BIOS_ADDR, BIOS_SIZE, |
| 283 | &error_fatal); |
| 284 | } |
| 285 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
| 286 | error_report("Could not load bios image '%s'", filename); |
| 287 | return; |
| 288 | } |
| 289 | g_free(filename); |
| 290 | |
| 291 | /* PCI host */ |
| 292 | dev = qdev_new("raven-pcihost"); |
| 293 | pcihost = SYS_BUS_DEVICE(dev); |
| 294 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); |
| 295 | sysbus_realize_and_unref(pcihost, &error_fatal); |
| 296 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
| 297 | if (!pci_bus) { |
| 298 | error_report("could not create PCI host controller"); |
| 299 | exit(1); |
| 300 | } |
| 301 | |
| 302 | /* PCI -> ISA bridge */ |
| 303 | i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378")); |
| 304 | qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); |
| 305 | qdev_connect_gpio_out(i82378_dev, 0, |
| 306 | qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); |
| 307 | |
| 308 | sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); |
| 309 | isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); |
| 310 | |
| 311 | /* system control ports */ |
| 312 | isa_dev = isa_new("prep-systemio"); |
| 313 | dev = DEVICE(isa_dev); |
| 314 | qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); |
| 315 | qdev_prop_set_uint32(dev, "equipment", 0xc0); |
| 316 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
| 317 | |
| 318 | /* Memory controller */ |
| 319 | isa_dev = isa_new("rs6000-mc"); |
| 320 | dev = DEVICE(isa_dev); |
| 321 | qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); |
| 322 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
| 323 | |
| 324 | /* RTC */ |
| 325 | isa_dev = isa_new(TYPE_MC146818_RTC); |
| 326 | dev = DEVICE(isa_dev); |
| 327 | qdev_prop_set_int32(dev, "base_year", 1900); |
| 328 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
| 329 | |
| 330 | /* initialize CMOS checksums */ |
| 331 | cmos_checksum = 0x6aa9; |
| 332 | qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, |
| 333 | &cmos_checksum); |
| 334 | |
| 335 | /* add some more devices */ |
| 336 | if (defaults_enabled()) { |
| 337 | m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); |
| 338 | |
| 339 | isa_dev = isa_new("cs4231a"); |
| 340 | dev = DEVICE(isa_dev); |
| 341 | qdev_prop_set_uint32(dev, "iobase", 0x830); |
| 342 | qdev_prop_set_uint32(dev, "irq", 10); |
| 343 | if (machine->audiodev) { |
| 344 | qdev_prop_set_string(dev, "audiodev", machine->audiodev); |
| 345 | } |
| 346 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
| 347 | |
| 348 | isa_dev = isa_new("pc87312"); |
| 349 | dev = DEVICE(isa_dev); |
| 350 | qdev_prop_set_uint32(dev, "config", 12); |
| 351 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
| 352 | |
| 353 | dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810")); |
| 354 | lsi53c8xx_handle_legacy_cmdline(dev); |
| 355 | qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); |
| 356 | |
| 357 | /* XXX: s3-trio at PCI_DEVFN(2, 0) */ |
| 358 | pci_vga_init(pci_bus); |
| 359 | |
| 360 | /* First PCNET device at PCI_DEVFN(3, 0) */ |
| 361 | pci_init_nic_in_slot(pci_bus, mc->default_nic, NULL, "3"); |
| 362 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 363 | } |
| 364 | |
| 365 | /* Prepare firmware configuration for OpenBIOS */ |
| 366 | dev = qdev_new(TYPE_FW_CFG_MEM); |
| 367 | fw_cfg = FW_CFG(dev); |
| 368 | qdev_prop_set_uint32(dev, "data_width", 1); |
| 369 | qdev_prop_set_bit(dev, "dma_enabled", false); |
| 370 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
| 371 | OBJECT(fw_cfg)); |
| 372 | s = SYS_BUS_DEVICE(dev); |
| 373 | sysbus_realize_and_unref(s, &error_fatal); |
| 374 | sysbus_mmio_map(s, 0, CFG_ADDR); |
| 375 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); |
| 376 | |
| 377 | if (machine->kernel_filename) { |
| 378 | /* load kernel */ |
| 379 | kernel_base = KERNEL_LOAD_ADDR; |
| 380 | kernel_size = load_image_targphys(machine->kernel_filename, |
| 381 | kernel_base, |
| 382 | machine->ram_size - kernel_base, |
| 383 | &error_fatal); |
| 384 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
| 385 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 386 | /* load initrd */ |
| 387 | if (machine->initrd_filename) { |
| 388 | initrd_base = INITRD_LOAD_ADDR; |
| 389 | initrd_size = load_image_targphys(machine->initrd_filename, |
| 390 | initrd_base, |
| 391 | machine->ram_size - initrd_base, |
| 392 | &error_fatal); |
| 393 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); |
| 394 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 395 | } |
| 396 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { |
| 397 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
| 398 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
| 399 | machine->kernel_cmdline); |
| 400 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
| 401 | machine->kernel_cmdline); |
| 402 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
| 403 | strlen(machine->kernel_cmdline) + 1); |
| 404 | } |
| 405 | boot_device = 'm'; |
| 406 | } else { |
| 407 | boot_device = machine->boot_config.order[0]; |
| 408 | } |
| 409 | |
| 410 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
| 411 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
| 412 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); |
| 413 | |
| 414 | if (!graphic_width) { |
| 415 | graphic_width = 800; |
| 416 | } |
| 417 | if (!graphic_height) { |
| 418 | graphic_height = 600; |
| 419 | } |
| 420 | if (!graphic_depth) { |
| 421 | graphic_depth = 32; |
| 422 | } |
| 423 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); |
| 424 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); |
| 425 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); |
| 426 | |
| 427 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); |
| 428 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); |
| 429 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 430 | |
| 431 | /* Prepare firmware configuration for Open Hack'Ware */ |
| 432 | if (m48t59) { |
| 433 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, |
| 434 | boot_device, |
| 435 | kernel_base, kernel_size, |
| 436 | machine->kernel_cmdline, |
| 437 | initrd_base, initrd_size, |
| 438 | /* XXX: need an option to load a NVRAM image */ |
| 439 | 0, |
| 440 | graphic_width, graphic_height, graphic_depth); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | static void ibm_40p_machine_init(MachineClass *mc) |
| 445 | { |
| 446 | mc->desc = "IBM RS/6000 7020 (40p)", |
| 447 | mc->init = ibm_40p_init; |
| 448 | mc->max_cpus = 1; |
| 449 | mc->default_ram_size = 128 * MiB; |
| 450 | mc->block_default_type = IF_SCSI; |
| 451 | mc->default_boot_order = "c"; |
| 452 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); |
| 453 | mc->default_display = "std"; |
| 454 | mc->default_nic = "pcnet"; |
| 455 | |
| 456 | machine_add_audiodev_property(mc); |
| 457 | } |
| 458 | |
| 459 | DEFINE_MACHINE("40p", ibm_40p_machine_init) |