| 1 | /* |
| 2 | * QEMU aCube Sam460ex board emulation |
| 3 | * |
| 4 | * Copyright (c) 2012 François Revol |
| 5 | * Copyright (c) 2016-2019 BALATON Zoltan |
| 6 | * |
| 7 | * This file is derived from hw/ppc440_bamboo.c, |
| 8 | * the copyright for that material belongs to the original owners. |
| 9 | * |
| 10 | * This work is licensed under the GNU GPL license version 2 or later. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | #include "qemu/units.h" |
| 16 | #include "qemu/datadir.h" |
| 17 | #include "qemu/error-report.h" |
| 18 | #include "qapi/error.h" |
| 19 | #include "hw/core/boards.h" |
| 20 | #include "system/kvm.h" |
| 21 | #include "kvm_ppc.h" |
| 22 | #include "system/device_tree.h" |
| 23 | #include "system/block-backend.h" |
| 24 | #include "exec/page-protection.h" |
| 25 | #include "hw/core/loader.h" |
| 26 | #include "elf.h" |
| 27 | #include "system/memory.h" |
| 28 | #include "ppc440.h" |
| 29 | #include "hw/pci-host/ppc4xx.h" |
| 30 | #include "hw/block/flash.h" |
| 31 | #include "system/system.h" |
| 32 | #include "system/reset.h" |
| 33 | #include "hw/core/sysbus.h" |
| 34 | #include "hw/char/serial-mm.h" |
| 35 | #include "hw/i2c/ppc4xx_i2c.h" |
| 36 | #include "hw/i2c/smbus_eeprom.h" |
| 37 | #include "hw/ide/pci.h" |
| 38 | #include "hw/usb/hcd-ehci.h" |
| 39 | #include "hw/ppc/fdt.h" |
| 40 | #include "hw/core/qdev-properties.h" |
| 41 | #include "hw/intc/ppc-uic.h" |
| 42 | |
| 43 | #include <libfdt.h> |
| 44 | |
| 45 | #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" |
| 46 | #define UBOOT_FILENAME "u-boot-sam460.bin" |
| 47 | |
| 48 | #define PCIE0_DCRN_BASE 0x100 |
| 49 | #define PCIE1_DCRN_BASE 0x120 |
| 50 | |
| 51 | /* from Sam460 U-Boot include/configs/Sam460ex.h */ |
| 52 | #define FLASH_BASE 0xfff00000 |
| 53 | #define FLASH_BASE_H 0x4 |
| 54 | #define FLASH_SIZE (1 * MiB) |
| 55 | #define UBOOT_LOAD_BASE 0xfff80000 |
| 56 | #define UBOOT_SIZE 0x00080000 |
| 57 | #define UBOOT_ENTRY 0xfffffffc |
| 58 | |
| 59 | /* from U-Boot */ |
| 60 | #define EPAPR_MAGIC (0x45504150) |
| 61 | #define KERNEL_ADDR 0x1000000 |
| 62 | #define FDT_ADDR 0x1800000 |
| 63 | #define RAMDISK_ADDR 0x1900000 |
| 64 | |
| 65 | /* Sam460ex IRQ MAP: |
| 66 | IRQ0 = ETH_INT |
| 67 | IRQ1 = FPGA_INT |
| 68 | IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) |
| 69 | IRQ3 = FPGA_INT2 |
| 70 | IRQ11 = RTC_INT |
| 71 | IRQ12 = SM502_INT |
| 72 | */ |
| 73 | |
| 74 | #define CPU_FREQ 1150000000 |
| 75 | #define PLB_FREQ 230000000 |
| 76 | #define OPB_FREQ 115000000 |
| 77 | #define EBC_FREQ 115000000 |
| 78 | #define UART_FREQ 11059200 |
| 79 | |
| 80 | struct boot_info { |
| 81 | uint32_t dt_base; |
| 82 | uint32_t dt_size; |
| 83 | uint32_t entry; |
| 84 | }; |
| 85 | |
| 86 | static int sam460ex_load_uboot(void) |
| 87 | { |
| 88 | /* |
| 89 | * This first creates 1MiB of flash memory mapped at the end of |
| 90 | * the 32-bit address space (0xFFF00000..0xFFFFFFFF). |
| 91 | * |
| 92 | * If_PFLASH unit 0 is defined, the flash memory is initialized |
| 93 | * from that block backend. |
| 94 | * |
| 95 | * Else, it's initialized to zero. And then 512KiB of ROM get |
| 96 | * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), |
| 97 | * initialized from UBOOT_FILENAME. |
| 98 | * |
| 99 | * This doesn't smell right. |
| 100 | * |
| 101 | * The physical hardware appears to have 512KiB flash memory. |
| 102 | * |
| 103 | * TODO Figure out what we really need here, and clean this up. |
| 104 | */ |
| 105 | |
| 106 | DriveInfo *dinfo; |
| 107 | |
| 108 | dinfo = drive_get(IF_PFLASH, 0, 0); |
| 109 | if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), |
| 110 | "sam460ex.flash", FLASH_SIZE, |
| 111 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
| 112 | 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { |
| 113 | error_report("Error registering flash memory"); |
| 114 | /* XXX: return an error instead? */ |
| 115 | exit(1); |
| 116 | } |
| 117 | |
| 118 | if (!dinfo) { |
| 119 | /*error_report("No flash image given with the 'pflash' parameter," |
| 120 | " using default u-boot image");*/ |
| 121 | rom_add_file_fixed(UBOOT_FILENAME, |
| 122 | UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), |
| 123 | -1); |
| 124 | } |
| 125 | |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | static int sam460ex_load_device_tree(MachineState *machine, |
| 130 | hwaddr addr, |
| 131 | hwaddr initrd_base, |
| 132 | hwaddr initrd_size) |
| 133 | { |
| 134 | uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; |
| 135 | char *filename; |
| 136 | int fdt_size; |
| 137 | void *fdt; |
| 138 | uint32_t tb_freq = CPU_FREQ; |
| 139 | uint32_t clock_freq = CPU_FREQ; |
| 140 | int offset; |
| 141 | |
| 142 | filename = qemu_find_file(QEMU_FILE_TYPE_DTB, BINARY_DEVICE_TREE_FILE); |
| 143 | if (!filename) { |
| 144 | error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); |
| 145 | exit(1); |
| 146 | } |
| 147 | fdt = load_device_tree(filename, &fdt_size); |
| 148 | if (!fdt) { |
| 149 | error_report("Couldn't load dtb file `%s'", filename); |
| 150 | g_free(filename); |
| 151 | exit(1); |
| 152 | } |
| 153 | g_free(filename); |
| 154 | |
| 155 | /* Manipulate device tree in memory. */ |
| 156 | |
| 157 | qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, |
| 158 | sizeof(mem_reg_property)); |
| 159 | |
| 160 | /* default FDT doesn't have a /chosen node... */ |
| 161 | qemu_fdt_add_subnode(fdt, "/chosen"); |
| 162 | |
| 163 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); |
| 164 | |
| 165 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
| 166 | (initrd_base + initrd_size)); |
| 167 | |
| 168 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
| 169 | machine->kernel_cmdline); |
| 170 | |
| 171 | /* Copy data from the host device tree into the guest. Since the guest can |
| 172 | * directly access the timebase without host involvement, we must expose |
| 173 | * the correct frequencies. */ |
| 174 | if (kvm_enabled()) { |
| 175 | tb_freq = kvmppc_get_tbfreq(); |
| 176 | clock_freq = kvmppc_get_clockfreq(); |
| 177 | } |
| 178 | |
| 179 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", |
| 180 | clock_freq); |
| 181 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", |
| 182 | tb_freq); |
| 183 | |
| 184 | /* Remove cpm node if it exists (it is not emulated) */ |
| 185 | offset = fdt_path_offset(fdt, "/cpm"); |
| 186 | if (offset >= 0) { |
| 187 | _FDT(fdt_nop_node(fdt, offset)); |
| 188 | } |
| 189 | |
| 190 | /* set serial port clocks */ |
| 191 | offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); |
| 192 | while (offset >= 0) { |
| 193 | _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); |
| 194 | offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); |
| 195 | } |
| 196 | |
| 197 | /* some more clocks */ |
| 198 | qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", |
| 199 | PLB_FREQ); |
| 200 | qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", |
| 201 | OPB_FREQ); |
| 202 | qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", |
| 203 | EBC_FREQ); |
| 204 | |
| 205 | rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
| 206 | |
| 207 | /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ |
| 208 | machine->fdt = fdt; |
| 209 | |
| 210 | return fdt_size; |
| 211 | } |
| 212 | |
| 213 | static void main_cpu_reset(void *opaque) |
| 214 | { |
| 215 | PowerPCCPU *cpu = opaque; |
| 216 | CPUPPCState *env = &cpu->env; |
| 217 | struct boot_info *bi = env->load_info; |
| 218 | |
| 219 | cpu_reset(CPU(cpu)); |
| 220 | |
| 221 | /* |
| 222 | * On reset the flash is mapped by a shadow TLB, but since we |
| 223 | * don't implement them we need to use the same values U-Boot |
| 224 | * will use to avoid a fault. |
| 225 | * either we have a kernel to boot or we jump to U-Boot |
| 226 | */ |
| 227 | if (bi->entry != UBOOT_ENTRY) { |
| 228 | env->gpr[1] = (16 * MiB) - 8; |
| 229 | env->gpr[3] = FDT_ADDR; |
| 230 | env->nip = bi->entry; |
| 231 | |
| 232 | /* Create a mapping for the kernel. */ |
| 233 | booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1 << 31); |
| 234 | env->gpr[6] = EPAPR_MAGIC; |
| 235 | env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ |
| 236 | |
| 237 | } else { |
| 238 | env->nip = UBOOT_ENTRY; |
| 239 | /* Create a mapping for U-Boot. */ |
| 240 | booke_set_tlb(&env->tlb.tlbe[0], 0xf0000000, 0xf0000000, 0x10000000); |
| 241 | env->tlb.tlbe[0].RPN |= 4; |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | static void sam460ex_init(MachineState *machine) |
| 246 | { |
| 247 | MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); |
| 248 | DeviceState *uic[4]; |
| 249 | int i; |
| 250 | PCIBus *pci_bus; |
| 251 | USBBus *usb_bus; |
| 252 | PowerPCCPU *cpu; |
| 253 | CPUPPCState *env; |
| 254 | I2CBus *i2c; |
| 255 | hwaddr entry = UBOOT_ENTRY; |
| 256 | target_long initrd_size = 0; |
| 257 | DeviceState *dev; |
| 258 | SysBusDevice *sbdev; |
| 259 | struct boot_info *boot_info; |
| 260 | uint8_t *spd_data; |
| 261 | int success; |
| 262 | |
| 263 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
| 264 | env = &cpu->env; |
| 265 | if (env->mmu_model != POWERPC_MMU_BOOKE) { |
| 266 | error_report("Only MMU model BookE is supported by this machine."); |
| 267 | exit(1); |
| 268 | } |
| 269 | |
| 270 | qemu_register_reset(main_cpu_reset, cpu); |
| 271 | boot_info = g_malloc0(sizeof(*boot_info)); |
| 272 | env->load_info = boot_info; |
| 273 | |
| 274 | ppc_booke_timers_init(cpu, CPU_FREQ, 0); |
| 275 | ppc_dcr_init(env, NULL, NULL); |
| 276 | |
| 277 | /* PLB arbitrer */ |
| 278 | dev = qdev_new(TYPE_PPC4xx_PLB); |
| 279 | ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); |
| 280 | object_unref(OBJECT(dev)); |
| 281 | |
| 282 | /* interrupt controllers */ |
| 283 | for (i = 0; i < ARRAY_SIZE(uic); i++) { |
| 284 | /* |
| 285 | * UICs 1, 2 and 3 are cascaded through UIC 0. |
| 286 | * input_ints[n] is the interrupt number on UIC 0 which |
| 287 | * the INT output of UIC n is connected to. The CINT output |
| 288 | * of UIC n connects to input_ints[n] + 1. |
| 289 | * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's |
| 290 | * INT and CINT outputs are connected to the CPU. |
| 291 | */ |
| 292 | const int input_ints[] = { -1, 30, 10, 16 }; |
| 293 | |
| 294 | uic[i] = qdev_new(TYPE_PPC_UIC); |
| 295 | qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); |
| 296 | ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); |
| 297 | object_unref(OBJECT(uic[i])); |
| 298 | |
| 299 | sbdev = SYS_BUS_DEVICE(uic[i]); |
| 300 | if (i == 0) { |
| 301 | sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, |
| 302 | qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); |
| 303 | sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, |
| 304 | qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); |
| 305 | } else { |
| 306 | sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, |
| 307 | qdev_get_gpio_in(uic[0], input_ints[i])); |
| 308 | sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, |
| 309 | qdev_get_gpio_in(uic[0], input_ints[i] + 1)); |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | /* SDRAM controller */ |
| 314 | /* The SoC could also handle 4 GiB but firmware does not work with that. */ |
| 315 | if (machine->ram_size > 2 * GiB) { |
| 316 | error_report("Memory over 2 GiB is not supported"); |
| 317 | exit(1); |
| 318 | } |
| 319 | /* Firmware needs at least 64 MiB */ |
| 320 | if (machine->ram_size < 64 * MiB) { |
| 321 | error_report("Memory below 64 MiB is not supported"); |
| 322 | exit(1); |
| 323 | } |
| 324 | dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); |
| 325 | object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), |
| 326 | &error_abort); |
| 327 | /* |
| 328 | * Put all RAM on first bank because board has one slot |
| 329 | * and firmware only checks that |
| 330 | */ |
| 331 | object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); |
| 332 | ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); |
| 333 | object_unref(OBJECT(dev)); |
| 334 | /* FIXME: does 460EX have ECC interrupts? */ |
| 335 | /* Enable SDRAM memory regions as we may boot without firmware */ |
| 336 | ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev)); |
| 337 | |
| 338 | /* IIC controllers and devices */ |
| 339 | dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, |
| 340 | qdev_get_gpio_in(uic[0], 2)); |
| 341 | i2c = PPC4xx_I2C(dev)->bus; |
| 342 | /* SPD EEPROM on RAM module */ |
| 343 | spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, |
| 344 | machine->ram_size); |
| 345 | spd_data[20] = 4; /* SO-DIMM module */ |
| 346 | smbus_eeprom_init_one(i2c, 0x50, spd_data); |
| 347 | /* RTC */ |
| 348 | i2c_slave_create_simple(i2c, "m41t80", 0x68); |
| 349 | |
| 350 | dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, |
| 351 | qdev_get_gpio_in(uic[0], 3)); |
| 352 | |
| 353 | /* External bus controller */ |
| 354 | dev = qdev_new(TYPE_PPC4xx_EBC); |
| 355 | ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); |
| 356 | object_unref(OBJECT(dev)); |
| 357 | |
| 358 | /* CPR */ |
| 359 | ppc4xx_cpr_init(env); |
| 360 | |
| 361 | /* PLB to AHB bridge */ |
| 362 | ppc4xx_ahb_init(env); |
| 363 | |
| 364 | /* System DCRs */ |
| 365 | ppc4xx_sdr_init(env); |
| 366 | |
| 367 | /* MAL */ |
| 368 | dev = qdev_new(TYPE_PPC4xx_MAL); |
| 369 | qdev_prop_set_uint8(dev, "txc-num", 4); |
| 370 | qdev_prop_set_uint8(dev, "rxc-num", 16); |
| 371 | ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); |
| 372 | object_unref(OBJECT(dev)); |
| 373 | sbdev = SYS_BUS_DEVICE(dev); |
| 374 | for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { |
| 375 | sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); |
| 376 | } |
| 377 | |
| 378 | /* DMA */ |
| 379 | ppc4xx_dma_init(env, 0x200); |
| 380 | |
| 381 | /* 256K of L2 cache as memory */ |
| 382 | ppc4xx_l2sram_init(env); |
| 383 | /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ |
| 384 | memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, |
| 385 | &error_abort); |
| 386 | memory_region_add_subregion(get_system_memory(), 0x400000000LL, |
| 387 | l2cache_ram); |
| 388 | |
| 389 | /* USB */ |
| 390 | sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, |
| 391 | qdev_get_gpio_in(uic[2], 29)); |
| 392 | dev = qdev_new("sysbus-ohci"); |
| 393 | qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); |
| 394 | qdev_prop_set_uint32(dev, "num-ports", 6); |
| 395 | sbdev = SYS_BUS_DEVICE(dev); |
| 396 | sysbus_realize_and_unref(sbdev, &error_fatal); |
| 397 | sysbus_mmio_map(sbdev, 0, 0x4bffd0000); |
| 398 | sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); |
| 399 | usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, |
| 400 | &error_abort)); |
| 401 | usb_create_simple(usb_bus, "usb-kbd"); |
| 402 | usb_create_simple(usb_bus, "usb-mouse"); |
| 403 | |
| 404 | /* PCIe buses */ |
| 405 | dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); |
| 406 | qdev_prop_set_int32(dev, "busnum", 0); |
| 407 | qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE); |
| 408 | object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); |
| 409 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 410 | |
| 411 | dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); |
| 412 | qdev_prop_set_int32(dev, "busnum", 1); |
| 413 | qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE); |
| 414 | object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); |
| 415 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 416 | |
| 417 | /* PCI bus */ |
| 418 | /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ |
| 419 | dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000, |
| 420 | qdev_get_gpio_in(uic[1], 0)); |
| 421 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000); |
| 422 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
| 423 | |
| 424 | /* PCI devices */ |
| 425 | pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); |
| 426 | /* |
| 427 | * SoC has a single SATA port but we don't emulate that |
| 428 | * However, firmware and usual clients have driver for SiI311x |
| 429 | * PCI SATA card so add one for convenience by default |
| 430 | */ |
| 431 | if (defaults_enabled()) { |
| 432 | PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112")); |
| 433 | DriveInfo *di; |
| 434 | |
| 435 | di = drive_get_by_index(IF_IDE, 0); |
| 436 | if (di) { |
| 437 | ide_bus_create_drive(&s->bus[0], 0, di); |
| 438 | } |
| 439 | /* Use index 2 only if 1 does not exist, this allows -cdrom */ |
| 440 | di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2); |
| 441 | if (di) { |
| 442 | ide_bus_create_drive(&s->bus[1], 0, di); |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | /* SoC has 4 UARTs but board has only one wired and two described in fdt */ |
| 447 | if (serial_hd(0) != NULL) { |
| 448 | serial_mm_init(get_system_memory(), 0x4ef600300, 0, |
| 449 | qdev_get_gpio_in(uic[1], 1), |
| 450 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
| 451 | DEVICE_BIG_ENDIAN); |
| 452 | } |
| 453 | if (serial_hd(1) != NULL) { |
| 454 | serial_mm_init(get_system_memory(), 0x4ef600400, 0, |
| 455 | qdev_get_gpio_in(uic[0], 1), |
| 456 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
| 457 | DEVICE_BIG_ENDIAN); |
| 458 | } |
| 459 | |
| 460 | /* Load U-Boot image. */ |
| 461 | if (!machine->kernel_filename) { |
| 462 | success = sam460ex_load_uboot(); |
| 463 | if (success < 0) { |
| 464 | error_report("could not load firmware"); |
| 465 | exit(1); |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | /* Load kernel. */ |
| 470 | if (machine->kernel_filename) { |
| 471 | hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
| 472 | success = load_uimage(machine->kernel_filename, &entry, &loadaddr, |
| 473 | NULL, NULL, NULL); |
| 474 | if (success < 0) { |
| 475 | uint64_t elf_entry; |
| 476 | |
| 477 | success = load_elf(machine->kernel_filename, NULL, NULL, NULL, |
| 478 | &elf_entry, NULL, NULL, NULL, |
| 479 | ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); |
| 480 | entry = elf_entry; |
| 481 | } |
| 482 | /* XXX try again as binary */ |
| 483 | if (success < 0) { |
| 484 | error_report("could not load kernel '%s'", |
| 485 | machine->kernel_filename); |
| 486 | exit(1); |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | /* Load initrd. */ |
| 491 | if (machine->initrd_filename) { |
| 492 | initrd_size = load_image_targphys(machine->initrd_filename, |
| 493 | RAMDISK_ADDR, |
| 494 | machine->ram_size - RAMDISK_ADDR, |
| 495 | &error_fatal); |
| 496 | } |
| 497 | |
| 498 | /* If we're loading a kernel directly, we must load the device tree too. */ |
| 499 | if (machine->kernel_filename) { |
| 500 | int dt_size; |
| 501 | |
| 502 | dt_size = sam460ex_load_device_tree(machine, FDT_ADDR, |
| 503 | RAMDISK_ADDR, initrd_size); |
| 504 | |
| 505 | boot_info->dt_base = FDT_ADDR; |
| 506 | boot_info->dt_size = dt_size; |
| 507 | } |
| 508 | |
| 509 | boot_info->entry = entry; |
| 510 | } |
| 511 | |
| 512 | static void sam460ex_machine_init(MachineClass *mc) |
| 513 | { |
| 514 | mc->desc = "aCube Sam460ex"; |
| 515 | mc->init = sam460ex_init; |
| 516 | mc->block_default_type = IF_IDE; |
| 517 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); |
| 518 | mc->default_ram_size = 512 * MiB; |
| 519 | mc->default_ram_id = "ppc4xx.sdram"; |
| 520 | } |
| 521 | |
| 522 | DEFINE_MACHINE("sam460ex", sam460ex_machine_init) |