| 1 | /* |
| 2 | * QEMU PowerPC pSeries Logical Partition capabilities handling |
| 3 | * |
| 4 | * Copyright (c) 2017 David Gibson, Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qemu/error-report.h" |
| 27 | #include "qapi/error.h" |
| 28 | #include "qapi/visitor.h" |
| 29 | #include "system/hw_accel.h" |
| 30 | #include "target/ppc/cpu.h" |
| 31 | #include "target/ppc/mmu-hash64.h" |
| 32 | #include "cpu-models.h" |
| 33 | #include "kvm_ppc.h" |
| 34 | #include "migration/vmstate.h" |
| 35 | #include "system/tcg.h" |
| 36 | #include "system/hostmem.h" |
| 37 | |
| 38 | #include "hw/ppc/spapr.h" |
| 39 | |
| 40 | typedef struct SpaprCapPossible { |
| 41 | int num; /* size of vals array below */ |
| 42 | const char *help; /* help text for vals */ |
| 43 | /* |
| 44 | * Note: |
| 45 | * - because of the way compatibility is determined vals MUST be ordered |
| 46 | * such that later options are a superset of all preceding options. |
| 47 | * - the order of vals must be preserved, that is their index is important, |
| 48 | * however vals may be added to the end of the list so long as the above |
| 49 | * point is observed |
| 50 | */ |
| 51 | const char *vals[]; |
| 52 | } SpaprCapPossible; |
| 53 | |
| 54 | typedef struct SpaprCapabilityInfo { |
| 55 | const char *name; |
| 56 | const char *description; |
| 57 | int index; |
| 58 | |
| 59 | /* Getter and Setter Function Pointers */ |
| 60 | ObjectPropertyAccessor *get; |
| 61 | ObjectPropertyAccessor *set; |
| 62 | const char *type; |
| 63 | /* Possible values if this is a custom string type */ |
| 64 | SpaprCapPossible *possible; |
| 65 | /* Make sure the virtual hardware can support this capability */ |
| 66 | void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp); |
| 67 | void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu, |
| 68 | uint8_t val, Error **errp); |
| 69 | } SpaprCapabilityInfo; |
| 70 | |
| 71 | static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name, |
| 72 | void *opaque, Error **errp) |
| 73 | { |
| 74 | SpaprCapabilityInfo *cap = opaque; |
| 75 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 76 | bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON; |
| 77 | |
| 78 | visit_type_bool(v, name, &value, errp); |
| 79 | } |
| 80 | |
| 81 | static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name, |
| 82 | void *opaque, Error **errp) |
| 83 | { |
| 84 | SpaprCapabilityInfo *cap = opaque; |
| 85 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 86 | bool value; |
| 87 | |
| 88 | if (!visit_type_bool(v, name, &value, errp)) { |
| 89 | return; |
| 90 | } |
| 91 | |
| 92 | spapr->cmd_line_caps[cap->index] = true; |
| 93 | spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF; |
| 94 | } |
| 95 | |
| 96 | |
| 97 | static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name, |
| 98 | void *opaque, Error **errp) |
| 99 | { |
| 100 | SpaprCapabilityInfo *cap = opaque; |
| 101 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 102 | g_autofree char *val = NULL; |
| 103 | uint8_t value = spapr_get_cap(spapr, cap->index); |
| 104 | |
| 105 | if (value >= cap->possible->num) { |
| 106 | error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name); |
| 107 | return; |
| 108 | } |
| 109 | |
| 110 | val = g_strdup(cap->possible->vals[value]); |
| 111 | |
| 112 | visit_type_str(v, name, &val, errp); |
| 113 | } |
| 114 | |
| 115 | static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name, |
| 116 | void *opaque, Error **errp) |
| 117 | { |
| 118 | SpaprCapabilityInfo *cap = opaque; |
| 119 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 120 | uint8_t i; |
| 121 | g_autofree char *val = NULL; |
| 122 | |
| 123 | if (!visit_type_str(v, name, &val, errp)) { |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | if (!strcmp(val, "?")) { |
| 128 | error_setg(errp, "%s", cap->possible->help); |
| 129 | return; |
| 130 | } |
| 131 | for (i = 0; i < cap->possible->num; i++) { |
| 132 | if (!g_ascii_strcasecmp(val, cap->possible->vals[i])) { |
| 133 | spapr->cmd_line_caps[cap->index] = true; |
| 134 | spapr->eff.caps[cap->index] = i; |
| 135 | return; |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val, |
| 140 | cap->name); |
| 141 | } |
| 142 | |
| 143 | static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name, |
| 144 | void *opaque, Error **errp) |
| 145 | { |
| 146 | SpaprCapabilityInfo *cap = opaque; |
| 147 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 148 | uint8_t val = spapr_get_cap(spapr, cap->index); |
| 149 | uint64_t pagesize = (1ULL << val); |
| 150 | |
| 151 | visit_type_size(v, name, &pagesize, errp); |
| 152 | } |
| 153 | |
| 154 | static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name, |
| 155 | void *opaque, Error **errp) |
| 156 | { |
| 157 | SpaprCapabilityInfo *cap = opaque; |
| 158 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
| 159 | uint64_t pagesize; |
| 160 | uint8_t val; |
| 161 | |
| 162 | if (!visit_type_size(v, name, &pagesize, errp)) { |
| 163 | return; |
| 164 | } |
| 165 | |
| 166 | if (!is_power_of_2(pagesize)) { |
| 167 | error_setg(errp, "cap-%s must be a power of 2", cap->name); |
| 168 | return; |
| 169 | } |
| 170 | |
| 171 | val = ctz64(pagesize); |
| 172 | spapr->cmd_line_caps[cap->index] = true; |
| 173 | spapr->eff.caps[cap->index] = val; |
| 174 | } |
| 175 | |
| 176 | static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) |
| 177 | { |
| 178 | ERRP_GUARD(); |
| 179 | if (!val) { |
| 180 | /* TODO: We don't support disabling htm yet */ |
| 181 | return; |
| 182 | } |
| 183 | if (tcg_enabled()) { |
| 184 | error_setg(errp, "No Transactional Memory support in TCG"); |
| 185 | error_append_hint(errp, "Try appending -machine cap-htm=off\n"); |
| 186 | } else if (kvm_enabled() && !kvmppc_has_cap_htm()) { |
| 187 | error_setg(errp, |
| 188 | "KVM implementation does not support Transactional Memory"); |
| 189 | error_append_hint(errp, "Try appending -machine cap-htm=off\n"); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) |
| 194 | { |
| 195 | ERRP_GUARD(); |
| 196 | CPUPPCState *env = cpu_env(first_cpu); |
| 197 | |
| 198 | if (!val) { |
| 199 | /* TODO: We don't support disabling vsx yet */ |
| 200 | return; |
| 201 | } |
| 202 | /* Allowable CPUs in spapr_cpu_core.c should already have gotten |
| 203 | * rid of anything that doesn't do VMX */ |
| 204 | g_assert(env->insns_flags & PPC_ALTIVEC); |
| 205 | if (!(env->insns_flags2 & PPC2_VSX)) { |
| 206 | error_setg(errp, "VSX support not available"); |
| 207 | error_append_hint(errp, "Try appending -machine cap-vsx=off\n"); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) |
| 212 | { |
| 213 | ERRP_GUARD(); |
| 214 | |
| 215 | if (!val) { |
| 216 | /* TODO: We don't support disabling dfp yet */ |
| 217 | return; |
| 218 | } |
| 219 | if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) { |
| 220 | error_setg(errp, "DFP support not available"); |
| 221 | error_append_hint(errp, "Try appending -machine cap-dfp=off\n"); |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | SpaprCapPossible cap_cfpc_possible = { |
| 226 | .num = 3, |
| 227 | .vals = {"broken", "workaround", "fixed"}, |
| 228 | .help = "broken - no protection, workaround - workaround available," |
| 229 | " fixed - fixed in hardware", |
| 230 | }; |
| 231 | |
| 232 | static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val, |
| 233 | Error **errp) |
| 234 | { |
| 235 | ERRP_GUARD(); |
| 236 | uint8_t kvm_val = kvmppc_get_cap_safe_cache(); |
| 237 | |
| 238 | if (tcg_enabled() && val) { |
| 239 | /* TCG only supports broken, allow other values and print a warning */ |
| 240 | warn_report("TCG doesn't support requested feature, cap-cfpc=%s", |
| 241 | cap_cfpc_possible.vals[val]); |
| 242 | } else if (kvm_enabled() && (val > kvm_val)) { |
| 243 | error_setg(errp, |
| 244 | "Requested safe cache capability level not supported by KVM"); |
| 245 | error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n", |
| 246 | cap_cfpc_possible.vals[kvm_val]); |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | SpaprCapPossible cap_sbbc_possible = { |
| 251 | .num = 3, |
| 252 | .vals = {"broken", "workaround", "fixed"}, |
| 253 | .help = "broken - no protection, workaround - workaround available," |
| 254 | " fixed - fixed in hardware", |
| 255 | }; |
| 256 | |
| 257 | static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val, |
| 258 | Error **errp) |
| 259 | { |
| 260 | ERRP_GUARD(); |
| 261 | uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check(); |
| 262 | |
| 263 | if (tcg_enabled() && val) { |
| 264 | /* TCG only supports broken, allow other values and print a warning */ |
| 265 | warn_report("TCG doesn't support requested feature, cap-sbbc=%s", |
| 266 | cap_sbbc_possible.vals[val]); |
| 267 | } else if (kvm_enabled() && (val > kvm_val)) { |
| 268 | error_setg(errp, |
| 269 | "Requested safe bounds check capability level not supported by KVM"); |
| 270 | error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n", |
| 271 | cap_sbbc_possible.vals[kvm_val]); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | SpaprCapPossible cap_ibs_possible = { |
| 276 | .num = 5, |
| 277 | /* Note workaround only maintained for compatibility */ |
| 278 | .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"}, |
| 279 | .help = "broken - no protection, workaround - count cache flush" |
| 280 | ", fixed-ibs - indirect branch serialisation," |
| 281 | " fixed-ccd - cache count disabled," |
| 282 | " fixed-na - fixed in hardware (no longer applicable)", |
| 283 | }; |
| 284 | |
| 285 | static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr, |
| 286 | uint8_t val, Error **errp) |
| 287 | { |
| 288 | ERRP_GUARD(); |
| 289 | uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch(); |
| 290 | |
| 291 | if (tcg_enabled() && val) { |
| 292 | /* TCG only supports broken, allow other values and print a warning */ |
| 293 | warn_report("TCG doesn't support requested feature, cap-ibs=%s", |
| 294 | cap_ibs_possible.vals[val]); |
| 295 | } else if (kvm_enabled() && (val > kvm_val)) { |
| 296 | error_setg(errp, |
| 297 | "Requested safe indirect branch capability level not supported by KVM"); |
| 298 | error_append_hint(errp, "Try appending -machine cap-ibs=%s\n", |
| 299 | cap_ibs_possible.vals[kvm_val]); |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | #define VALUE_DESC_TRISTATE " (broken, workaround, fixed)" |
| 304 | |
| 305 | bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, |
| 306 | Error **errp) |
| 307 | { |
| 308 | hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]); |
| 309 | |
| 310 | if (!kvmppc_hpt_needs_host_contiguous_pages()) { |
| 311 | return true; |
| 312 | } |
| 313 | |
| 314 | if (maxpagesize > pagesize) { |
| 315 | error_setg(errp, |
| 316 | "Can't support %"HWADDR_PRIu" kiB guest pages with %" |
| 317 | HWADDR_PRIu" kiB host pages with this KVM implementation", |
| 318 | maxpagesize >> 10, pagesize >> 10); |
| 319 | return false; |
| 320 | } |
| 321 | |
| 322 | return true; |
| 323 | } |
| 324 | |
| 325 | static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr, |
| 326 | uint8_t val, Error **errp) |
| 327 | { |
| 328 | if (val < 12) { |
| 329 | error_setg(errp, "Require at least 4kiB hpt-max-page-size"); |
| 330 | return; |
| 331 | } else if (val < 16) { |
| 332 | warn_report("Many guests require at least 64kiB hpt-max-page-size"); |
| 333 | } |
| 334 | |
| 335 | spapr_check_pagesize(spapr, qemu_minrampagesize(), errp); |
| 336 | } |
| 337 | |
| 338 | static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift, |
| 339 | uint32_t pshift) |
| 340 | { |
| 341 | unsigned maxshift = *((unsigned *)opaque); |
| 342 | |
| 343 | assert(pshift >= seg_pshift); |
| 344 | |
| 345 | /* Don't allow the guest to use pages bigger than the configured |
| 346 | * maximum size */ |
| 347 | if (pshift > maxshift) { |
| 348 | return false; |
| 349 | } |
| 350 | |
| 351 | /* For whatever reason, KVM doesn't allow multiple pagesizes |
| 352 | * within a segment, *except* for the case of 16M pages in a 4k or |
| 353 | * 64k segment. Always exclude other cases, so that TCG and KVM |
| 354 | * guests see a consistent environment */ |
| 355 | if ((pshift != seg_pshift) && (pshift != 24)) { |
| 356 | return false; |
| 357 | } |
| 358 | |
| 359 | return true; |
| 360 | } |
| 361 | |
| 362 | static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, |
| 363 | bool (*cb)(void *, uint32_t, uint32_t), |
| 364 | void *opaque) |
| 365 | { |
| 366 | PPCHash64Options *opts = cpu->hash64_opts; |
| 367 | int i; |
| 368 | int n = 0; |
| 369 | bool ci_largepage = false; |
| 370 | |
| 371 | assert(opts); |
| 372 | |
| 373 | n = 0; |
| 374 | for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { |
| 375 | PPCHash64SegmentPageSizes *sps = &opts->sps[i]; |
| 376 | int j; |
| 377 | int m = 0; |
| 378 | |
| 379 | assert(n <= i); |
| 380 | |
| 381 | if (!sps->page_shift) { |
| 382 | break; |
| 383 | } |
| 384 | |
| 385 | for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { |
| 386 | PPCHash64PageSize *ps = &sps->enc[j]; |
| 387 | |
| 388 | assert(m <= j); |
| 389 | if (!ps->page_shift) { |
| 390 | break; |
| 391 | } |
| 392 | |
| 393 | if (cb(opaque, sps->page_shift, ps->page_shift)) { |
| 394 | if (ps->page_shift >= 16) { |
| 395 | ci_largepage = true; |
| 396 | } |
| 397 | sps->enc[m++] = *ps; |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | /* Clear rest of the row */ |
| 402 | for (j = m; j < ARRAY_SIZE(sps->enc); j++) { |
| 403 | memset(&sps->enc[j], 0, sizeof(sps->enc[j])); |
| 404 | } |
| 405 | |
| 406 | if (m) { |
| 407 | n++; |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | /* Clear the rest of the table */ |
| 412 | for (i = n; i < ARRAY_SIZE(opts->sps); i++) { |
| 413 | memset(&opts->sps[i], 0, sizeof(opts->sps[i])); |
| 414 | } |
| 415 | |
| 416 | if (!ci_largepage) { |
| 417 | opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr, |
| 422 | PowerPCCPU *cpu, |
| 423 | uint8_t val, Error **errp) |
| 424 | { |
| 425 | unsigned maxshift = val; |
| 426 | |
| 427 | ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift); |
| 428 | } |
| 429 | |
| 430 | static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr, |
| 431 | uint8_t val, Error **errp) |
| 432 | { |
| 433 | ERRP_GUARD(); |
| 434 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
| 435 | CPUPPCState *env = &cpu->env; |
| 436 | |
| 437 | if (!val) { |
| 438 | /* capability disabled by default */ |
| 439 | return; |
| 440 | } |
| 441 | |
| 442 | if (!(env->insns_flags2 & PPC2_ISA300)) { |
| 443 | error_setg(errp, "Nested-HV only supported on POWER9 and later"); |
| 444 | error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n"); |
| 445 | return; |
| 446 | } |
| 447 | |
| 448 | if (kvm_enabled()) { |
| 449 | if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
| 450 | spapr->max_compat_pvr)) { |
| 451 | error_setg(errp, "Nested-HV only supported on POWER9 and later"); |
| 452 | error_append_hint(errp, |
| 453 | "Try appending -machine max-cpu-compat=power9\n"); |
| 454 | return; |
| 455 | } |
| 456 | |
| 457 | if (!kvmppc_has_cap_nested_kvm_hv()) { |
| 458 | error_setg(errp, |
| 459 | "KVM implementation does not support Nested-HV"); |
| 460 | error_append_hint(errp, |
| 461 | "Try appending -machine cap-nested-hv=off\n"); |
| 462 | } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) { |
| 463 | error_setg(errp, "Error enabling cap-nested-hv with KVM"); |
| 464 | error_append_hint(errp, |
| 465 | "Try appending -machine cap-nested-hv=off\n"); |
| 466 | } |
| 467 | } else if (tcg_enabled()) { |
| 468 | MachineState *ms = MACHINE(spapr); |
| 469 | unsigned int smp_threads = ms->smp.threads; |
| 470 | |
| 471 | /* |
| 472 | * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for |
| 473 | * example, do not necessarily update the correct SPR value on sibling |
| 474 | * threads that are in a different guest/host context. |
| 475 | */ |
| 476 | if (smp_threads > 1) { |
| 477 | error_setg(errp, "TCG does not support nested-HV with SMT"); |
| 478 | error_append_hint(errp, "Try appending -machine cap-nested-hv=off " |
| 479 | "or use threads=1 with -smp\n"); |
| 480 | } |
| 481 | if (spapr_nested_api(spapr) && |
| 482 | spapr_nested_api(spapr) != NESTED_API_KVM_HV) { |
| 483 | error_setg(errp, "Nested-HV APIs are mutually exclusive"); |
| 484 | error_append_hint(errp, "Please use either cap-nested-hv or " |
| 485 | "cap-nested-papr to proceed.\n"); |
| 486 | return; |
| 487 | } else { |
| 488 | spapr->nested.api = NESTED_API_KVM_HV; |
| 489 | } |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static void cap_nested_papr_apply(SpaprMachineState *spapr, |
| 494 | uint8_t val, Error **errp) |
| 495 | { |
| 496 | ERRP_GUARD(); |
| 497 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
| 498 | CPUPPCState *env = &cpu->env; |
| 499 | |
| 500 | if (!val) { |
| 501 | /* capability disabled by default */ |
| 502 | return; |
| 503 | } |
| 504 | |
| 505 | if (tcg_enabled()) { |
| 506 | if (!(env->insns_flags2 & PPC2_ISA300)) { |
| 507 | error_setg(errp, "Nested-PAPR only supported on POWER9 and later"); |
| 508 | error_append_hint(errp, |
| 509 | "Try appending -machine cap-nested-papr=off\n"); |
| 510 | return; |
| 511 | } |
| 512 | if (spapr_nested_api(spapr) && |
| 513 | spapr_nested_api(spapr) != NESTED_API_PAPR) { |
| 514 | error_setg(errp, "Nested-HV APIs are mutually exclusive"); |
| 515 | error_append_hint(errp, "Please use either cap-nested-hv or " |
| 516 | "cap-nested-papr to proceed.\n"); |
| 517 | return; |
| 518 | } else { |
| 519 | spapr->nested.api = NESTED_API_PAPR; |
| 520 | } |
| 521 | } else if (kvm_enabled()) { |
| 522 | error_setg(errp, "KVM implementation does not support Nested-PAPR"); |
| 523 | error_append_hint(errp, |
| 524 | "Try appending -machine cap-nested-papr=off\n"); |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | static void cap_large_decr_apply(SpaprMachineState *spapr, |
| 529 | uint8_t val, Error **errp) |
| 530 | { |
| 531 | ERRP_GUARD(); |
| 532 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
| 533 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 534 | |
| 535 | if (!val) { |
| 536 | return; /* Disabled by default */ |
| 537 | } |
| 538 | |
| 539 | if (tcg_enabled()) { |
| 540 | if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
| 541 | spapr->max_compat_pvr)) { |
| 542 | error_setg(errp, "Large decrementer only supported on POWER9"); |
| 543 | error_append_hint(errp, "Try -cpu POWER9\n"); |
| 544 | return; |
| 545 | } |
| 546 | } else if (kvm_enabled()) { |
| 547 | int kvm_nr_bits = kvmppc_get_cap_large_decr(); |
| 548 | |
| 549 | if (!kvm_nr_bits) { |
| 550 | error_setg(errp, "No large decrementer support"); |
| 551 | error_append_hint(errp, |
| 552 | "Try appending -machine cap-large-decr=off\n"); |
| 553 | } else if (pcc->lrg_decr_bits != kvm_nr_bits) { |
| 554 | error_setg(errp, |
| 555 | "KVM large decrementer size (%d) differs to model (%d)", |
| 556 | kvm_nr_bits, pcc->lrg_decr_bits); |
| 557 | error_append_hint(errp, |
| 558 | "Try appending -machine cap-large-decr=off\n"); |
| 559 | } |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | static void cap_large_decr_cpu_apply(SpaprMachineState *spapr, |
| 564 | PowerPCCPU *cpu, |
| 565 | uint8_t val, Error **errp) |
| 566 | { |
| 567 | ERRP_GUARD(); |
| 568 | CPUPPCState *env = &cpu->env; |
| 569 | target_ulong lpcr = env->spr[SPR_LPCR]; |
| 570 | |
| 571 | if (kvm_enabled()) { |
| 572 | if (kvmppc_enable_cap_large_decr(cpu, val)) { |
| 573 | error_setg(errp, "No large decrementer support"); |
| 574 | error_append_hint(errp, |
| 575 | "Try appending -machine cap-large-decr=off\n"); |
| 576 | } |
| 577 | } |
| 578 | |
| 579 | if (val) { |
| 580 | lpcr |= LPCR_LD; |
| 581 | } else { |
| 582 | lpcr &= ~LPCR_LD; |
| 583 | } |
| 584 | ppc_store_lpcr(cpu, lpcr); |
| 585 | } |
| 586 | |
| 587 | static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val, |
| 588 | Error **errp) |
| 589 | { |
| 590 | ERRP_GUARD(); |
| 591 | uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist(); |
| 592 | |
| 593 | if (tcg_enabled() && val) { |
| 594 | /* TCG doesn't implement anything here, but allow with a warning */ |
| 595 | warn_report("TCG doesn't support requested feature, cap-ccf-assist=on"); |
| 596 | } else if (kvm_enabled() && (val > kvm_val)) { |
| 597 | uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch(); |
| 598 | |
| 599 | if (kvm_ibs == SPAPR_CAP_FIXED_CCD) { |
| 600 | /* |
| 601 | * If we don't have CCF assist on the host, the assist |
| 602 | * instruction is a harmless no-op. It won't correctly |
| 603 | * implement the cache count flush *but* if we have |
| 604 | * count-cache-disabled in the host, that flush is |
| 605 | * unnecessary. So, specifically allow this case. This |
| 606 | * allows us to have better performance on POWER9 DD2.3, |
| 607 | * while still working on POWER9 DD2.2 and POWER8 host |
| 608 | * cpus. |
| 609 | */ |
| 610 | return; |
| 611 | } |
| 612 | error_setg(errp, |
| 613 | "Requested count cache flush assist capability level not supported by KVM"); |
| 614 | error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n"); |
| 615 | } |
| 616 | } |
| 617 | |
| 618 | static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val, |
| 619 | Error **errp) |
| 620 | { |
| 621 | ERRP_GUARD(); |
| 622 | if (!val) { |
| 623 | return; /* Disabled by default */ |
| 624 | } |
| 625 | |
| 626 | if (kvm_enabled()) { |
| 627 | if (!kvmppc_get_fwnmi()) { |
| 628 | error_setg(errp, |
| 629 | "Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM."); |
| 630 | error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n"); |
| 631 | } |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | static void cap_rpt_invalidate_apply(SpaprMachineState *spapr, |
| 636 | uint8_t val, Error **errp) |
| 637 | { |
| 638 | ERRP_GUARD(); |
| 639 | |
| 640 | if (!val) { |
| 641 | /* capability disabled by default */ |
| 642 | return; |
| 643 | } |
| 644 | |
| 645 | if (tcg_enabled()) { |
| 646 | error_setg(errp, "No H_RPT_INVALIDATE support in TCG"); |
| 647 | error_append_hint(errp, |
| 648 | "Try appending -machine cap-rpt-invalidate=off\n"); |
| 649 | } else if (kvm_enabled()) { |
| 650 | if (!kvmppc_has_cap_mmu_radix()) { |
| 651 | error_setg(errp, "H_RPT_INVALIDATE only supported on Radix"); |
| 652 | return; |
| 653 | } |
| 654 | |
| 655 | if (!kvmppc_has_cap_rpt_invalidate()) { |
| 656 | error_setg(errp, |
| 657 | "KVM implementation does not support H_RPT_INVALIDATE"); |
| 658 | error_append_hint(errp, |
| 659 | "Try appending -machine cap-rpt-invalidate=off\n"); |
| 660 | } else { |
| 661 | kvmppc_enable_h_rpt_invalidate(); |
| 662 | } |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | static void cap_ail_mode_3_apply(SpaprMachineState *spapr, |
| 667 | uint8_t val, Error **errp) |
| 668 | { |
| 669 | ERRP_GUARD(); |
| 670 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
| 671 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 672 | |
| 673 | if (!val) { |
| 674 | return; |
| 675 | } |
| 676 | |
| 677 | if (tcg_enabled()) { |
| 678 | /* AIL-3 is only supported on POWER8 and above CPUs. */ |
| 679 | if (!(pcc->insns_flags2 & PPC2_ISA207)) { |
| 680 | error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs"); |
| 681 | error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); |
| 682 | return; |
| 683 | } |
| 684 | } else if (kvm_enabled()) { |
| 685 | if (!kvmppc_supports_ail_3()) { |
| 686 | error_setg(errp, "KVM implementation does not support cap-ail-mode-3"); |
| 687 | error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); |
| 688 | return; |
| 689 | } |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val, |
| 694 | Error **errp) |
| 695 | { |
| 696 | ERRP_GUARD(); |
| 697 | |
| 698 | if (!val) { |
| 699 | return; /* Disable by default */ |
| 700 | } |
| 701 | |
| 702 | if (!ppc_type_check_compat(MACHINE(spapr)->cpu_type, |
| 703 | CPU_POWERPC_LOGICAL_3_10, 0, |
| 704 | spapr->max_compat_pvr)) { |
| 705 | error_setg(errp, "DAWR1 supported only on POWER10 and later CPUs"); |
| 706 | error_append_hint(errp, "Try appending -machine cap-dawr1=off\n"); |
| 707 | return; |
| 708 | } |
| 709 | |
| 710 | if (kvm_enabled()) { |
| 711 | if (!kvmppc_has_cap_dawr1()) { |
| 712 | error_setg(errp, "DAWR1 not supported by KVM."); |
| 713 | error_append_hint(errp, "Try appending -machine cap-dawr1=off"); |
| 714 | } else if (kvmppc_set_cap_dawr1(val) < 0) { |
| 715 | error_setg(errp, "Error enabling cap-dawr1 with KVM."); |
| 716 | error_append_hint(errp, "Try appending -machine cap-dawr1=off"); |
| 717 | } |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { |
| 722 | [SPAPR_CAP_HTM] = { |
| 723 | .name = "htm", |
| 724 | .description = "Allow Hardware Transactional Memory (HTM)", |
| 725 | .index = SPAPR_CAP_HTM, |
| 726 | .get = spapr_cap_get_bool, |
| 727 | .set = spapr_cap_set_bool, |
| 728 | .type = "bool", |
| 729 | .apply = cap_htm_apply, |
| 730 | }, |
| 731 | [SPAPR_CAP_VSX] = { |
| 732 | .name = "vsx", |
| 733 | .description = "Allow Vector Scalar Extensions (VSX)", |
| 734 | .index = SPAPR_CAP_VSX, |
| 735 | .get = spapr_cap_get_bool, |
| 736 | .set = spapr_cap_set_bool, |
| 737 | .type = "bool", |
| 738 | .apply = cap_vsx_apply, |
| 739 | }, |
| 740 | [SPAPR_CAP_DFP] = { |
| 741 | .name = "dfp", |
| 742 | .description = "Allow Decimal Floating Point (DFP)", |
| 743 | .index = SPAPR_CAP_DFP, |
| 744 | .get = spapr_cap_get_bool, |
| 745 | .set = spapr_cap_set_bool, |
| 746 | .type = "bool", |
| 747 | .apply = cap_dfp_apply, |
| 748 | }, |
| 749 | [SPAPR_CAP_CFPC] = { |
| 750 | .name = "cfpc", |
| 751 | .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE, |
| 752 | .index = SPAPR_CAP_CFPC, |
| 753 | .get = spapr_cap_get_string, |
| 754 | .set = spapr_cap_set_string, |
| 755 | .type = "string", |
| 756 | .possible = &cap_cfpc_possible, |
| 757 | .apply = cap_safe_cache_apply, |
| 758 | }, |
| 759 | [SPAPR_CAP_SBBC] = { |
| 760 | .name = "sbbc", |
| 761 | .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE, |
| 762 | .index = SPAPR_CAP_SBBC, |
| 763 | .get = spapr_cap_get_string, |
| 764 | .set = spapr_cap_set_string, |
| 765 | .type = "string", |
| 766 | .possible = &cap_sbbc_possible, |
| 767 | .apply = cap_safe_bounds_check_apply, |
| 768 | }, |
| 769 | [SPAPR_CAP_IBS] = { |
| 770 | .name = "ibs", |
| 771 | .description = |
| 772 | "Indirect Branch Speculation (broken, workaround, fixed-ibs," |
| 773 | "fixed-ccd, fixed-na)", |
| 774 | .index = SPAPR_CAP_IBS, |
| 775 | .get = spapr_cap_get_string, |
| 776 | .set = spapr_cap_set_string, |
| 777 | .type = "string", |
| 778 | .possible = &cap_ibs_possible, |
| 779 | .apply = cap_safe_indirect_branch_apply, |
| 780 | }, |
| 781 | [SPAPR_CAP_HPT_MAXPAGESIZE] = { |
| 782 | .name = "hpt-max-page-size", |
| 783 | .description = "Maximum page size for Hash Page Table guests", |
| 784 | .index = SPAPR_CAP_HPT_MAXPAGESIZE, |
| 785 | .get = spapr_cap_get_pagesize, |
| 786 | .set = spapr_cap_set_pagesize, |
| 787 | .type = "int", |
| 788 | .apply = cap_hpt_maxpagesize_apply, |
| 789 | .cpu_apply = cap_hpt_maxpagesize_cpu_apply, |
| 790 | }, |
| 791 | [SPAPR_CAP_NESTED_KVM_HV] = { |
| 792 | .name = "nested-hv", |
| 793 | .description = "Allow Nested KVM-HV", |
| 794 | .index = SPAPR_CAP_NESTED_KVM_HV, |
| 795 | .get = spapr_cap_get_bool, |
| 796 | .set = spapr_cap_set_bool, |
| 797 | .type = "bool", |
| 798 | .apply = cap_nested_kvm_hv_apply, |
| 799 | }, |
| 800 | [SPAPR_CAP_NESTED_PAPR] = { |
| 801 | .name = "nested-papr", |
| 802 | .description = "Allow Nested HV (PAPR API)", |
| 803 | .index = SPAPR_CAP_NESTED_PAPR, |
| 804 | .get = spapr_cap_get_bool, |
| 805 | .set = spapr_cap_set_bool, |
| 806 | .type = "bool", |
| 807 | .apply = cap_nested_papr_apply, |
| 808 | }, |
| 809 | [SPAPR_CAP_LARGE_DECREMENTER] = { |
| 810 | .name = "large-decr", |
| 811 | .description = "Allow Large Decrementer", |
| 812 | .index = SPAPR_CAP_LARGE_DECREMENTER, |
| 813 | .get = spapr_cap_get_bool, |
| 814 | .set = spapr_cap_set_bool, |
| 815 | .type = "bool", |
| 816 | .apply = cap_large_decr_apply, |
| 817 | .cpu_apply = cap_large_decr_cpu_apply, |
| 818 | }, |
| 819 | [SPAPR_CAP_CCF_ASSIST] = { |
| 820 | .name = "ccf-assist", |
| 821 | .description = "Count Cache Flush Assist via HW Instruction", |
| 822 | .index = SPAPR_CAP_CCF_ASSIST, |
| 823 | .get = spapr_cap_get_bool, |
| 824 | .set = spapr_cap_set_bool, |
| 825 | .type = "bool", |
| 826 | .apply = cap_ccf_assist_apply, |
| 827 | }, |
| 828 | [SPAPR_CAP_FWNMI] = { |
| 829 | .name = "fwnmi", |
| 830 | .description = "Implements PAPR FWNMI option", |
| 831 | .index = SPAPR_CAP_FWNMI, |
| 832 | .get = spapr_cap_get_bool, |
| 833 | .set = spapr_cap_set_bool, |
| 834 | .type = "bool", |
| 835 | .apply = cap_fwnmi_apply, |
| 836 | }, |
| 837 | [SPAPR_CAP_RPT_INVALIDATE] = { |
| 838 | .name = "rpt-invalidate", |
| 839 | .description = "Allow H_RPT_INVALIDATE", |
| 840 | .index = SPAPR_CAP_RPT_INVALIDATE, |
| 841 | .get = spapr_cap_get_bool, |
| 842 | .set = spapr_cap_set_bool, |
| 843 | .type = "bool", |
| 844 | .apply = cap_rpt_invalidate_apply, |
| 845 | }, |
| 846 | [SPAPR_CAP_AIL_MODE_3] = { |
| 847 | .name = "ail-mode-3", |
| 848 | .description = "Alternate Interrupt Location (AIL) mode 3 support", |
| 849 | .index = SPAPR_CAP_AIL_MODE_3, |
| 850 | .get = spapr_cap_get_bool, |
| 851 | .set = spapr_cap_set_bool, |
| 852 | .type = "bool", |
| 853 | .apply = cap_ail_mode_3_apply, |
| 854 | }, |
| 855 | [SPAPR_CAP_DAWR1] = { |
| 856 | .name = "dawr1", |
| 857 | .description = "Allow 2nd Data Address Watchpoint Register (DAWR1)", |
| 858 | .index = SPAPR_CAP_DAWR1, |
| 859 | .get = spapr_cap_get_bool, |
| 860 | .set = spapr_cap_set_bool, |
| 861 | .type = "bool", |
| 862 | .apply = cap_dawr1_apply, |
| 863 | }, |
| 864 | }; |
| 865 | |
| 866 | static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, |
| 867 | const char *cputype) |
| 868 | { |
| 869 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
| 870 | SpaprCapabilities caps; |
| 871 | |
| 872 | caps = smc->default_caps; |
| 873 | |
| 874 | if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_10, |
| 875 | 0, spapr->max_compat_pvr)) { |
| 876 | caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF; |
| 877 | } |
| 878 | |
| 879 | if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00, |
| 880 | 0, spapr->max_compat_pvr)) { |
| 881 | caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; |
| 882 | } |
| 883 | |
| 884 | if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07, |
| 885 | 0, spapr->max_compat_pvr)) { |
| 886 | caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
| 887 | caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
| 888 | caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_OFF; |
| 889 | } |
| 890 | |
| 891 | if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS, |
| 892 | 0, spapr->max_compat_pvr)) { |
| 893 | caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; |
| 894 | } |
| 895 | |
| 896 | if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06, |
| 897 | 0, spapr->max_compat_pvr)) { |
| 898 | caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF; |
| 899 | caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF; |
| 900 | caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; |
| 901 | } |
| 902 | |
| 903 | /* This is for pseries-2.12 and older */ |
| 904 | if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) { |
| 905 | uint8_t mps; |
| 906 | |
| 907 | if (kvmppc_hpt_needs_host_contiguous_pages()) { |
| 908 | mps = ctz64(qemu_minrampagesize()); |
| 909 | } else { |
| 910 | mps = 34; /* allow everything up to 16GiB, i.e. everything */ |
| 911 | } |
| 912 | |
| 913 | caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps; |
| 914 | } |
| 915 | |
| 916 | return caps; |
| 917 | } |
| 918 | |
| 919 | int spapr_caps_pre_load(void *opaque) |
| 920 | { |
| 921 | SpaprMachineState *spapr = opaque; |
| 922 | |
| 923 | /* Set to default so we can tell if this came in with the migration */ |
| 924 | spapr->mig = spapr->def; |
| 925 | return 0; |
| 926 | } |
| 927 | |
| 928 | int spapr_caps_pre_save(void *opaque) |
| 929 | { |
| 930 | SpaprMachineState *spapr = opaque; |
| 931 | |
| 932 | spapr->mig = spapr->eff; |
| 933 | return 0; |
| 934 | } |
| 935 | |
| 936 | /* This has to be called from the top-level spapr post_load, not the |
| 937 | * caps specific one. Otherwise it wouldn't be called when the source |
| 938 | * caps are all defaults, which could still conflict with overridden |
| 939 | * caps on the destination */ |
| 940 | int spapr_caps_post_migration(SpaprMachineState *spapr) |
| 941 | { |
| 942 | int i; |
| 943 | bool ok = true; |
| 944 | SpaprCapabilities dstcaps = spapr->eff; |
| 945 | SpaprCapabilities srccaps; |
| 946 | |
| 947 | srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); |
| 948 | for (i = 0; i < SPAPR_CAP_NUM; i++) { |
| 949 | /* If not default value then assume came in with the migration */ |
| 950 | if (spapr->mig.caps[i] != spapr->def.caps[i]) { |
| 951 | srccaps.caps[i] = spapr->mig.caps[i]; |
| 952 | } |
| 953 | } |
| 954 | |
| 955 | for (i = 0; i < SPAPR_CAP_NUM; i++) { |
| 956 | SpaprCapabilityInfo *info = &capability_table[i]; |
| 957 | |
| 958 | if (srccaps.caps[i] > dstcaps.caps[i]) { |
| 959 | error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)", |
| 960 | info->name, srccaps.caps[i], dstcaps.caps[i]); |
| 961 | ok = false; |
| 962 | } |
| 963 | |
| 964 | if (srccaps.caps[i] < dstcaps.caps[i]) { |
| 965 | warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)", |
| 966 | info->name, srccaps.caps[i], dstcaps.caps[i]); |
| 967 | } |
| 968 | } |
| 969 | |
| 970 | return ok ? 0 : -EINVAL; |
| 971 | } |
| 972 | |
| 973 | /* Used to generate the migration field and needed function for a spapr cap */ |
| 974 | #define SPAPR_CAP_MIG_STATE(sname, cap) \ |
| 975 | static bool spapr_cap_##sname##_needed(void *opaque) \ |
| 976 | { \ |
| 977 | SpaprMachineState *spapr = opaque; \ |
| 978 | \ |
| 979 | return spapr->cmd_line_caps[cap] && \ |
| 980 | (spapr->eff.caps[cap] != \ |
| 981 | spapr->def.caps[cap]); \ |
| 982 | } \ |
| 983 | \ |
| 984 | const VMStateDescription vmstate_spapr_cap_##sname = { \ |
| 985 | .name = "spapr/cap/" #sname, \ |
| 986 | .version_id = 1, \ |
| 987 | .minimum_version_id = 1, \ |
| 988 | .needed = spapr_cap_##sname##_needed, \ |
| 989 | .fields = (const VMStateField[]) { \ |
| 990 | VMSTATE_UINT8(mig.caps[cap], \ |
| 991 | SpaprMachineState), \ |
| 992 | VMSTATE_END_OF_LIST() \ |
| 993 | }, \ |
| 994 | } |
| 995 | |
| 996 | SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM); |
| 997 | SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX); |
| 998 | SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP); |
| 999 | SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC); |
| 1000 | SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC); |
| 1001 | SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS); |
| 1002 | SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); |
| 1003 | SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); |
| 1004 | SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR); |
| 1005 | SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); |
| 1006 | SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); |
| 1007 | SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI); |
| 1008 | SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE); |
| 1009 | SPAPR_CAP_MIG_STATE(ail_mode_3, SPAPR_CAP_AIL_MODE_3); |
| 1010 | SPAPR_CAP_MIG_STATE(dawr1, SPAPR_CAP_DAWR1); |
| 1011 | |
| 1012 | void spapr_caps_init(SpaprMachineState *spapr) |
| 1013 | { |
| 1014 | SpaprCapabilities default_caps; |
| 1015 | int i; |
| 1016 | |
| 1017 | /* Compute the actual set of caps we should run with */ |
| 1018 | default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); |
| 1019 | |
| 1020 | for (i = 0; i < SPAPR_CAP_NUM; i++) { |
| 1021 | /* Store the defaults */ |
| 1022 | spapr->def.caps[i] = default_caps.caps[i]; |
| 1023 | /* If not set on the command line then apply the default value */ |
| 1024 | if (!spapr->cmd_line_caps[i]) { |
| 1025 | spapr->eff.caps[i] = default_caps.caps[i]; |
| 1026 | } |
| 1027 | } |
| 1028 | } |
| 1029 | |
| 1030 | void spapr_caps_apply(SpaprMachineState *spapr) |
| 1031 | { |
| 1032 | int i; |
| 1033 | |
| 1034 | for (i = 0; i < SPAPR_CAP_NUM; i++) { |
| 1035 | SpaprCapabilityInfo *info = &capability_table[i]; |
| 1036 | |
| 1037 | /* |
| 1038 | * If the apply function can't set the desired level and thinks it's |
| 1039 | * fatal, it should cause that. |
| 1040 | */ |
| 1041 | info->apply(spapr, spapr->eff.caps[i], &error_fatal); |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu) |
| 1046 | { |
| 1047 | int i; |
| 1048 | |
| 1049 | for (i = 0; i < SPAPR_CAP_NUM; i++) { |
| 1050 | SpaprCapabilityInfo *info = &capability_table[i]; |
| 1051 | |
| 1052 | /* |
| 1053 | * If the apply function can't set the desired level and thinks it's |
| 1054 | * fatal, it should cause that. |
| 1055 | */ |
| 1056 | if (info->cpu_apply) { |
| 1057 | info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal); |
| 1058 | } |
| 1059 | } |
| 1060 | } |
| 1061 | |
| 1062 | void spapr_caps_add_properties(SpaprMachineClass *smc) |
| 1063 | { |
| 1064 | ObjectClass *klass = OBJECT_CLASS(smc); |
| 1065 | int i; |
| 1066 | |
| 1067 | for (i = 0; i < ARRAY_SIZE(capability_table); i++) { |
| 1068 | SpaprCapabilityInfo *cap = &capability_table[i]; |
| 1069 | g_autofree char *name = g_strdup_printf("cap-%s", cap->name); |
| 1070 | g_autofree char *desc = g_strdup(cap->description); |
| 1071 | |
| 1072 | object_class_property_add(klass, name, cap->type, |
| 1073 | cap->get, cap->set, |
| 1074 | NULL, cap); |
| 1075 | |
| 1076 | object_class_property_set_description(klass, name, desc); |
| 1077 | } |
| 1078 | } |