| 1 | /* |
| 2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator |
| 3 | * |
| 4 | * RTAS events handling |
| 5 | * |
| 6 | * Copyright (c) 2012 David Gibson, IBM Corporation. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "qemu/osdep.h" |
| 29 | #include "qapi/error.h" |
| 30 | #include "system/device_tree.h" |
| 31 | #include "system/physmem.h" |
| 32 | #include "system/runstate.h" |
| 33 | |
| 34 | #include "hw/ppc/fdt.h" |
| 35 | #include "hw/ppc/spapr.h" |
| 36 | #include "hw/ppc/spapr_vio.h" |
| 37 | #include "hw/pci/pci.h" |
| 38 | #include "hw/core/irq.h" |
| 39 | #include "hw/pci-host/spapr.h" |
| 40 | #include "hw/ppc/spapr_drc.h" |
| 41 | #include "qemu/help_option.h" |
| 42 | #include "qemu/bcd.h" |
| 43 | #include "qemu/main-loop.h" |
| 44 | #include "hw/ppc/spapr_ovec.h" |
| 45 | #include "exec/cpu-common.h" |
| 46 | #include <libfdt.h> |
| 47 | #include "migration/blocker.h" |
| 48 | |
| 49 | #define RTAS_LOG_VERSION_MASK 0xff000000 |
| 50 | #define RTAS_LOG_VERSION_6 0x06000000 |
| 51 | #define RTAS_LOG_SEVERITY_MASK 0x00e00000 |
| 52 | #define RTAS_LOG_SEVERITY_ALREADY_REPORTED 0x00c00000 |
| 53 | #define RTAS_LOG_SEVERITY_FATAL 0x00a00000 |
| 54 | #define RTAS_LOG_SEVERITY_ERROR 0x00800000 |
| 55 | #define RTAS_LOG_SEVERITY_ERROR_SYNC 0x00600000 |
| 56 | #define RTAS_LOG_SEVERITY_WARNING 0x00400000 |
| 57 | #define RTAS_LOG_SEVERITY_EVENT 0x00200000 |
| 58 | #define RTAS_LOG_SEVERITY_NO_ERROR 0x00000000 |
| 59 | #define RTAS_LOG_DISPOSITION_MASK 0x00180000 |
| 60 | #define RTAS_LOG_DISPOSITION_FULLY_RECOVERED 0x00000000 |
| 61 | #define RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000 |
| 62 | #define RTAS_LOG_DISPOSITION_NOT_RECOVERED 0x00100000 |
| 63 | #define RTAS_LOG_OPTIONAL_PART_PRESENT 0x00040000 |
| 64 | #define RTAS_LOG_INITIATOR_MASK 0x0000f000 |
| 65 | #define RTAS_LOG_INITIATOR_UNKNOWN 0x00000000 |
| 66 | #define RTAS_LOG_INITIATOR_CPU 0x00001000 |
| 67 | #define RTAS_LOG_INITIATOR_PCI 0x00002000 |
| 68 | #define RTAS_LOG_INITIATOR_MEMORY 0x00004000 |
| 69 | #define RTAS_LOG_INITIATOR_HOTPLUG 0x00006000 |
| 70 | #define RTAS_LOG_TARGET_MASK 0x00000f00 |
| 71 | #define RTAS_LOG_TARGET_UNKNOWN 0x00000000 |
| 72 | #define RTAS_LOG_TARGET_CPU 0x00000100 |
| 73 | #define RTAS_LOG_TARGET_PCI 0x00000200 |
| 74 | #define RTAS_LOG_TARGET_MEMORY 0x00000400 |
| 75 | #define RTAS_LOG_TARGET_HOTPLUG 0x00000600 |
| 76 | #define RTAS_LOG_TYPE_MASK 0x000000ff |
| 77 | #define RTAS_LOG_TYPE_OTHER 0x00000000 |
| 78 | #define RTAS_LOG_TYPE_RETRY 0x00000001 |
| 79 | #define RTAS_LOG_TYPE_TCE_ERR 0x00000002 |
| 80 | #define RTAS_LOG_TYPE_INTERN_DEV_FAIL 0x00000003 |
| 81 | #define RTAS_LOG_TYPE_TIMEOUT 0x00000004 |
| 82 | #define RTAS_LOG_TYPE_DATA_PARITY 0x00000005 |
| 83 | #define RTAS_LOG_TYPE_ADDR_PARITY 0x00000006 |
| 84 | #define RTAS_LOG_TYPE_CACHE_PARITY 0x00000007 |
| 85 | #define RTAS_LOG_TYPE_ADDR_INVALID 0x00000008 |
| 86 | #define RTAS_LOG_TYPE_ECC_UNCORR 0x00000009 |
| 87 | #define RTAS_LOG_TYPE_ECC_CORR 0x0000000a |
| 88 | #define RTAS_LOG_TYPE_EPOW 0x00000040 |
| 89 | #define RTAS_LOG_TYPE_HOTPLUG 0x000000e5 |
| 90 | |
| 91 | struct rtas_error_log { |
| 92 | uint32_t summary; |
| 93 | uint32_t extended_length; |
| 94 | } QEMU_PACKED; |
| 95 | |
| 96 | struct rtas_event_log_v6 { |
| 97 | uint8_t b0; |
| 98 | #define RTAS_LOG_V6_B0_VALID 0x80 |
| 99 | #define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR 0x40 |
| 100 | #define RTAS_LOG_V6_B0_RECOVERABLE_ERROR 0x20 |
| 101 | #define RTAS_LOG_V6_B0_DEGRADED_OPERATION 0x10 |
| 102 | #define RTAS_LOG_V6_B0_PREDICTIVE_ERROR 0x08 |
| 103 | #define RTAS_LOG_V6_B0_NEW_LOG 0x04 |
| 104 | #define RTAS_LOG_V6_B0_BIGENDIAN 0x02 |
| 105 | uint8_t _resv1; |
| 106 | uint8_t b2; |
| 107 | #define RTAS_LOG_V6_B2_POWERPC_FORMAT 0x80 |
| 108 | #define RTAS_LOG_V6_B2_LOG_FORMAT_MASK 0x0f |
| 109 | #define RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT 0x0e |
| 110 | uint8_t _resv2[9]; |
| 111 | uint32_t company; |
| 112 | #define RTAS_LOG_V6_COMPANY_IBM 0x49424d00 /* IBM<null> */ |
| 113 | } QEMU_PACKED; |
| 114 | |
| 115 | struct rtas_event_log_v6_section_header { |
| 116 | uint16_t section_id; |
| 117 | uint16_t section_length; |
| 118 | uint8_t section_version; |
| 119 | uint8_t section_subtype; |
| 120 | uint16_t creator_component_id; |
| 121 | } QEMU_PACKED; |
| 122 | |
| 123 | struct rtas_event_log_v6_maina { |
| 124 | #define RTAS_LOG_V6_SECTION_ID_MAINA 0x5048 /* PH */ |
| 125 | struct rtas_event_log_v6_section_header hdr; |
| 126 | uint32_t creation_date; /* BCD: YYYYMMDD */ |
| 127 | uint32_t creation_time; /* BCD: HHMMSS00 */ |
| 128 | uint8_t _platform1[8]; |
| 129 | char creator_id; |
| 130 | uint8_t _resv1[2]; |
| 131 | uint8_t section_count; |
| 132 | uint8_t _resv2[4]; |
| 133 | uint8_t _platform2[8]; |
| 134 | uint32_t plid; |
| 135 | uint8_t _platform3[4]; |
| 136 | } QEMU_PACKED; |
| 137 | |
| 138 | struct rtas_event_log_v6_mainb { |
| 139 | #define RTAS_LOG_V6_SECTION_ID_MAINB 0x5548 /* UH */ |
| 140 | struct rtas_event_log_v6_section_header hdr; |
| 141 | uint8_t subsystem_id; |
| 142 | uint8_t _platform1; |
| 143 | uint8_t event_severity; |
| 144 | uint8_t event_subtype; |
| 145 | uint8_t _platform2[4]; |
| 146 | uint8_t _resv1[2]; |
| 147 | uint16_t action_flags; |
| 148 | uint8_t _resv2[4]; |
| 149 | } QEMU_PACKED; |
| 150 | |
| 151 | struct rtas_event_log_v6_epow { |
| 152 | #define RTAS_LOG_V6_SECTION_ID_EPOW 0x4550 /* EP */ |
| 153 | struct rtas_event_log_v6_section_header hdr; |
| 154 | uint8_t sensor_value; |
| 155 | #define RTAS_LOG_V6_EPOW_ACTION_RESET 0 |
| 156 | #define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING 1 |
| 157 | #define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER 2 |
| 158 | #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN 3 |
| 159 | #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT 4 |
| 160 | #define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE 5 |
| 161 | #define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF 7 |
| 162 | uint8_t event_modifier; |
| 163 | #define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL 1 |
| 164 | #define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS 2 |
| 165 | #define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL 3 |
| 166 | #define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE 4 |
| 167 | uint8_t extended_modifier; |
| 168 | #define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE 0 |
| 169 | #define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC 1 |
| 170 | uint8_t _resv; |
| 171 | uint64_t reason_code; |
| 172 | } QEMU_PACKED; |
| 173 | |
| 174 | struct epow_extended_log { |
| 175 | struct rtas_event_log_v6 v6hdr; |
| 176 | struct rtas_event_log_v6_maina maina; |
| 177 | struct rtas_event_log_v6_mainb mainb; |
| 178 | struct rtas_event_log_v6_epow epow; |
| 179 | } QEMU_PACKED; |
| 180 | |
| 181 | union drc_identifier { |
| 182 | uint32_t index; |
| 183 | uint32_t count; |
| 184 | struct { |
| 185 | uint32_t count; |
| 186 | uint32_t index; |
| 187 | } count_indexed; |
| 188 | char name[1]; |
| 189 | } QEMU_PACKED; |
| 190 | |
| 191 | struct rtas_event_log_v6_hp { |
| 192 | #define RTAS_LOG_V6_SECTION_ID_HOTPLUG 0x4850 /* HP */ |
| 193 | struct rtas_event_log_v6_section_header hdr; |
| 194 | uint8_t hotplug_type; |
| 195 | #define RTAS_LOG_V6_HP_TYPE_CPU 1 |
| 196 | #define RTAS_LOG_V6_HP_TYPE_MEMORY 2 |
| 197 | #define RTAS_LOG_V6_HP_TYPE_SLOT 3 |
| 198 | #define RTAS_LOG_V6_HP_TYPE_PHB 4 |
| 199 | #define RTAS_LOG_V6_HP_TYPE_PCI 5 |
| 200 | #define RTAS_LOG_V6_HP_TYPE_PMEM 6 |
| 201 | uint8_t hotplug_action; |
| 202 | #define RTAS_LOG_V6_HP_ACTION_ADD 1 |
| 203 | #define RTAS_LOG_V6_HP_ACTION_REMOVE 2 |
| 204 | uint8_t hotplug_identifier; |
| 205 | #define RTAS_LOG_V6_HP_ID_DRC_NAME 1 |
| 206 | #define RTAS_LOG_V6_HP_ID_DRC_INDEX 2 |
| 207 | #define RTAS_LOG_V6_HP_ID_DRC_COUNT 3 |
| 208 | #define RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED 4 |
| 209 | uint8_t reserved; |
| 210 | union drc_identifier drc_id; |
| 211 | } QEMU_PACKED; |
| 212 | |
| 213 | struct hp_extended_log { |
| 214 | struct rtas_event_log_v6 v6hdr; |
| 215 | struct rtas_event_log_v6_maina maina; |
| 216 | struct rtas_event_log_v6_mainb mainb; |
| 217 | struct rtas_event_log_v6_hp hp; |
| 218 | } QEMU_PACKED; |
| 219 | |
| 220 | struct rtas_event_log_v6_mc { |
| 221 | #define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ |
| 222 | struct rtas_event_log_v6_section_header hdr; |
| 223 | uint32_t fru_id; |
| 224 | uint32_t proc_id; |
| 225 | uint8_t error_type; |
| 226 | #define RTAS_LOG_V6_MC_TYPE_UE 0 |
| 227 | #define RTAS_LOG_V6_MC_TYPE_SLB 1 |
| 228 | #define RTAS_LOG_V6_MC_TYPE_ERAT 2 |
| 229 | #define RTAS_LOG_V6_MC_TYPE_TLB 4 |
| 230 | #define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 |
| 231 | #define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 |
| 232 | uint8_t sub_err_type; |
| 233 | #define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 |
| 234 | #define RTAS_LOG_V6_MC_UE_IFETCH 1 |
| 235 | #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 |
| 236 | #define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 |
| 237 | #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 |
| 238 | #define RTAS_LOG_V6_MC_SLB_PARITY 0 |
| 239 | #define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 |
| 240 | #define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 |
| 241 | #define RTAS_LOG_V6_MC_ERAT_PARITY 1 |
| 242 | #define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 |
| 243 | #define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 |
| 244 | #define RTAS_LOG_V6_MC_TLB_PARITY 1 |
| 245 | #define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 |
| 246 | #define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 |
| 247 | /* |
| 248 | * Per PAPR, |
| 249 | * For UE error type, set bit 1 of sub_err_type to indicate effective addr is |
| 250 | * provided. For other error types (SLB/ERAT/TLB), set bit 0 to indicate |
| 251 | * same. |
| 252 | */ |
| 253 | #define RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED 0x40 |
| 254 | #define RTAS_LOG_V6_MC_EA_ADDR_PROVIDED 0x80 |
| 255 | uint8_t reserved_1[6]; |
| 256 | uint64_t effective_address; |
| 257 | uint64_t logical_address; |
| 258 | } QEMU_PACKED; |
| 259 | |
| 260 | struct mc_extended_log { |
| 261 | struct rtas_event_log_v6 v6hdr; |
| 262 | struct rtas_event_log_v6_mc mc; |
| 263 | } QEMU_PACKED; |
| 264 | |
| 265 | struct MC_ierror_table { |
| 266 | unsigned long srr1_mask; |
| 267 | unsigned long srr1_value; |
| 268 | bool nip_valid; /* nip is a valid indicator of faulting address */ |
| 269 | uint8_t error_type; |
| 270 | uint8_t error_subtype; |
| 271 | unsigned int initiator; |
| 272 | unsigned int severity; |
| 273 | }; |
| 274 | |
| 275 | static const struct MC_ierror_table mc_ierror_table[] = { |
| 276 | { 0x00000000081c0000, 0x0000000000040000, true, |
| 277 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, |
| 278 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 279 | { 0x00000000081c0000, 0x0000000000080000, true, |
| 280 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, |
| 281 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 282 | { 0x00000000081c0000, 0x00000000000c0000, true, |
| 283 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, |
| 284 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 285 | { 0x00000000081c0000, 0x0000000000100000, true, |
| 286 | RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, |
| 287 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 288 | { 0x00000000081c0000, 0x0000000000140000, true, |
| 289 | RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, |
| 290 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 291 | { 0x00000000081c0000, 0x0000000000180000, true, |
| 292 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, |
| 293 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; |
| 294 | |
| 295 | struct MC_derror_table { |
| 296 | unsigned long dsisr_value; |
| 297 | bool dar_valid; /* dar is a valid indicator of faulting address */ |
| 298 | uint8_t error_type; |
| 299 | uint8_t error_subtype; |
| 300 | unsigned int initiator; |
| 301 | unsigned int severity; |
| 302 | }; |
| 303 | |
| 304 | static const struct MC_derror_table mc_derror_table[] = { |
| 305 | { 0x00008000, false, |
| 306 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, |
| 307 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 308 | { 0x00004000, true, |
| 309 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, |
| 310 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 311 | { 0x00000800, true, |
| 312 | RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, |
| 313 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 314 | { 0x00000400, true, |
| 315 | RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, |
| 316 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 317 | { 0x00000080, true, |
| 318 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY */ |
| 319 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, |
| 320 | { 0x00000100, true, |
| 321 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, |
| 322 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; |
| 323 | |
| 324 | #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) |
| 325 | |
| 326 | typedef enum EventClass { |
| 327 | EVENT_CLASS_INTERNAL_ERRORS = 0, |
| 328 | EVENT_CLASS_EPOW = 1, |
| 329 | EVENT_CLASS_RESERVED = 2, |
| 330 | EVENT_CLASS_HOT_PLUG = 3, |
| 331 | EVENT_CLASS_IO = 4, |
| 332 | EVENT_CLASS_MAX |
| 333 | } EventClassIndex; |
| 334 | #define EVENT_CLASS_MASK(index) (1 << (31 - index)) |
| 335 | |
| 336 | static const char * const event_names[EVENT_CLASS_MAX] = { |
| 337 | [EVENT_CLASS_INTERNAL_ERRORS] = "internal-errors", |
| 338 | [EVENT_CLASS_EPOW] = "epow-events", |
| 339 | [EVENT_CLASS_HOT_PLUG] = "hot-plug-events", |
| 340 | [EVENT_CLASS_IO] = "ibm,io-events", |
| 341 | }; |
| 342 | |
| 343 | struct SpaprEventSource { |
| 344 | int irq; |
| 345 | uint32_t mask; |
| 346 | bool enabled; |
| 347 | }; |
| 348 | |
| 349 | static SpaprEventSource *spapr_event_sources_new(void) |
| 350 | { |
| 351 | return g_new0(SpaprEventSource, EVENT_CLASS_MAX); |
| 352 | } |
| 353 | |
| 354 | static void spapr_event_sources_register(SpaprEventSource *event_sources, |
| 355 | EventClassIndex index, int irq) |
| 356 | { |
| 357 | /* we only support 1 irq per event class at the moment */ |
| 358 | g_assert(event_sources); |
| 359 | g_assert(!event_sources[index].enabled); |
| 360 | event_sources[index].irq = irq; |
| 361 | event_sources[index].mask = EVENT_CLASS_MASK(index); |
| 362 | event_sources[index].enabled = true; |
| 363 | } |
| 364 | |
| 365 | static const SpaprEventSource * |
| 366 | spapr_event_sources_get_source(SpaprEventSource *event_sources, |
| 367 | EventClassIndex index) |
| 368 | { |
| 369 | g_assert(index < EVENT_CLASS_MAX); |
| 370 | g_assert(event_sources); |
| 371 | |
| 372 | return &event_sources[index]; |
| 373 | } |
| 374 | |
| 375 | void spapr_dt_events(SpaprMachineState *spapr, void *fdt) |
| 376 | { |
| 377 | uint32_t irq_ranges[EVENT_CLASS_MAX * 2]; |
| 378 | int i, count = 0, event_sources; |
| 379 | SpaprEventSource *events = spapr->event_sources; |
| 380 | |
| 381 | g_assert(events); |
| 382 | |
| 383 | _FDT(event_sources = fdt_add_subnode(fdt, 0, "event-sources")); |
| 384 | |
| 385 | for (i = 0, count = 0; i < EVENT_CLASS_MAX; i++) { |
| 386 | int node_offset; |
| 387 | uint32_t interrupts[2]; |
| 388 | const SpaprEventSource *source = |
| 389 | spapr_event_sources_get_source(events, i); |
| 390 | const char *source_name = event_names[i]; |
| 391 | |
| 392 | if (!source->enabled) { |
| 393 | continue; |
| 394 | } |
| 395 | |
| 396 | spapr_dt_irq(interrupts, source->irq, false); |
| 397 | |
| 398 | _FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name)); |
| 399 | _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, |
| 400 | sizeof(interrupts))); |
| 401 | |
| 402 | irq_ranges[count++] = interrupts[0]; |
| 403 | irq_ranges[count++] = cpu_to_be32(1); |
| 404 | } |
| 405 | |
| 406 | _FDT((fdt_setprop(fdt, event_sources, "interrupt-controller", NULL, 0))); |
| 407 | _FDT((fdt_setprop_cell(fdt, event_sources, "#interrupt-cells", 2))); |
| 408 | _FDT((fdt_setprop(fdt, event_sources, "interrupt-ranges", |
| 409 | irq_ranges, count * sizeof(uint32_t)))); |
| 410 | } |
| 411 | |
| 412 | static const SpaprEventSource * |
| 413 | rtas_event_log_to_source(SpaprMachineState *spapr, int log_type) |
| 414 | { |
| 415 | const SpaprEventSource *source; |
| 416 | |
| 417 | g_assert(spapr->event_sources); |
| 418 | |
| 419 | switch (log_type) { |
| 420 | case RTAS_LOG_TYPE_HOTPLUG: |
| 421 | source = spapr_event_sources_get_source(spapr->event_sources, |
| 422 | EVENT_CLASS_HOT_PLUG); |
| 423 | if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) { |
| 424 | g_assert(source->enabled); |
| 425 | break; |
| 426 | } |
| 427 | /* fall through back to epow for legacy hotplug interrupt source */ |
| 428 | case RTAS_LOG_TYPE_EPOW: |
| 429 | source = spapr_event_sources_get_source(spapr->event_sources, |
| 430 | EVENT_CLASS_EPOW); |
| 431 | break; |
| 432 | default: |
| 433 | source = NULL; |
| 434 | } |
| 435 | |
| 436 | return source; |
| 437 | } |
| 438 | |
| 439 | static int rtas_event_log_to_irq(SpaprMachineState *spapr, int log_type) |
| 440 | { |
| 441 | const SpaprEventSource *source; |
| 442 | |
| 443 | source = rtas_event_log_to_source(spapr, log_type); |
| 444 | g_assert(source); |
| 445 | g_assert(source->enabled); |
| 446 | |
| 447 | return source->irq; |
| 448 | } |
| 449 | |
| 450 | static uint32_t spapr_event_log_entry_type(SpaprEventLogEntry *entry) |
| 451 | { |
| 452 | return entry->summary & RTAS_LOG_TYPE_MASK; |
| 453 | } |
| 454 | |
| 455 | static void rtas_event_log_queue(SpaprMachineState *spapr, |
| 456 | SpaprEventLogEntry *entry) |
| 457 | { |
| 458 | QTAILQ_INSERT_TAIL(&spapr->pending_events, entry, next); |
| 459 | } |
| 460 | |
| 461 | static SpaprEventLogEntry *rtas_event_log_dequeue(SpaprMachineState *spapr, |
| 462 | uint32_t event_mask) |
| 463 | { |
| 464 | SpaprEventLogEntry *entry; |
| 465 | |
| 466 | QTAILQ_FOREACH(entry, &spapr->pending_events, next) { |
| 467 | const SpaprEventSource *source = |
| 468 | rtas_event_log_to_source(spapr, |
| 469 | spapr_event_log_entry_type(entry)); |
| 470 | |
| 471 | g_assert(source); |
| 472 | if (source->mask & event_mask) { |
| 473 | break; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | if (entry) { |
| 478 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); |
| 479 | } |
| 480 | |
| 481 | return entry; |
| 482 | } |
| 483 | |
| 484 | static bool rtas_event_log_contains(SpaprMachineState *spapr, uint32_t event_mask) |
| 485 | { |
| 486 | SpaprEventLogEntry *entry; |
| 487 | |
| 488 | QTAILQ_FOREACH(entry, &spapr->pending_events, next) { |
| 489 | const SpaprEventSource *source = |
| 490 | rtas_event_log_to_source(spapr, |
| 491 | spapr_event_log_entry_type(entry)); |
| 492 | |
| 493 | if (source->mask & event_mask) { |
| 494 | return true; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | return false; |
| 499 | } |
| 500 | |
| 501 | static uint32_t next_plid; |
| 502 | |
| 503 | static void spapr_init_v6hdr(struct rtas_event_log_v6 *v6hdr) |
| 504 | { |
| 505 | v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG |
| 506 | | RTAS_LOG_V6_B0_BIGENDIAN; |
| 507 | v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT |
| 508 | | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT; |
| 509 | v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM); |
| 510 | } |
| 511 | |
| 512 | static void spapr_init_maina(SpaprMachineState *spapr, |
| 513 | struct rtas_event_log_v6_maina *maina, |
| 514 | int section_count) |
| 515 | { |
| 516 | struct tm tm; |
| 517 | int year; |
| 518 | |
| 519 | maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA); |
| 520 | maina->hdr.section_length = cpu_to_be16(sizeof(*maina)); |
| 521 | /* FIXME: section version, subtype and creator id? */ |
| 522 | spapr_rtc_read(&spapr->rtc, &tm, NULL); |
| 523 | year = tm.tm_year + 1900; |
| 524 | maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24) |
| 525 | | (to_bcd(year % 100) << 16) |
| 526 | | (to_bcd(tm.tm_mon + 1) << 8) |
| 527 | | to_bcd(tm.tm_mday)); |
| 528 | maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24) |
| 529 | | (to_bcd(tm.tm_min) << 16) |
| 530 | | (to_bcd(tm.tm_sec) << 8)); |
| 531 | maina->creator_id = 'H'; /* Hypervisor */ |
| 532 | maina->section_count = section_count; |
| 533 | maina->plid = next_plid++; |
| 534 | } |
| 535 | |
| 536 | static void spapr_powerdown_req(Notifier *n, void *opaque) |
| 537 | { |
| 538 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 539 | SpaprEventLogEntry *entry; |
| 540 | struct rtas_event_log_v6 *v6hdr; |
| 541 | struct rtas_event_log_v6_maina *maina; |
| 542 | struct rtas_event_log_v6_mainb *mainb; |
| 543 | struct rtas_event_log_v6_epow *epow; |
| 544 | struct epow_extended_log *new_epow; |
| 545 | |
| 546 | entry = g_new(SpaprEventLogEntry, 1); |
| 547 | new_epow = g_malloc0(sizeof(*new_epow)); |
| 548 | entry->extended_log = new_epow; |
| 549 | |
| 550 | v6hdr = &new_epow->v6hdr; |
| 551 | maina = &new_epow->maina; |
| 552 | mainb = &new_epow->mainb; |
| 553 | epow = &new_epow->epow; |
| 554 | |
| 555 | entry->summary = RTAS_LOG_VERSION_6 |
| 556 | | RTAS_LOG_SEVERITY_EVENT |
| 557 | | RTAS_LOG_DISPOSITION_NOT_RECOVERED |
| 558 | | RTAS_LOG_OPTIONAL_PART_PRESENT |
| 559 | | RTAS_LOG_TYPE_EPOW; |
| 560 | entry->extended_length = sizeof(*new_epow); |
| 561 | |
| 562 | spapr_init_v6hdr(v6hdr); |
| 563 | spapr_init_maina(spapr, maina, 3 /* Main-A, Main-B and EPOW */); |
| 564 | |
| 565 | mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); |
| 566 | mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); |
| 567 | /* FIXME: section version, subtype and creator id? */ |
| 568 | mainb->subsystem_id = 0xa0; /* External environment */ |
| 569 | mainb->event_severity = 0x00; /* Informational / non-error */ |
| 570 | mainb->event_subtype = 0xd0; /* Normal shutdown */ |
| 571 | |
| 572 | epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW); |
| 573 | epow->hdr.section_length = cpu_to_be16(sizeof(*epow)); |
| 574 | epow->hdr.section_version = 2; /* includes extended modifier */ |
| 575 | /* FIXME: section subtype and creator id? */ |
| 576 | epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN; |
| 577 | epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL; |
| 578 | epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC; |
| 579 | |
| 580 | rtas_event_log_queue(spapr, entry); |
| 581 | |
| 582 | qemu_irq_pulse(spapr_qirq(spapr, |
| 583 | rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_EPOW))); |
| 584 | } |
| 585 | |
| 586 | static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action, |
| 587 | SpaprDrcType drc_type, |
| 588 | union drc_identifier *drc_id) |
| 589 | { |
| 590 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 591 | SpaprEventLogEntry *entry; |
| 592 | struct hp_extended_log *new_hp; |
| 593 | struct rtas_event_log_v6 *v6hdr; |
| 594 | struct rtas_event_log_v6_maina *maina; |
| 595 | struct rtas_event_log_v6_mainb *mainb; |
| 596 | struct rtas_event_log_v6_hp *hp; |
| 597 | |
| 598 | entry = g_new(SpaprEventLogEntry, 1); |
| 599 | new_hp = g_new0(struct hp_extended_log, 1); |
| 600 | entry->extended_log = new_hp; |
| 601 | |
| 602 | v6hdr = &new_hp->v6hdr; |
| 603 | maina = &new_hp->maina; |
| 604 | mainb = &new_hp->mainb; |
| 605 | hp = &new_hp->hp; |
| 606 | |
| 607 | entry->summary = RTAS_LOG_VERSION_6 |
| 608 | | RTAS_LOG_SEVERITY_EVENT |
| 609 | | RTAS_LOG_DISPOSITION_NOT_RECOVERED |
| 610 | | RTAS_LOG_OPTIONAL_PART_PRESENT |
| 611 | | RTAS_LOG_INITIATOR_HOTPLUG |
| 612 | | RTAS_LOG_TYPE_HOTPLUG; |
| 613 | entry->extended_length = sizeof(*new_hp); |
| 614 | |
| 615 | spapr_init_v6hdr(v6hdr); |
| 616 | spapr_init_maina(spapr, maina, 3 /* Main-A, Main-B, HP */); |
| 617 | |
| 618 | mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); |
| 619 | mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); |
| 620 | mainb->subsystem_id = 0x80; /* External environment */ |
| 621 | mainb->event_severity = 0x00; /* Informational / non-error */ |
| 622 | mainb->event_subtype = 0x00; /* Normal shutdown */ |
| 623 | |
| 624 | hp->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_HOTPLUG); |
| 625 | hp->hdr.section_length = cpu_to_be16(sizeof(*hp)); |
| 626 | hp->hdr.section_version = 1; /* includes extended modifier */ |
| 627 | hp->hotplug_action = hp_action; |
| 628 | hp->hotplug_identifier = hp_id; |
| 629 | |
| 630 | switch (drc_type) { |
| 631 | case SPAPR_DR_CONNECTOR_TYPE_PCI: |
| 632 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PCI; |
| 633 | break; |
| 634 | case SPAPR_DR_CONNECTOR_TYPE_LMB: |
| 635 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_MEMORY; |
| 636 | break; |
| 637 | case SPAPR_DR_CONNECTOR_TYPE_CPU: |
| 638 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_CPU; |
| 639 | break; |
| 640 | case SPAPR_DR_CONNECTOR_TYPE_PHB: |
| 641 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PHB; |
| 642 | break; |
| 643 | case SPAPR_DR_CONNECTOR_TYPE_PMEM: |
| 644 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PMEM; |
| 645 | break; |
| 646 | default: |
| 647 | /* we shouldn't be signaling hotplug events for resources |
| 648 | * that don't support them |
| 649 | */ |
| 650 | g_assert_not_reached(); |
| 651 | } |
| 652 | |
| 653 | if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT) { |
| 654 | hp->drc_id.count = cpu_to_be32(drc_id->count); |
| 655 | } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_INDEX) { |
| 656 | hp->drc_id.index = cpu_to_be32(drc_id->index); |
| 657 | } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED) { |
| 658 | /* we should not be using count_indexed value unless the guest |
| 659 | * supports dedicated hotplug event source |
| 660 | */ |
| 661 | g_assert(spapr_memory_hot_unplug_supported(spapr)); |
| 662 | hp->drc_id.count_indexed.count = |
| 663 | cpu_to_be32(drc_id->count_indexed.count); |
| 664 | hp->drc_id.count_indexed.index = |
| 665 | cpu_to_be32(drc_id->count_indexed.index); |
| 666 | } |
| 667 | |
| 668 | rtas_event_log_queue(spapr, entry); |
| 669 | |
| 670 | qemu_irq_pulse(spapr_qirq(spapr, |
| 671 | rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_HOTPLUG))); |
| 672 | } |
| 673 | |
| 674 | void spapr_hotplug_req_add_by_index(SpaprDrc *drc) |
| 675 | { |
| 676 | SpaprDrcType drc_type = spapr_drc_type(drc); |
| 677 | union drc_identifier drc_id; |
| 678 | |
| 679 | drc_id.index = spapr_drc_index(drc); |
| 680 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, |
| 681 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); |
| 682 | } |
| 683 | |
| 684 | void spapr_hotplug_req_remove_by_index(SpaprDrc *drc) |
| 685 | { |
| 686 | SpaprDrcType drc_type = spapr_drc_type(drc); |
| 687 | union drc_identifier drc_id; |
| 688 | |
| 689 | drc_id.index = spapr_drc_index(drc); |
| 690 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, |
| 691 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); |
| 692 | } |
| 693 | |
| 694 | void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, |
| 695 | uint32_t count) |
| 696 | { |
| 697 | union drc_identifier drc_id; |
| 698 | |
| 699 | drc_id.count = count; |
| 700 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, |
| 701 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); |
| 702 | } |
| 703 | |
| 704 | void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, |
| 705 | uint32_t count) |
| 706 | { |
| 707 | union drc_identifier drc_id; |
| 708 | |
| 709 | drc_id.count = count; |
| 710 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, |
| 711 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); |
| 712 | } |
| 713 | |
| 714 | void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, |
| 715 | uint32_t count, uint32_t index) |
| 716 | { |
| 717 | union drc_identifier drc_id; |
| 718 | |
| 719 | drc_id.count_indexed.count = count; |
| 720 | drc_id.count_indexed.index = index; |
| 721 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, |
| 722 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); |
| 723 | } |
| 724 | |
| 725 | void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, |
| 726 | uint32_t count, uint32_t index) |
| 727 | { |
| 728 | union drc_identifier drc_id; |
| 729 | |
| 730 | drc_id.count_indexed.count = count; |
| 731 | drc_id.count_indexed.index = index; |
| 732 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, |
| 733 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); |
| 734 | } |
| 735 | |
| 736 | static void spapr_mc_set_ea_provided_flag(struct mc_extended_log *ext_elog) |
| 737 | { |
| 738 | switch (ext_elog->mc.error_type) { |
| 739 | case RTAS_LOG_V6_MC_TYPE_UE: |
| 740 | ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED; |
| 741 | break; |
| 742 | case RTAS_LOG_V6_MC_TYPE_SLB: |
| 743 | case RTAS_LOG_V6_MC_TYPE_ERAT: |
| 744 | case RTAS_LOG_V6_MC_TYPE_TLB: |
| 745 | ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_EA_ADDR_PROVIDED; |
| 746 | break; |
| 747 | default: |
| 748 | break; |
| 749 | } |
| 750 | } |
| 751 | |
| 752 | static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, |
| 753 | struct mc_extended_log *ext_elog) |
| 754 | { |
| 755 | int i; |
| 756 | CPUPPCState *env = &cpu->env; |
| 757 | uint32_t summary; |
| 758 | uint64_t dsisr = env->spr[SPR_DSISR]; |
| 759 | |
| 760 | summary = RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; |
| 761 | if (recovered) { |
| 762 | summary |= RTAS_LOG_DISPOSITION_FULLY_RECOVERED; |
| 763 | } else { |
| 764 | summary |= RTAS_LOG_DISPOSITION_NOT_RECOVERED; |
| 765 | } |
| 766 | |
| 767 | if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { |
| 768 | for (i = 0; i < ARRAY_SIZE(mc_derror_table); i++) { |
| 769 | if (!(dsisr & mc_derror_table[i].dsisr_value)) { |
| 770 | continue; |
| 771 | } |
| 772 | |
| 773 | ext_elog->mc.error_type = mc_derror_table[i].error_type; |
| 774 | ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype; |
| 775 | if (mc_derror_table[i].dar_valid) { |
| 776 | ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]); |
| 777 | spapr_mc_set_ea_provided_flag(ext_elog); |
| 778 | } |
| 779 | |
| 780 | summary |= mc_derror_table[i].initiator |
| 781 | | mc_derror_table[i].severity; |
| 782 | |
| 783 | return summary; |
| 784 | } |
| 785 | } else { |
| 786 | for (i = 0; i < ARRAY_SIZE(mc_ierror_table); i++) { |
| 787 | if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) != |
| 788 | mc_ierror_table[i].srr1_value) { |
| 789 | continue; |
| 790 | } |
| 791 | |
| 792 | ext_elog->mc.error_type = mc_ierror_table[i].error_type; |
| 793 | ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype; |
| 794 | if (mc_ierror_table[i].nip_valid) { |
| 795 | ext_elog->mc.effective_address = cpu_to_be64(env->nip); |
| 796 | spapr_mc_set_ea_provided_flag(ext_elog); |
| 797 | } |
| 798 | |
| 799 | summary |= mc_ierror_table[i].initiator |
| 800 | | mc_ierror_table[i].severity; |
| 801 | |
| 802 | return summary; |
| 803 | } |
| 804 | } |
| 805 | |
| 806 | summary |= RTAS_LOG_INITIATOR_CPU; |
| 807 | return summary; |
| 808 | } |
| 809 | |
| 810 | static void spapr_mce_dispatch_elog(SpaprMachineState *spapr, PowerPCCPU *cpu, |
| 811 | bool recovered) |
| 812 | { |
| 813 | CPUState *cs = CPU(cpu); |
| 814 | CPUPPCState *env = &cpu->env; |
| 815 | uint64_t rtas_addr; |
| 816 | struct rtas_error_log log; |
| 817 | struct mc_extended_log *ext_elog; |
| 818 | uint32_t summary; |
| 819 | |
| 820 | ext_elog = g_malloc0(sizeof(*ext_elog)); |
| 821 | summary = spapr_mce_get_elog_type(cpu, recovered, ext_elog); |
| 822 | |
| 823 | log.summary = cpu_to_be32(summary); |
| 824 | log.extended_length = cpu_to_be32(sizeof(*ext_elog)); |
| 825 | |
| 826 | spapr_init_v6hdr(&ext_elog->v6hdr); |
| 827 | ext_elog->mc.hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); |
| 828 | ext_elog->mc.hdr.section_length = |
| 829 | cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); |
| 830 | ext_elog->mc.hdr.section_version = 1; |
| 831 | |
| 832 | /* get rtas addr from fdt */ |
| 833 | rtas_addr = spapr_get_rtas_addr(); |
| 834 | if (!rtas_addr) { |
| 835 | if (!recovered) { |
| 836 | error_report( |
| 837 | "FWNMI: Unable to deliver machine check to guest: rtas_addr not found."); |
| 838 | qemu_system_guest_panicked(NULL); |
| 839 | } else { |
| 840 | warn_report( |
| 841 | "FWNMI: Unable to deliver machine check to guest: rtas_addr not found. " |
| 842 | "Machine check recovered."); |
| 843 | } |
| 844 | g_free(ext_elog); |
| 845 | return; |
| 846 | } |
| 847 | |
| 848 | /* |
| 849 | * By taking the interlock, we assume that the MCE will be |
| 850 | * delivered to the guest. CAUTION: don't add anything that could |
| 851 | * prevent the MCE to be delivered after this line, otherwise the |
| 852 | * guest won't be able to release the interlock and ultimately |
| 853 | * hang/crash? |
| 854 | */ |
| 855 | spapr->fwnmi_machine_check_interlock = cpu->vcpu_id; |
| 856 | |
| 857 | stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET, |
| 858 | env->gpr[3]); |
| 859 | physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + |
| 860 | sizeof(env->gpr[3]), &log, sizeof(log)); |
| 861 | physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + |
| 862 | sizeof(env->gpr[3]) + sizeof(log), ext_elog, |
| 863 | sizeof(*ext_elog)); |
| 864 | g_free(ext_elog); |
| 865 | |
| 866 | env->gpr[3] = rtas_addr + RTAS_ERROR_LOG_OFFSET; |
| 867 | |
| 868 | ppc_cpu_do_fwnmi_machine_check(cs, spapr->fwnmi_machine_check_addr); |
| 869 | } |
| 870 | |
| 871 | void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) |
| 872 | { |
| 873 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 874 | CPUState *cs = CPU(cpu); |
| 875 | int ret; |
| 876 | |
| 877 | if (spapr->fwnmi_machine_check_addr == -1) { |
| 878 | /* Non-FWNMI case, deliver it like an architected CPU interrupt. */ |
| 879 | cs->exception_index = POWERPC_EXCP_MCHECK; |
| 880 | ppc_cpu_do_interrupt(cs); |
| 881 | return; |
| 882 | } |
| 883 | |
| 884 | /* Wait for FWNMI interlock. */ |
| 885 | while (spapr->fwnmi_machine_check_interlock != -1) { |
| 886 | /* |
| 887 | * Check whether the same CPU got machine check error |
| 888 | * while still handling the mc error (i.e., before |
| 889 | * that CPU called "ibm,nmi-interlock") |
| 890 | */ |
| 891 | if (spapr->fwnmi_machine_check_interlock == cpu->vcpu_id) { |
| 892 | if (!recovered) { |
| 893 | error_report( |
| 894 | "FWNMI: Unable to deliver machine check to guest: nested machine check."); |
| 895 | qemu_system_guest_panicked(NULL); |
| 896 | } else { |
| 897 | warn_report( |
| 898 | "FWNMI: Unable to deliver machine check to guest: nested machine check. " |
| 899 | "Machine check recovered."); |
| 900 | } |
| 901 | return; |
| 902 | } |
| 903 | qemu_cond_wait_bql(&spapr->fwnmi_machine_check_interlock_cond); |
| 904 | if (spapr->fwnmi_machine_check_addr == -1) { |
| 905 | /* |
| 906 | * If the machine was reset while waiting for the interlock, |
| 907 | * abort the delivery. The machine check applies to a context |
| 908 | * that no longer exists, so it wouldn't make sense to deliver |
| 909 | * it now. |
| 910 | */ |
| 911 | return; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | /* |
| 916 | * Try to block migration while FWNMI is being handled, so the |
| 917 | * machine check handler runs where the information passed to it |
| 918 | * actually makes sense. This shouldn't actually block migration, |
| 919 | * only delay it slightly, assuming migration is retried. If the |
| 920 | * attempt to block fails, carry on. Unfortunately, it always |
| 921 | * fails when running with -only-migrate. A proper interface to |
| 922 | * delay migration completion for a bit could avoid that. |
| 923 | */ |
| 924 | error_setg(&spapr->fwnmi_migration_blocker, |
| 925 | "A machine check is being handled during migration. The handler" |
| 926 | "may run and log hardware error on the destination"); |
| 927 | |
| 928 | ret = migrate_add_blocker(&spapr->fwnmi_migration_blocker, NULL); |
| 929 | if (ret == -EBUSY) { |
| 930 | warn_report("Received a fwnmi while migration was in progress"); |
| 931 | } |
| 932 | |
| 933 | spapr_mce_dispatch_elog(spapr, cpu, recovered); |
| 934 | } |
| 935 | |
| 936 | static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 937 | uint32_t token, uint32_t nargs, |
| 938 | target_ulong args, |
| 939 | uint32_t nret, target_ulong rets) |
| 940 | { |
| 941 | uint32_t mask, buf, len, event_len; |
| 942 | SpaprEventLogEntry *event; |
| 943 | struct rtas_error_log header; |
| 944 | int i; |
| 945 | |
| 946 | if ((nargs < 6) || (nargs > 7) || nret != 1) { |
| 947 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
| 948 | return; |
| 949 | } |
| 950 | |
| 951 | mask = rtas_ld(args, 2); |
| 952 | buf = rtas_ld(args, 4); |
| 953 | len = rtas_ld(args, 5); |
| 954 | |
| 955 | event = rtas_event_log_dequeue(spapr, mask); |
| 956 | if (!event) { |
| 957 | goto out_no_events; |
| 958 | } |
| 959 | |
| 960 | event_len = event->extended_length + sizeof(header); |
| 961 | |
| 962 | if (event_len < len) { |
| 963 | len = event_len; |
| 964 | } |
| 965 | |
| 966 | header.summary = cpu_to_be32(event->summary); |
| 967 | header.extended_length = cpu_to_be32(event->extended_length); |
| 968 | physical_memory_write(buf, &header, sizeof(header)); |
| 969 | physical_memory_write(buf + sizeof(header), event->extended_log, |
| 970 | event->extended_length); |
| 971 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
| 972 | g_free(event->extended_log); |
| 973 | g_free(event); |
| 974 | |
| 975 | /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if |
| 976 | * there are still pending events to be fetched via check-exception. We |
| 977 | * do the latter here, since our code relies on edge-triggered |
| 978 | * interrupts. |
| 979 | */ |
| 980 | for (i = 0; i < EVENT_CLASS_MAX; i++) { |
| 981 | if (rtas_event_log_contains(spapr, EVENT_CLASS_MASK(i))) { |
| 982 | const SpaprEventSource *source = |
| 983 | spapr_event_sources_get_source(spapr->event_sources, i); |
| 984 | |
| 985 | g_assert(source->enabled); |
| 986 | qemu_irq_pulse(spapr_qirq(spapr, source->irq)); |
| 987 | } |
| 988 | } |
| 989 | |
| 990 | return; |
| 991 | |
| 992 | out_no_events: |
| 993 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); |
| 994 | } |
| 995 | |
| 996 | static void event_scan(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 997 | uint32_t token, uint32_t nargs, |
| 998 | target_ulong args, |
| 999 | uint32_t nret, target_ulong rets) |
| 1000 | { |
| 1001 | int i; |
| 1002 | if (nargs != 4 || nret != 1) { |
| 1003 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
| 1004 | return; |
| 1005 | } |
| 1006 | |
| 1007 | for (i = 0; i < EVENT_CLASS_MAX; i++) { |
| 1008 | if (rtas_event_log_contains(spapr, EVENT_CLASS_MASK(i))) { |
| 1009 | const SpaprEventSource *source = |
| 1010 | spapr_event_sources_get_source(spapr->event_sources, i); |
| 1011 | |
| 1012 | g_assert(source->enabled); |
| 1013 | qemu_irq_pulse(spapr_qirq(spapr, source->irq)); |
| 1014 | } |
| 1015 | } |
| 1016 | |
| 1017 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); |
| 1018 | } |
| 1019 | |
| 1020 | void spapr_clear_pending_events(SpaprMachineState *spapr) |
| 1021 | { |
| 1022 | SpaprEventLogEntry *entry = NULL, *next_entry; |
| 1023 | |
| 1024 | QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) { |
| 1025 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); |
| 1026 | g_free(entry->extended_log); |
| 1027 | g_free(entry); |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr) |
| 1032 | { |
| 1033 | SpaprEventLogEntry *entry = NULL, *next_entry; |
| 1034 | |
| 1035 | QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) { |
| 1036 | if (spapr_event_log_entry_type(entry) == RTAS_LOG_TYPE_HOTPLUG) { |
| 1037 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); |
| 1038 | g_free(entry->extended_log); |
| 1039 | g_free(entry); |
| 1040 | } |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | void spapr_events_init(SpaprMachineState *spapr) |
| 1045 | { |
| 1046 | spapr_irq_claim(spapr, SPAPR_IRQ_EPOW, false, &error_fatal); |
| 1047 | |
| 1048 | QTAILQ_INIT(&spapr->pending_events); |
| 1049 | |
| 1050 | spapr->event_sources = spapr_event_sources_new(); |
| 1051 | |
| 1052 | spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_EPOW, |
| 1053 | SPAPR_IRQ_EPOW); |
| 1054 | |
| 1055 | /* NOTE: if machine supports modern/dedicated hotplug event source, |
| 1056 | * we add it to the device-tree unconditionally. This means we may |
| 1057 | * have cases where the source is enabled in QEMU, but unused by the |
| 1058 | * guest because it does not support modern hotplug events, so we |
| 1059 | * take care to rely on checking for negotiation of OV5_HP_EVT option |
| 1060 | * before attempting to use it to signal events, rather than simply |
| 1061 | * checking that it's enabled. |
| 1062 | */ |
| 1063 | if (spapr->use_hotplug_event_source) { |
| 1064 | spapr_irq_claim(spapr, SPAPR_IRQ_HOTPLUG, false, &error_fatal); |
| 1065 | |
| 1066 | spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT_PLUG, |
| 1067 | SPAPR_IRQ_HOTPLUG); |
| 1068 | } |
| 1069 | |
| 1070 | spapr->epow_notifier.notify = spapr_powerdown_req; |
| 1071 | qemu_register_powerdown_notifier(&spapr->epow_notifier); |
| 1072 | spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception", |
| 1073 | check_exception); |
| 1074 | spapr_rtas_register(RTAS_EVENT_SCAN, "event-scan", event_scan); |
| 1075 | } |