| 1 | #include "qemu/osdep.h" |
| 2 | #include "qemu/cutils.h" |
| 3 | #include "qapi/error.h" |
| 4 | #include "system/hw_accel.h" |
| 5 | #include "system/physmem.h" |
| 6 | #include "system/runstate.h" |
| 7 | #include "system/tcg.h" |
| 8 | #include "qemu/log.h" |
| 9 | #include "qemu/main-loop.h" |
| 10 | #include "qemu/module.h" |
| 11 | #include "qemu/error-report.h" |
| 12 | #include "exec/translation-block.h" |
| 13 | #include "exec/target_page.h" |
| 14 | #include "helper_regs.h" |
| 15 | #include "hw/ppc/ppc.h" |
| 16 | #include "hw/ppc/spapr.h" |
| 17 | #include "hw/ppc/spapr_cpu_core.h" |
| 18 | #include "hw/ppc/spapr_nested.h" |
| 19 | #include "mmu-hash64.h" |
| 20 | #include "cpu-models.h" |
| 21 | #include "trace.h" |
| 22 | #include "kvm_ppc.h" |
| 23 | #include "hw/ppc/fdt.h" |
| 24 | #include "hw/ppc/spapr_ovec.h" |
| 25 | #include "hw/ppc/spapr_numa.h" |
| 26 | #include "mmu-book3s-v3.h" |
| 27 | #include "hw/mem/memory-device.h" |
| 28 | #include "exec/cpu-common.h" |
| 29 | |
| 30 | bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) |
| 31 | { |
| 32 | MachineState *machine = MACHINE(spapr); |
| 33 | DeviceMemoryState *dms = machine->device_memory; |
| 34 | |
| 35 | if (addr < machine->ram_size) { |
| 36 | return true; |
| 37 | } |
| 38 | if (dms && (addr >= dms->base) |
| 39 | && ((addr - dms->base) < memory_region_size(&dms->mr))) { |
| 40 | return true; |
| 41 | } |
| 42 | |
| 43 | return false; |
| 44 | } |
| 45 | |
| 46 | /* Convert a return code from the KVM ioctl()s implementing resize HPT |
| 47 | * into a PAPR hypercall return code */ |
| 48 | static target_ulong resize_hpt_convert_rc(int ret) |
| 49 | { |
| 50 | if (ret >= 100000) { |
| 51 | return H_LONG_BUSY_ORDER_100_SEC; |
| 52 | } else if (ret >= 10000) { |
| 53 | return H_LONG_BUSY_ORDER_10_SEC; |
| 54 | } else if (ret >= 1000) { |
| 55 | return H_LONG_BUSY_ORDER_1_SEC; |
| 56 | } else if (ret >= 100) { |
| 57 | return H_LONG_BUSY_ORDER_100_MSEC; |
| 58 | } else if (ret >= 10) { |
| 59 | return H_LONG_BUSY_ORDER_10_MSEC; |
| 60 | } else if (ret > 0) { |
| 61 | return H_LONG_BUSY_ORDER_1_MSEC; |
| 62 | } |
| 63 | |
| 64 | switch (ret) { |
| 65 | case 0: |
| 66 | return H_SUCCESS; |
| 67 | case -EPERM: |
| 68 | return H_AUTHORITY; |
| 69 | case -EINVAL: |
| 70 | return H_PARAMETER; |
| 71 | case -ENXIO: |
| 72 | return H_CLOSED; |
| 73 | case -ENOSPC: |
| 74 | return H_PTEG_FULL; |
| 75 | case -EBUSY: |
| 76 | return H_BUSY; |
| 77 | case -ENOMEM: |
| 78 | return H_NO_MEM; |
| 79 | default: |
| 80 | return H_HARDWARE; |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, |
| 85 | SpaprMachineState *spapr, |
| 86 | target_ulong opcode, |
| 87 | target_ulong *args) |
| 88 | { |
| 89 | target_ulong flags = args[0]; |
| 90 | int shift = args[1]; |
| 91 | uint64_t current_ram_size; |
| 92 | int rc; |
| 93 | |
| 94 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { |
| 95 | return H_AUTHORITY; |
| 96 | } |
| 97 | |
| 98 | if (!spapr->htab_shift) { |
| 99 | /* Radix guest, no HPT */ |
| 100 | return H_NOT_AVAILABLE; |
| 101 | } |
| 102 | |
| 103 | trace_spapr_h_resize_hpt_prepare(flags, shift); |
| 104 | |
| 105 | if (flags != 0) { |
| 106 | return H_PARAMETER; |
| 107 | } |
| 108 | |
| 109 | if (shift && ((shift < 18) || (shift > 46))) { |
| 110 | return H_PARAMETER; |
| 111 | } |
| 112 | |
| 113 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); |
| 114 | |
| 115 | /* We only allow the guest to allocate an HPT one order above what |
| 116 | * we'd normally give them (to stop a small guest claiming a huge |
| 117 | * chunk of resources in the HPT */ |
| 118 | if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { |
| 119 | return H_RESOURCE; |
| 120 | } |
| 121 | |
| 122 | rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); |
| 123 | if (rc != -ENOSYS) { |
| 124 | return resize_hpt_convert_rc(rc); |
| 125 | } |
| 126 | |
| 127 | if (kvm_enabled()) { |
| 128 | return H_HARDWARE; |
| 129 | } else if (tcg_enabled()) { |
| 130 | return vhyp_mmu_resize_hpt_prepare(cpu, spapr, shift); |
| 131 | } else { |
| 132 | g_assert_not_reached(); |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) |
| 137 | { |
| 138 | int ret; |
| 139 | |
| 140 | cpu_synchronize_state(cs); |
| 141 | |
| 142 | ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); |
| 143 | if (ret < 0) { |
| 144 | error_report("failed to push sregs to KVM: %s", strerror(-ret)); |
| 145 | exit(1); |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | void push_sregs_to_kvm_pr(SpaprMachineState *spapr) |
| 150 | { |
| 151 | CPUState *cs; |
| 152 | |
| 153 | /* |
| 154 | * This is a hack for the benefit of KVM PR - it abuses the SDR1 |
| 155 | * slot in kvm_sregs to communicate the userspace address of the |
| 156 | * HPT |
| 157 | */ |
| 158 | if (!kvm_enabled() || !spapr->htab) { |
| 159 | return; |
| 160 | } |
| 161 | |
| 162 | CPU_FOREACH(cs) { |
| 163 | run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, |
| 168 | SpaprMachineState *spapr, |
| 169 | target_ulong opcode, |
| 170 | target_ulong *args) |
| 171 | { |
| 172 | target_ulong flags = args[0]; |
| 173 | target_ulong shift = args[1]; |
| 174 | int rc; |
| 175 | |
| 176 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { |
| 177 | return H_AUTHORITY; |
| 178 | } |
| 179 | |
| 180 | if (!spapr->htab_shift) { |
| 181 | /* Radix guest, no HPT */ |
| 182 | return H_NOT_AVAILABLE; |
| 183 | } |
| 184 | |
| 185 | trace_spapr_h_resize_hpt_commit(flags, shift); |
| 186 | |
| 187 | rc = kvmppc_resize_hpt_commit(cpu, flags, shift); |
| 188 | if (rc != -ENOSYS) { |
| 189 | rc = resize_hpt_convert_rc(rc); |
| 190 | if (rc == H_SUCCESS) { |
| 191 | /* Need to set the new htab_shift in the machine state */ |
| 192 | spapr->htab_shift = shift; |
| 193 | } |
| 194 | return rc; |
| 195 | } |
| 196 | |
| 197 | if (kvm_enabled()) { |
| 198 | return H_HARDWARE; |
| 199 | } else if (tcg_enabled()) { |
| 200 | return vhyp_mmu_resize_hpt_commit(cpu, spapr, flags, shift); |
| 201 | } else { |
| 202 | g_assert_not_reached(); |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | |
| 207 | |
| 208 | static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 209 | target_ulong opcode, target_ulong *args) |
| 210 | { |
| 211 | cpu_synchronize_state(CPU(cpu)); |
| 212 | cpu->env.spr[SPR_SPRG0] = args[0]; |
| 213 | |
| 214 | return H_SUCCESS; |
| 215 | } |
| 216 | |
| 217 | static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 218 | target_ulong opcode, target_ulong *args) |
| 219 | { |
| 220 | if (!ppc_has_spr(cpu, SPR_DABR)) { |
| 221 | return H_HARDWARE; /* DABR register not available */ |
| 222 | } |
| 223 | cpu_synchronize_state(CPU(cpu)); |
| 224 | |
| 225 | if (ppc_has_spr(cpu, SPR_DABRX)) { |
| 226 | cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ |
| 227 | } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ |
| 228 | return H_RESERVED_DABR; |
| 229 | } |
| 230 | |
| 231 | cpu->env.spr[SPR_DABR] = args[0]; |
| 232 | return H_SUCCESS; |
| 233 | } |
| 234 | |
| 235 | static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 236 | target_ulong opcode, target_ulong *args) |
| 237 | { |
| 238 | target_ulong dabrx = args[1]; |
| 239 | |
| 240 | if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { |
| 241 | return H_HARDWARE; |
| 242 | } |
| 243 | |
| 244 | if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 |
| 245 | || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { |
| 246 | return H_PARAMETER; |
| 247 | } |
| 248 | |
| 249 | cpu_synchronize_state(CPU(cpu)); |
| 250 | cpu->env.spr[SPR_DABRX] = dabrx; |
| 251 | cpu->env.spr[SPR_DABR] = args[0]; |
| 252 | |
| 253 | return H_SUCCESS; |
| 254 | } |
| 255 | |
| 256 | static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 257 | target_ulong opcode, target_ulong *args) |
| 258 | { |
| 259 | target_ulong flags = args[0]; |
| 260 | hwaddr dst = args[1]; |
| 261 | hwaddr src = args[2]; |
| 262 | hwaddr len = TARGET_PAGE_SIZE; |
| 263 | uint8_t *pdst, *psrc; |
| 264 | target_long ret = H_SUCCESS; |
| 265 | |
| 266 | if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE |
| 267 | | H_COPY_PAGE | H_ZERO_PAGE)) { |
| 268 | qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", |
| 269 | flags); |
| 270 | return H_PARAMETER; |
| 271 | } |
| 272 | |
| 273 | /* Map-in destination */ |
| 274 | if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { |
| 275 | return H_PARAMETER; |
| 276 | } |
| 277 | pdst = physical_memory_map(dst, &len, true); |
| 278 | if (!pdst || len != TARGET_PAGE_SIZE) { |
| 279 | return H_PARAMETER; |
| 280 | } |
| 281 | |
| 282 | if (flags & H_COPY_PAGE) { |
| 283 | /* Map-in source, copy to destination, and unmap source again */ |
| 284 | if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { |
| 285 | ret = H_PARAMETER; |
| 286 | goto unmap_out; |
| 287 | } |
| 288 | psrc = physical_memory_map(src, &len, false); |
| 289 | if (!psrc || len != TARGET_PAGE_SIZE) { |
| 290 | ret = H_PARAMETER; |
| 291 | goto unmap_out; |
| 292 | } |
| 293 | memcpy(pdst, psrc, len); |
| 294 | physical_memory_unmap(psrc, len, 0, len); |
| 295 | } else if (flags & H_ZERO_PAGE) { |
| 296 | memset(pdst, 0, len); /* Just clear the destination page */ |
| 297 | } |
| 298 | |
| 299 | if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { |
| 300 | kvmppc_dcbst_range(cpu, pdst, len); |
| 301 | } |
| 302 | if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { |
| 303 | if (kvm_enabled()) { |
| 304 | kvmppc_icbi_range(cpu, pdst, len); |
| 305 | } else if (tcg_enabled()) { |
| 306 | tb_invalidate_phys_range(CPU(cpu), dst, dst + len - 1); |
| 307 | } else { |
| 308 | g_assert_not_reached(); |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | unmap_out: |
| 313 | physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); |
| 314 | return ret; |
| 315 | } |
| 316 | |
| 317 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
| 318 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL |
| 319 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL |
| 320 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL |
| 321 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL |
| 322 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL |
| 323 | |
| 324 | static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) |
| 325 | { |
| 326 | CPUState *cs = CPU(cpu); |
| 327 | CPUPPCState *env = &cpu->env; |
| 328 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 329 | uint16_t size; |
| 330 | uint8_t tmp; |
| 331 | |
| 332 | if (vpa == 0) { |
| 333 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); |
| 334 | return H_HARDWARE; |
| 335 | } |
| 336 | |
| 337 | if (vpa % env->dcache_line_size) { |
| 338 | return H_PARAMETER; |
| 339 | } |
| 340 | /* FIXME: bounds check the address */ |
| 341 | |
| 342 | size = lduw_be_phys(cs->as, vpa + 0x4); |
| 343 | |
| 344 | if (size < VPA_MIN_SIZE) { |
| 345 | return H_PARAMETER; |
| 346 | } |
| 347 | |
| 348 | /* VPA is not allowed to cross a page boundary */ |
| 349 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { |
| 350 | return H_PARAMETER; |
| 351 | } |
| 352 | |
| 353 | spapr_cpu->vpa_addr = vpa; |
| 354 | |
| 355 | tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); |
| 356 | tmp |= VPA_SHARED_PROC_VAL; |
| 357 | stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
| 358 | |
| 359 | return H_SUCCESS; |
| 360 | } |
| 361 | |
| 362 | static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) |
| 363 | { |
| 364 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 365 | |
| 366 | if (spapr_cpu->slb_shadow_addr) { |
| 367 | return H_RESOURCE; |
| 368 | } |
| 369 | |
| 370 | if (spapr_cpu->dtl_addr) { |
| 371 | return H_RESOURCE; |
| 372 | } |
| 373 | |
| 374 | spapr_cpu->vpa_addr = 0; |
| 375 | return H_SUCCESS; |
| 376 | } |
| 377 | |
| 378 | static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) |
| 379 | { |
| 380 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 381 | uint32_t size; |
| 382 | |
| 383 | if (addr == 0) { |
| 384 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); |
| 385 | return H_HARDWARE; |
| 386 | } |
| 387 | |
| 388 | size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); |
| 389 | if (size < 0x8) { |
| 390 | return H_PARAMETER; |
| 391 | } |
| 392 | |
| 393 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { |
| 394 | return H_PARAMETER; |
| 395 | } |
| 396 | |
| 397 | if (!spapr_cpu->vpa_addr) { |
| 398 | return H_RESOURCE; |
| 399 | } |
| 400 | |
| 401 | spapr_cpu->slb_shadow_addr = addr; |
| 402 | spapr_cpu->slb_shadow_size = size; |
| 403 | |
| 404 | return H_SUCCESS; |
| 405 | } |
| 406 | |
| 407 | static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) |
| 408 | { |
| 409 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 410 | |
| 411 | spapr_cpu->slb_shadow_addr = 0; |
| 412 | spapr_cpu->slb_shadow_size = 0; |
| 413 | return H_SUCCESS; |
| 414 | } |
| 415 | |
| 416 | static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) |
| 417 | { |
| 418 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 419 | uint32_t size; |
| 420 | |
| 421 | if (addr == 0) { |
| 422 | hcall_dprintf("Can't cope with DTL at logical 0\n"); |
| 423 | return H_HARDWARE; |
| 424 | } |
| 425 | |
| 426 | size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); |
| 427 | |
| 428 | if (size < 48) { |
| 429 | return H_PARAMETER; |
| 430 | } |
| 431 | |
| 432 | if (!spapr_cpu->vpa_addr) { |
| 433 | return H_RESOURCE; |
| 434 | } |
| 435 | |
| 436 | spapr_cpu->dtl_addr = addr; |
| 437 | spapr_cpu->dtl_size = size; |
| 438 | |
| 439 | return H_SUCCESS; |
| 440 | } |
| 441 | |
| 442 | static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) |
| 443 | { |
| 444 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 445 | |
| 446 | spapr_cpu->dtl_addr = 0; |
| 447 | spapr_cpu->dtl_size = 0; |
| 448 | |
| 449 | return H_SUCCESS; |
| 450 | } |
| 451 | |
| 452 | static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 453 | target_ulong opcode, target_ulong *args) |
| 454 | { |
| 455 | target_ulong flags = args[0]; |
| 456 | target_ulong procno = args[1]; |
| 457 | target_ulong vpa = args[2]; |
| 458 | target_ulong ret = H_PARAMETER; |
| 459 | PowerPCCPU *tcpu; |
| 460 | |
| 461 | tcpu = spapr_find_cpu(procno); |
| 462 | if (!tcpu) { |
| 463 | return H_PARAMETER; |
| 464 | } |
| 465 | |
| 466 | switch (flags) { |
| 467 | case FLAGS_REGISTER_VPA: |
| 468 | ret = register_vpa(tcpu, vpa); |
| 469 | break; |
| 470 | |
| 471 | case FLAGS_DEREGISTER_VPA: |
| 472 | ret = deregister_vpa(tcpu, vpa); |
| 473 | break; |
| 474 | |
| 475 | case FLAGS_REGISTER_SLBSHADOW: |
| 476 | ret = register_slb_shadow(tcpu, vpa); |
| 477 | break; |
| 478 | |
| 479 | case FLAGS_DEREGISTER_SLBSHADOW: |
| 480 | ret = deregister_slb_shadow(tcpu, vpa); |
| 481 | break; |
| 482 | |
| 483 | case FLAGS_REGISTER_DTL: |
| 484 | ret = register_dtl(tcpu, vpa); |
| 485 | break; |
| 486 | |
| 487 | case FLAGS_DEREGISTER_DTL: |
| 488 | ret = deregister_dtl(tcpu, vpa); |
| 489 | break; |
| 490 | } |
| 491 | |
| 492 | return ret; |
| 493 | } |
| 494 | |
| 495 | static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 496 | target_ulong opcode, target_ulong *args) |
| 497 | { |
| 498 | CPUPPCState *env = &cpu->env; |
| 499 | CPUState *cs = CPU(cpu); |
| 500 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 501 | |
| 502 | env->msr |= (1ULL << MSR_EE); |
| 503 | hreg_compute_hflags(env); |
| 504 | ppc_maybe_interrupt(env); |
| 505 | |
| 506 | if (spapr_cpu->prod) { |
| 507 | spapr_cpu->prod = false; |
| 508 | return H_SUCCESS; |
| 509 | } |
| 510 | |
| 511 | if (!cpu_has_work(cs)) { |
| 512 | cs->halted = 1; |
| 513 | cs->exception_index = EXCP_HLT; |
| 514 | ppc_maybe_interrupt(env); |
| 515 | cpu_exit(cs); |
| 516 | } |
| 517 | |
| 518 | return H_SUCCESS; |
| 519 | } |
| 520 | |
| 521 | /* |
| 522 | * Confer to self, aka join. Cede could use the same pattern as well, if |
| 523 | * EXCP_HLT can be changed to ECXP_HALTED. |
| 524 | */ |
| 525 | static target_ulong h_confer_self(PowerPCCPU *cpu) |
| 526 | { |
| 527 | CPUState *cs = CPU(cpu); |
| 528 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 529 | |
| 530 | if (spapr_cpu->prod) { |
| 531 | spapr_cpu->prod = false; |
| 532 | return H_SUCCESS; |
| 533 | } |
| 534 | cs->halted = 1; |
| 535 | cs->exception_index = EXCP_HALTED; |
| 536 | ppc_maybe_interrupt(&cpu->env); |
| 537 | cpu_exit(cs); |
| 538 | |
| 539 | return H_SUCCESS; |
| 540 | } |
| 541 | |
| 542 | static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 543 | target_ulong opcode, target_ulong *args) |
| 544 | { |
| 545 | CPUPPCState *env = &cpu->env; |
| 546 | CPUState *cs; |
| 547 | bool last_unjoined = true; |
| 548 | |
| 549 | if (env->msr & (1ULL << MSR_EE)) { |
| 550 | return H_BAD_MODE; |
| 551 | } |
| 552 | |
| 553 | /* |
| 554 | * Must not join the last CPU running. Interestingly, no such restriction |
| 555 | * for H_CONFER-to-self, but that is probably not intended to be used |
| 556 | * when H_JOIN is available. |
| 557 | */ |
| 558 | CPU_FOREACH(cs) { |
| 559 | PowerPCCPU *c = POWERPC_CPU(cs); |
| 560 | CPUPPCState *e = &c->env; |
| 561 | if (c == cpu) { |
| 562 | continue; |
| 563 | } |
| 564 | |
| 565 | /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ |
| 566 | if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { |
| 567 | last_unjoined = false; |
| 568 | break; |
| 569 | } |
| 570 | } |
| 571 | if (last_unjoined) { |
| 572 | return H_CONTINUE; |
| 573 | } |
| 574 | |
| 575 | return h_confer_self(cpu); |
| 576 | } |
| 577 | |
| 578 | static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 579 | target_ulong opcode, target_ulong *args) |
| 580 | { |
| 581 | target_long target = args[0]; |
| 582 | uint32_t dispatch = args[1]; |
| 583 | CPUState *cs = CPU(cpu); |
| 584 | SpaprCpuState *spapr_cpu; |
| 585 | |
| 586 | assert(tcg_enabled()); /* KVM will have handled this */ |
| 587 | |
| 588 | /* |
| 589 | * -1 means confer to all other CPUs without dispatch counter check, |
| 590 | * otherwise it's a targeted confer. |
| 591 | */ |
| 592 | if (target != -1) { |
| 593 | PowerPCCPU *target_cpu = spapr_find_cpu(target); |
| 594 | uint32_t target_dispatch; |
| 595 | |
| 596 | if (!target_cpu) { |
| 597 | return H_PARAMETER; |
| 598 | } |
| 599 | |
| 600 | /* |
| 601 | * target == self is a special case, we wait until prodded, without |
| 602 | * dispatch counter check. |
| 603 | */ |
| 604 | if (cpu == target_cpu) { |
| 605 | return h_confer_self(cpu); |
| 606 | } |
| 607 | |
| 608 | spapr_cpu = spapr_cpu_state(target_cpu); |
| 609 | if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { |
| 610 | return H_SUCCESS; |
| 611 | } |
| 612 | |
| 613 | target_dispatch = ldl_be_phys(cs->as, |
| 614 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); |
| 615 | if (target_dispatch != dispatch) { |
| 616 | return H_SUCCESS; |
| 617 | } |
| 618 | |
| 619 | /* |
| 620 | * The targeted confer does not do anything special beyond yielding |
| 621 | * the current vCPU, but even this should be better than nothing. |
| 622 | * At least for single-threaded tcg, it gives the target a chance to |
| 623 | * run before we run again. Multi-threaded tcg does not really do |
| 624 | * anything with EXCP_YIELD yet. |
| 625 | */ |
| 626 | } |
| 627 | |
| 628 | cs->exception_index = EXCP_YIELD; |
| 629 | cpu_exit(cs); |
| 630 | |
| 631 | return H_SUCCESS; |
| 632 | } |
| 633 | |
| 634 | static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 635 | target_ulong opcode, target_ulong *args) |
| 636 | { |
| 637 | target_long target = args[0]; |
| 638 | PowerPCCPU *tcpu; |
| 639 | CPUState *cs; |
| 640 | SpaprCpuState *spapr_cpu; |
| 641 | |
| 642 | tcpu = spapr_find_cpu(target); |
| 643 | cs = CPU(tcpu); |
| 644 | if (!cs) { |
| 645 | return H_PARAMETER; |
| 646 | } |
| 647 | |
| 648 | spapr_cpu = spapr_cpu_state(tcpu); |
| 649 | spapr_cpu->prod = true; |
| 650 | cs->halted = 0; |
| 651 | ppc_maybe_interrupt(&cpu->env); |
| 652 | qemu_cpu_kick(cs); |
| 653 | |
| 654 | return H_SUCCESS; |
| 655 | } |
| 656 | |
| 657 | static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 658 | target_ulong opcode, target_ulong *args) |
| 659 | { |
| 660 | target_ulong rtas_r3 = args[0]; |
| 661 | uint32_t token = rtas_ld(rtas_r3, 0); |
| 662 | uint32_t nargs = rtas_ld(rtas_r3, 1); |
| 663 | uint32_t nret = rtas_ld(rtas_r3, 2); |
| 664 | |
| 665 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
| 666 | nret, rtas_r3 + 12 + 4*nargs); |
| 667 | } |
| 668 | |
| 669 | static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 670 | target_ulong opcode, target_ulong *args) |
| 671 | { |
| 672 | CPUState *cs = CPU(cpu); |
| 673 | target_ulong size = args[0]; |
| 674 | target_ulong addr = args[1]; |
| 675 | |
| 676 | switch (size) { |
| 677 | case 1: |
| 678 | args[0] = ldub_phys(cs->as, addr); |
| 679 | return H_SUCCESS; |
| 680 | case 2: |
| 681 | args[0] = lduw_phys(cs->as, addr); |
| 682 | return H_SUCCESS; |
| 683 | case 4: |
| 684 | args[0] = ldl_phys(cs->as, addr); |
| 685 | return H_SUCCESS; |
| 686 | case 8: |
| 687 | args[0] = ldq_phys(cs->as, addr); |
| 688 | return H_SUCCESS; |
| 689 | } |
| 690 | return H_PARAMETER; |
| 691 | } |
| 692 | |
| 693 | static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 694 | target_ulong opcode, target_ulong *args) |
| 695 | { |
| 696 | CPUState *cs = CPU(cpu); |
| 697 | |
| 698 | target_ulong size = args[0]; |
| 699 | target_ulong addr = args[1]; |
| 700 | target_ulong val = args[2]; |
| 701 | |
| 702 | switch (size) { |
| 703 | case 1: |
| 704 | stb_phys(cs->as, addr, val); |
| 705 | return H_SUCCESS; |
| 706 | case 2: |
| 707 | stw_phys(cs->as, addr, val); |
| 708 | return H_SUCCESS; |
| 709 | case 4: |
| 710 | stl_phys(cs->as, addr, val); |
| 711 | return H_SUCCESS; |
| 712 | case 8: |
| 713 | stq_phys(cs->as, addr, val); |
| 714 | return H_SUCCESS; |
| 715 | } |
| 716 | return H_PARAMETER; |
| 717 | } |
| 718 | |
| 719 | static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 720 | target_ulong opcode, target_ulong *args) |
| 721 | { |
| 722 | CPUState *cs = CPU(cpu); |
| 723 | |
| 724 | target_ulong dst = args[0]; /* Destination address */ |
| 725 | target_ulong src = args[1]; /* Source address */ |
| 726 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ |
| 727 | target_ulong count = args[3]; /* Element count */ |
| 728 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ |
| 729 | uint64_t tmp; |
| 730 | unsigned int mask = (1 << esize) - 1; |
| 731 | int step = 1 << esize; |
| 732 | |
| 733 | if (count > 0x80000000) { |
| 734 | return H_PARAMETER; |
| 735 | } |
| 736 | |
| 737 | if ((dst & mask) || (src & mask) || (op > 1)) { |
| 738 | return H_PARAMETER; |
| 739 | } |
| 740 | |
| 741 | if (dst >= src && dst < (src + (count << esize))) { |
| 742 | dst = dst + ((count - 1) << esize); |
| 743 | src = src + ((count - 1) << esize); |
| 744 | step = -step; |
| 745 | } |
| 746 | |
| 747 | while (count--) { |
| 748 | switch (esize) { |
| 749 | case 0: |
| 750 | tmp = ldub_phys(cs->as, src); |
| 751 | break; |
| 752 | case 1: |
| 753 | tmp = lduw_phys(cs->as, src); |
| 754 | break; |
| 755 | case 2: |
| 756 | tmp = ldl_phys(cs->as, src); |
| 757 | break; |
| 758 | case 3: |
| 759 | tmp = ldq_phys(cs->as, src); |
| 760 | break; |
| 761 | default: |
| 762 | return H_PARAMETER; |
| 763 | } |
| 764 | if (op == 1) { |
| 765 | tmp = ~tmp; |
| 766 | } |
| 767 | switch (esize) { |
| 768 | case 0: |
| 769 | stb_phys(cs->as, dst, tmp); |
| 770 | break; |
| 771 | case 1: |
| 772 | stw_phys(cs->as, dst, tmp); |
| 773 | break; |
| 774 | case 2: |
| 775 | stl_phys(cs->as, dst, tmp); |
| 776 | break; |
| 777 | case 3: |
| 778 | stq_phys(cs->as, dst, tmp); |
| 779 | break; |
| 780 | } |
| 781 | dst = dst + step; |
| 782 | src = src + step; |
| 783 | } |
| 784 | |
| 785 | return H_SUCCESS; |
| 786 | } |
| 787 | |
| 788 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 789 | target_ulong opcode, target_ulong *args) |
| 790 | { |
| 791 | /* Nothing to do on emulation, KVM will trap this in the kernel */ |
| 792 | return H_SUCCESS; |
| 793 | } |
| 794 | |
| 795 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 796 | target_ulong opcode, target_ulong *args) |
| 797 | { |
| 798 | /* Nothing to do on emulation, KVM will trap this in the kernel */ |
| 799 | return H_SUCCESS; |
| 800 | } |
| 801 | |
| 802 | static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, |
| 803 | SpaprMachineState *spapr, |
| 804 | target_ulong mflags, |
| 805 | target_ulong value1, |
| 806 | target_ulong value2) |
| 807 | { |
| 808 | CPUPPCState *env = &cpu->env; |
| 809 | |
| 810 | assert(tcg_enabled()); /* KVM will have handled this */ |
| 811 | |
| 812 | if (mflags) { |
| 813 | return H_UNSUPPORTED_FLAG; |
| 814 | } |
| 815 | if (value2) { |
| 816 | return H_P4; |
| 817 | } |
| 818 | if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { |
| 819 | return H_P3; |
| 820 | } |
| 821 | |
| 822 | ppc_store_ciabr(env, value1); |
| 823 | |
| 824 | return H_SUCCESS; |
| 825 | } |
| 826 | |
| 827 | static target_ulong h_set_mode_resource_set_dawr(PowerPCCPU *cpu, |
| 828 | SpaprMachineState *spapr, |
| 829 | target_ulong mflags, |
| 830 | target_ulong resource, |
| 831 | target_ulong value1, |
| 832 | target_ulong value2) |
| 833 | { |
| 834 | CPUPPCState *env = &cpu->env; |
| 835 | |
| 836 | assert(tcg_enabled()); /* KVM will have handled this */ |
| 837 | |
| 838 | if (mflags) { |
| 839 | return H_UNSUPPORTED_FLAG; |
| 840 | } |
| 841 | if (value2 & PPC_BIT(61)) { |
| 842 | return H_P4; |
| 843 | } |
| 844 | |
| 845 | if (resource == H_SET_MODE_RESOURCE_SET_DAWR0) { |
| 846 | ppc_store_dawr0(env, value1); |
| 847 | ppc_store_dawrx0(env, value2); |
| 848 | } else if (resource == H_SET_MODE_RESOURCE_SET_DAWR1) { |
| 849 | ppc_store_dawr1(env, value1); |
| 850 | ppc_store_dawrx1(env, value2); |
| 851 | } else { |
| 852 | g_assert_not_reached(); |
| 853 | } |
| 854 | |
| 855 | return H_SUCCESS; |
| 856 | } |
| 857 | |
| 858 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
| 859 | SpaprMachineState *spapr, |
| 860 | target_ulong mflags, |
| 861 | target_ulong value1, |
| 862 | target_ulong value2) |
| 863 | { |
| 864 | if (value1) { |
| 865 | return H_P3; |
| 866 | } |
| 867 | if (value2) { |
| 868 | return H_P4; |
| 869 | } |
| 870 | |
| 871 | switch (mflags) { |
| 872 | case H_SET_MODE_ENDIAN_BIG: |
| 873 | spapr_set_all_lpcrs(0, LPCR_ILE); |
| 874 | spapr_pci_switch_vga(spapr, true); |
| 875 | return H_SUCCESS; |
| 876 | |
| 877 | case H_SET_MODE_ENDIAN_LITTLE: |
| 878 | spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); |
| 879 | spapr_pci_switch_vga(spapr, false); |
| 880 | return H_SUCCESS; |
| 881 | } |
| 882 | |
| 883 | return H_UNSUPPORTED_FLAG; |
| 884 | } |
| 885 | |
| 886 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
| 887 | SpaprMachineState *spapr, |
| 888 | target_ulong mflags, |
| 889 | target_ulong value1, |
| 890 | target_ulong value2) |
| 891 | { |
| 892 | if (value1) { |
| 893 | return H_P3; |
| 894 | } |
| 895 | |
| 896 | if (value2) { |
| 897 | return H_P4; |
| 898 | } |
| 899 | |
| 900 | /* |
| 901 | * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. |
| 902 | * It is supported for faithful emulation of bare metal systems, but for |
| 903 | * compatibility concerns we leave it out of the pseries machine. |
| 904 | */ |
| 905 | if (mflags != 0 && mflags != 3) { |
| 906 | return H_UNSUPPORTED_FLAG; |
| 907 | } |
| 908 | |
| 909 | if (mflags == 3) { |
| 910 | if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { |
| 911 | return H_UNSUPPORTED_FLAG; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); |
| 916 | |
| 917 | return H_SUCCESS; |
| 918 | } |
| 919 | |
| 920 | static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 921 | target_ulong opcode, target_ulong *args) |
| 922 | { |
| 923 | target_ulong resource = args[1]; |
| 924 | target_ulong ret = H_P2; |
| 925 | |
| 926 | switch (resource) { |
| 927 | case H_SET_MODE_RESOURCE_SET_CIABR: |
| 928 | ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], |
| 929 | args[3]); |
| 930 | break; |
| 931 | case H_SET_MODE_RESOURCE_SET_DAWR0: |
| 932 | case H_SET_MODE_RESOURCE_SET_DAWR1: |
| 933 | ret = h_set_mode_resource_set_dawr(cpu, spapr, args[0], args[1], |
| 934 | args[2], args[3]); |
| 935 | break; |
| 936 | case H_SET_MODE_RESOURCE_LE: |
| 937 | ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); |
| 938 | break; |
| 939 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
| 940 | ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], |
| 941 | args[2], args[3]); |
| 942 | break; |
| 943 | } |
| 944 | |
| 945 | return ret; |
| 946 | } |
| 947 | |
| 948 | static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 949 | target_ulong opcode, target_ulong *args) |
| 950 | { |
| 951 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", |
| 952 | opcode, " (H_CLEAN_SLB)"); |
| 953 | return H_FUNCTION; |
| 954 | } |
| 955 | |
| 956 | static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 957 | target_ulong opcode, target_ulong *args) |
| 958 | { |
| 959 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", |
| 960 | opcode, " (H_INVALIDATE_PID)"); |
| 961 | return H_FUNCTION; |
| 962 | } |
| 963 | |
| 964 | static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, |
| 965 | uint64_t patbe_old, uint64_t patbe_new) |
| 966 | { |
| 967 | /* |
| 968 | * We have 4 Options: |
| 969 | * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing |
| 970 | * HASH->RADIX : Free HPT |
| 971 | * RADIX->HASH : Allocate HPT |
| 972 | * NOTHING->HASH : Allocate HPT |
| 973 | * Note: NOTHING implies the case where we said the guest could choose |
| 974 | * later and so assumed radix and now it's called H_REG_PROC_TBL |
| 975 | */ |
| 976 | |
| 977 | if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { |
| 978 | /* We assume RADIX, so this catches all the "Do Nothing" cases */ |
| 979 | } else if (!(patbe_old & PATE1_GR)) { |
| 980 | /* HASH->RADIX : Free HPT */ |
| 981 | spapr_free_hpt(spapr); |
| 982 | } else if (!(patbe_new & PATE1_GR)) { |
| 983 | /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ |
| 984 | spapr_setup_hpt(spapr); |
| 985 | } |
| 986 | } |
| 987 | |
| 988 | #define FLAGS_MASK 0x01FULL |
| 989 | #define FLAG_MODIFY 0x10 |
| 990 | #define FLAG_REGISTER 0x08 |
| 991 | #define FLAG_RADIX 0x04 |
| 992 | #define FLAG_HASH_PROC_TBL 0x02 |
| 993 | #define FLAG_GTSE 0x01 |
| 994 | |
| 995 | static target_ulong h_register_process_table(PowerPCCPU *cpu, |
| 996 | SpaprMachineState *spapr, |
| 997 | target_ulong opcode, |
| 998 | target_ulong *args) |
| 999 | { |
| 1000 | target_ulong flags = args[0]; |
| 1001 | target_ulong proc_tbl = args[1]; |
| 1002 | target_ulong page_size = args[2]; |
| 1003 | target_ulong table_size = args[3]; |
| 1004 | target_ulong update_lpcr = 0; |
| 1005 | target_ulong table_byte_size; |
| 1006 | uint64_t cproc; |
| 1007 | |
| 1008 | if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ |
| 1009 | return H_PARAMETER; |
| 1010 | } |
| 1011 | if (flags & FLAG_MODIFY) { |
| 1012 | if (flags & FLAG_REGISTER) { |
| 1013 | /* Check process table alignment */ |
| 1014 | table_byte_size = 1ULL << (table_size + 12); |
| 1015 | if (proc_tbl & (table_byte_size - 1)) { |
| 1016 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1017 | "%s: process table not properly aligned: proc_tbl 0x" |
| 1018 | TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", |
| 1019 | __func__, proc_tbl, table_byte_size); |
| 1020 | } |
| 1021 | if (flags & FLAG_RADIX) { /* Register new RADIX process table */ |
| 1022 | if (proc_tbl & 0xfff || proc_tbl >> 60) { |
| 1023 | return H_P2; |
| 1024 | } else if (page_size) { |
| 1025 | return H_P3; |
| 1026 | } else if (table_size > 24) { |
| 1027 | return H_P4; |
| 1028 | } |
| 1029 | cproc = PATE1_GR | proc_tbl | table_size; |
| 1030 | } else { /* Register new HPT process table */ |
| 1031 | if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ |
| 1032 | /* TODO - Not Supported */ |
| 1033 | /* Technically caused by flag bits => H_PARAMETER */ |
| 1034 | return H_PARAMETER; |
| 1035 | } else { /* Hash with SLB */ |
| 1036 | if (proc_tbl >> 38) { |
| 1037 | return H_P2; |
| 1038 | } else if (page_size & ~0x7) { |
| 1039 | return H_P3; |
| 1040 | } else if (table_size > 24) { |
| 1041 | return H_P4; |
| 1042 | } |
| 1043 | } |
| 1044 | cproc = (proc_tbl << 25) | page_size << 5 | table_size; |
| 1045 | } |
| 1046 | |
| 1047 | } else { /* Deregister current process table */ |
| 1048 | /* |
| 1049 | * Set to benign value: (current GR) | 0. This allows |
| 1050 | * deregistration in KVM to succeed even if the radix bit |
| 1051 | * in flags doesn't match the radix bit in the old PATE. |
| 1052 | */ |
| 1053 | cproc = spapr->patb_entry & PATE1_GR; |
| 1054 | } |
| 1055 | } else { /* Maintain current registration */ |
| 1056 | if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { |
| 1057 | /* Technically caused by flag bits => H_PARAMETER */ |
| 1058 | return H_PARAMETER; /* Existing Process Table Mismatch */ |
| 1059 | } |
| 1060 | cproc = spapr->patb_entry; |
| 1061 | } |
| 1062 | |
| 1063 | /* Check if we need to setup OR free the hpt */ |
| 1064 | spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); |
| 1065 | |
| 1066 | spapr->patb_entry = cproc; /* Save new process table */ |
| 1067 | |
| 1068 | /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ |
| 1069 | if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ |
| 1070 | update_lpcr |= (LPCR_UPRT | LPCR_HR); |
| 1071 | else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ |
| 1072 | update_lpcr |= LPCR_UPRT; |
| 1073 | if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ |
| 1074 | update_lpcr |= LPCR_GTSE; |
| 1075 | |
| 1076 | spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); |
| 1077 | |
| 1078 | if (kvm_enabled()) { |
| 1079 | return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, |
| 1080 | flags & FLAG_GTSE, cproc); |
| 1081 | } |
| 1082 | return H_SUCCESS; |
| 1083 | } |
| 1084 | |
| 1085 | #define H_SIGNAL_SYS_RESET_ALL -1 |
| 1086 | #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 |
| 1087 | |
| 1088 | static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, |
| 1089 | SpaprMachineState *spapr, |
| 1090 | target_ulong opcode, target_ulong *args) |
| 1091 | { |
| 1092 | target_long target = args[0]; |
| 1093 | CPUState *cs; |
| 1094 | |
| 1095 | if (target < 0) { |
| 1096 | /* Broadcast */ |
| 1097 | if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { |
| 1098 | return H_PARAMETER; |
| 1099 | } |
| 1100 | |
| 1101 | CPU_FOREACH(cs) { |
| 1102 | PowerPCCPU *c = POWERPC_CPU(cs); |
| 1103 | |
| 1104 | if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { |
| 1105 | if (c == cpu) { |
| 1106 | continue; |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | /* Skip quiesced CPUs - they are in RTAS stopped state and |
| 1111 | * should not be reset. This prevents kdump hangs when CPUs |
| 1112 | * are hotplugged but not yet started by the guest. |
| 1113 | */ |
| 1114 | if (c->env.quiesced) { |
| 1115 | continue; |
| 1116 | } |
| 1117 | |
| 1118 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
| 1119 | } |
| 1120 | return H_SUCCESS; |
| 1121 | |
| 1122 | } else { |
| 1123 | /* Unicast */ |
| 1124 | cs = CPU(spapr_find_cpu(target)); |
| 1125 | if (cs) { |
| 1126 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
| 1127 | return H_SUCCESS; |
| 1128 | } |
| 1129 | return H_PARAMETER; |
| 1130 | } |
| 1131 | } |
| 1132 | |
| 1133 | /* Returns either a logical PVR or zero if none was found */ |
| 1134 | static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, |
| 1135 | target_ulong *addr, bool *raw_mode_supported) |
| 1136 | { |
| 1137 | bool explicit_match = false; /* Matched the CPU's real PVR */ |
| 1138 | uint32_t best_compat = 0; |
| 1139 | uint32_t compat_host_pvr = 0; |
| 1140 | int i; |
| 1141 | |
| 1142 | /* |
| 1143 | * We scan the supplied table of PVRs looking for two things |
| 1144 | * 1. Is our real CPU PVR in the list? |
| 1145 | * 2. What's the "best" listed logical PVR |
| 1146 | */ |
| 1147 | for (i = 0; i < 512; ++i) { |
| 1148 | uint32_t pvr, pvr_mask; |
| 1149 | |
| 1150 | pvr_mask = ldl_be_phys(&address_space_memory, *addr); |
| 1151 | pvr = ldl_be_phys(&address_space_memory, *addr + 4); |
| 1152 | *addr += 8; |
| 1153 | |
| 1154 | if (~pvr_mask & pvr) { |
| 1155 | break; /* Terminator record */ |
| 1156 | } |
| 1157 | |
| 1158 | if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { |
| 1159 | explicit_match = true; |
| 1160 | } else { |
| 1161 | if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { |
| 1162 | best_compat = pvr; |
| 1163 | } |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | if (explicit_match && kvm_enabled()) { |
| 1168 | compat_host_pvr = kvm_ppc_host_compat_pvr(); |
| 1169 | /* |
| 1170 | * If the host is booted in a compatibility mode, do not try booting in |
| 1171 | * the raw mode as it may allow KVM guests to boot with a higher CPU |
| 1172 | * version compared to what host was booted with; which should not be |
| 1173 | * allowed. |
| 1174 | */ |
| 1175 | if (compat_host_pvr) { |
| 1176 | explicit_match = false; |
| 1177 | } |
| 1178 | } |
| 1179 | |
| 1180 | *raw_mode_supported = explicit_match; |
| 1181 | |
| 1182 | /* Parsing finished */ |
| 1183 | trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); |
| 1184 | |
| 1185 | return best_compat; |
| 1186 | } |
| 1187 | |
| 1188 | static |
| 1189 | target_ulong do_client_architecture_support(PowerPCCPU *cpu, |
| 1190 | SpaprMachineState *spapr, |
| 1191 | target_ulong vec, |
| 1192 | target_ulong fdt_bufsize) |
| 1193 | { |
| 1194 | target_ulong ov_table; /* Working address in data buffer */ |
| 1195 | uint32_t cas_pvr; |
| 1196 | SpaprOptionVector *ov1_guest, *ov5_guest; |
| 1197 | bool guest_radix; |
| 1198 | bool raw_mode_supported = false; |
| 1199 | bool guest_xive; |
| 1200 | CPUState *cs; |
| 1201 | void *fdt; |
| 1202 | uint32_t max_compat = spapr->max_compat_pvr; |
| 1203 | |
| 1204 | /* CAS is supposed to be called early when only the boot vCPU is active. */ |
| 1205 | CPU_FOREACH(cs) { |
| 1206 | if (cs == CPU(cpu)) { |
| 1207 | continue; |
| 1208 | } |
| 1209 | if (!cs->halted) { |
| 1210 | warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); |
| 1211 | return H_MULTI_THREADS_ACTIVE; |
| 1212 | } |
| 1213 | } |
| 1214 | |
| 1215 | cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); |
| 1216 | if (!cas_pvr && (!raw_mode_supported || max_compat)) { |
| 1217 | /* |
| 1218 | * We couldn't find a suitable compatibility mode, and either |
| 1219 | * the guest doesn't support "raw" mode for this CPU, or "raw" |
| 1220 | * mode is disabled because a maximum compat mode is set. |
| 1221 | */ |
| 1222 | error_report("Couldn't negotiate a suitable PVR during CAS"); |
| 1223 | return H_HARDWARE; |
| 1224 | } |
| 1225 | |
| 1226 | /* Update CPUs */ |
| 1227 | if (cpu->compat_pvr != cas_pvr) { |
| 1228 | Error *local_err = NULL; |
| 1229 | |
| 1230 | if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { |
| 1231 | /* We fail to set compat mode (likely because running with KVM PR), |
| 1232 | * but maybe we can fallback to raw mode if the guest supports it. |
| 1233 | */ |
| 1234 | if (!raw_mode_supported) { |
| 1235 | error_report_err(local_err); |
| 1236 | return H_HARDWARE; |
| 1237 | } |
| 1238 | error_free(local_err); |
| 1239 | } |
| 1240 | } |
| 1241 | |
| 1242 | /* For the future use: here @ov_table points to the first option vector */ |
| 1243 | ov_table = vec; |
| 1244 | |
| 1245 | ov1_guest = spapr_ovec_parse_vector(ov_table, 1); |
| 1246 | if (!ov1_guest) { |
| 1247 | warn_report("guest didn't provide option vector 1"); |
| 1248 | return H_PARAMETER; |
| 1249 | } |
| 1250 | ov5_guest = spapr_ovec_parse_vector(ov_table, 5); |
| 1251 | if (!ov5_guest) { |
| 1252 | spapr_ovec_cleanup(ov1_guest); |
| 1253 | warn_report("guest didn't provide option vector 5"); |
| 1254 | return H_PARAMETER; |
| 1255 | } |
| 1256 | if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { |
| 1257 | error_report("guest requested hash and radix MMU, which is invalid."); |
| 1258 | exit(EXIT_FAILURE); |
| 1259 | } |
| 1260 | if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { |
| 1261 | error_report("guest requested an invalid interrupt mode"); |
| 1262 | exit(EXIT_FAILURE); |
| 1263 | } |
| 1264 | |
| 1265 | guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); |
| 1266 | |
| 1267 | guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); |
| 1268 | |
| 1269 | /* |
| 1270 | * HPT resizing is a bit of a special case, because when enabled |
| 1271 | * we assume an HPT guest will support it until it says it |
| 1272 | * doesn't, instead of assuming it won't support it until it says |
| 1273 | * it does. Strictly speaking that approach could break for |
| 1274 | * guests which don't make a CAS call, but those are so old we |
| 1275 | * don't care about them. Without that assumption we'd have to |
| 1276 | * make at least a temporary allocation of an HPT sized for max |
| 1277 | * memory, which could be impossibly difficult under KVM HV if |
| 1278 | * maxram is large. |
| 1279 | */ |
| 1280 | if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { |
| 1281 | int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); |
| 1282 | |
| 1283 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { |
| 1284 | error_report( |
| 1285 | "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); |
| 1286 | exit(1); |
| 1287 | } |
| 1288 | |
| 1289 | if (spapr->htab_shift < maxshift) { |
| 1290 | /* Guest doesn't know about HPT resizing, so we |
| 1291 | * pre-emptively resize for the maximum permitted RAM. At |
| 1292 | * the point this is called, nothing should have been |
| 1293 | * entered into the existing HPT */ |
| 1294 | spapr_reallocate_hpt(spapr, maxshift, &error_fatal); |
| 1295 | push_sregs_to_kvm_pr(spapr); |
| 1296 | } |
| 1297 | } |
| 1298 | |
| 1299 | /* NOTE: there are actually a number of ov5 bits where input from the |
| 1300 | * guest is always zero, and the platform/QEMU enables them independently |
| 1301 | * of guest input. To model these properly we'd want some sort of mask, |
| 1302 | * but since they only currently apply to memory migration as defined |
| 1303 | * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need |
| 1304 | * to worry about this for now. |
| 1305 | */ |
| 1306 | |
| 1307 | /* full range of negotiated ov5 capabilities */ |
| 1308 | spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); |
| 1309 | spapr_ovec_cleanup(ov5_guest); |
| 1310 | |
| 1311 | spapr_check_mmu_mode(guest_radix); |
| 1312 | |
| 1313 | spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); |
| 1314 | spapr_ovec_cleanup(ov1_guest); |
| 1315 | |
| 1316 | /* |
| 1317 | * Check for NUMA affinity conditions now that we know which NUMA |
| 1318 | * affinity the guest will use. |
| 1319 | */ |
| 1320 | spapr_numa_associativity_check(spapr); |
| 1321 | |
| 1322 | /* |
| 1323 | * Ensure the guest asks for an interrupt mode we support; |
| 1324 | * otherwise terminate the boot. |
| 1325 | */ |
| 1326 | if (guest_xive) { |
| 1327 | if (!spapr->irq->xive) { |
| 1328 | error_report( |
| 1329 | "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); |
| 1330 | exit(EXIT_FAILURE); |
| 1331 | } |
| 1332 | } else { |
| 1333 | if (!spapr->irq->xics) { |
| 1334 | error_report( |
| 1335 | "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); |
| 1336 | exit(EXIT_FAILURE); |
| 1337 | } |
| 1338 | } |
| 1339 | |
| 1340 | spapr_irq_update_active_intc(spapr); |
| 1341 | |
| 1342 | /* |
| 1343 | * Process all pending hot-plug/unplug requests now. An updated full |
| 1344 | * rendered FDT will be returned to the guest. |
| 1345 | */ |
| 1346 | spapr_drc_reset_all(spapr); |
| 1347 | spapr_clear_pending_hotplug_events(spapr); |
| 1348 | |
| 1349 | /* |
| 1350 | * If spapr_machine_reset() did not set up a HPT but one is necessary |
| 1351 | * (because the guest isn't going to use radix) then set it up here. |
| 1352 | */ |
| 1353 | if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { |
| 1354 | /* legacy hash or new hash: */ |
| 1355 | spapr_setup_hpt(spapr); |
| 1356 | } |
| 1357 | |
| 1358 | fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); |
| 1359 | g_free(spapr->fdt_blob); |
| 1360 | spapr->fdt_size = fdt_totalsize(fdt); |
| 1361 | spapr->fdt_initial_size = spapr->fdt_size; |
| 1362 | spapr->fdt_blob = fdt; |
| 1363 | |
| 1364 | /* |
| 1365 | * Set the machine->fdt pointer again since we just freed |
| 1366 | * it above (by freeing spapr->fdt_blob). We set this |
| 1367 | * pointer to enable support for the 'dumpdtb' QMP/HMP |
| 1368 | * command. |
| 1369 | */ |
| 1370 | MACHINE(spapr)->fdt = fdt; |
| 1371 | |
| 1372 | return H_SUCCESS; |
| 1373 | } |
| 1374 | |
| 1375 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu, |
| 1376 | SpaprMachineState *spapr, |
| 1377 | target_ulong opcode, |
| 1378 | target_ulong *args) |
| 1379 | { |
| 1380 | target_ulong vec = ppc64_phys_to_real(args[0]); |
| 1381 | target_ulong fdt_buf = args[1]; |
| 1382 | target_ulong fdt_bufsize = args[2]; |
| 1383 | target_ulong ret; |
| 1384 | SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; |
| 1385 | |
| 1386 | if (fdt_bufsize < sizeof(hdr)) { |
| 1387 | error_report("SLOF provided insufficient CAS buffer " |
| 1388 | TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); |
| 1389 | exit(EXIT_FAILURE); |
| 1390 | } |
| 1391 | |
| 1392 | fdt_bufsize -= sizeof(hdr); |
| 1393 | |
| 1394 | ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); |
| 1395 | if (ret == H_SUCCESS) { |
| 1396 | _FDT((fdt_pack(spapr->fdt_blob))); |
| 1397 | spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); |
| 1398 | spapr->fdt_initial_size = spapr->fdt_size; |
| 1399 | |
| 1400 | physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); |
| 1401 | physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, |
| 1402 | spapr->fdt_size); |
| 1403 | trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); |
| 1404 | } |
| 1405 | |
| 1406 | return ret; |
| 1407 | } |
| 1408 | |
| 1409 | target_ulong spapr_vof_client_architecture_support(MachineState *ms, |
| 1410 | CPUState *cs, |
| 1411 | target_ulong ovec_addr) |
| 1412 | { |
| 1413 | SpaprMachineState *spapr = SPAPR_MACHINE(ms); |
| 1414 | |
| 1415 | target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, |
| 1416 | ovec_addr, FDT_MAX_SIZE); |
| 1417 | |
| 1418 | /* |
| 1419 | * This adds stdout and generates phandles for boottime and CAS FDTs. |
| 1420 | * It is alright to update the FDT here as do_client_architecture_support() |
| 1421 | * does not pack it. |
| 1422 | */ |
| 1423 | spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); |
| 1424 | |
| 1425 | return ret; |
| 1426 | } |
| 1427 | |
| 1428 | static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, |
| 1429 | SpaprMachineState *spapr, |
| 1430 | target_ulong opcode, |
| 1431 | target_ulong *args) |
| 1432 | { |
| 1433 | uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & |
| 1434 | ~H_CPU_CHAR_THR_RECONF_TRIG; |
| 1435 | uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; |
| 1436 | uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); |
| 1437 | uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); |
| 1438 | uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); |
| 1439 | uint8_t count_cache_flush_assist = spapr_get_cap(spapr, |
| 1440 | SPAPR_CAP_CCF_ASSIST); |
| 1441 | |
| 1442 | switch (safe_cache) { |
| 1443 | case SPAPR_CAP_WORKAROUND: |
| 1444 | characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; |
| 1445 | characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; |
| 1446 | characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; |
| 1447 | behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; |
| 1448 | break; |
| 1449 | case SPAPR_CAP_FIXED: |
| 1450 | behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; |
| 1451 | behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; |
| 1452 | break; |
| 1453 | default: /* broken */ |
| 1454 | assert(safe_cache == SPAPR_CAP_BROKEN); |
| 1455 | behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; |
| 1456 | break; |
| 1457 | } |
| 1458 | |
| 1459 | switch (safe_bounds_check) { |
| 1460 | case SPAPR_CAP_WORKAROUND: |
| 1461 | characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; |
| 1462 | behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; |
| 1463 | break; |
| 1464 | case SPAPR_CAP_FIXED: |
| 1465 | break; |
| 1466 | default: /* broken */ |
| 1467 | assert(safe_bounds_check == SPAPR_CAP_BROKEN); |
| 1468 | behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; |
| 1469 | break; |
| 1470 | } |
| 1471 | |
| 1472 | switch (safe_indirect_branch) { |
| 1473 | case SPAPR_CAP_FIXED_NA: |
| 1474 | break; |
| 1475 | case SPAPR_CAP_FIXED_CCD: |
| 1476 | characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; |
| 1477 | break; |
| 1478 | case SPAPR_CAP_FIXED_IBS: |
| 1479 | characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; |
| 1480 | break; |
| 1481 | case SPAPR_CAP_WORKAROUND: |
| 1482 | behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; |
| 1483 | if (count_cache_flush_assist) { |
| 1484 | characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; |
| 1485 | } |
| 1486 | break; |
| 1487 | default: /* broken */ |
| 1488 | assert(safe_indirect_branch == SPAPR_CAP_BROKEN); |
| 1489 | break; |
| 1490 | } |
| 1491 | |
| 1492 | args[0] = characteristics; |
| 1493 | args[1] = behaviour; |
| 1494 | return H_SUCCESS; |
| 1495 | } |
| 1496 | |
| 1497 | static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 1498 | target_ulong opcode, target_ulong *args) |
| 1499 | { |
| 1500 | target_ulong dt = ppc64_phys_to_real(args[0]); |
| 1501 | struct fdt_header hdr = { 0 }; |
| 1502 | unsigned cb; |
| 1503 | void *fdt; |
| 1504 | |
| 1505 | physical_memory_read(dt, &hdr, sizeof(hdr)); |
| 1506 | cb = fdt32_to_cpu(hdr.totalsize); |
| 1507 | |
| 1508 | /* Check that the fdt did not grow out of proportion */ |
| 1509 | if (cb > spapr->fdt_initial_size * 2) { |
| 1510 | trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, |
| 1511 | fdt32_to_cpu(hdr.magic)); |
| 1512 | return H_PARAMETER; |
| 1513 | } |
| 1514 | |
| 1515 | fdt = g_malloc0(cb); |
| 1516 | physical_memory_read(dt, fdt, cb); |
| 1517 | |
| 1518 | /* Check the fdt consistency */ |
| 1519 | if (fdt_check_full(fdt, cb)) { |
| 1520 | trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, |
| 1521 | fdt32_to_cpu(hdr.magic)); |
| 1522 | return H_PARAMETER; |
| 1523 | } |
| 1524 | |
| 1525 | g_free(spapr->fdt_blob); |
| 1526 | spapr->fdt_size = cb; |
| 1527 | spapr->fdt_blob = fdt; |
| 1528 | trace_spapr_update_dt(cb); |
| 1529 | |
| 1530 | return H_SUCCESS; |
| 1531 | } |
| 1532 | |
| 1533 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
| 1534 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; |
| 1535 | static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; |
| 1536 | |
| 1537 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) |
| 1538 | { |
| 1539 | spapr_hcall_fn *slot; |
| 1540 | |
| 1541 | if (opcode <= MAX_HCALL_OPCODE) { |
| 1542 | assert((opcode & 0x3) == 0); |
| 1543 | |
| 1544 | slot = &papr_hypercall_table[opcode / 4]; |
| 1545 | } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { |
| 1546 | /* we only have SVM-related hcall numbers assigned in multiples of 4 */ |
| 1547 | assert((opcode & 0x3) == 0); |
| 1548 | |
| 1549 | slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; |
| 1550 | } else { |
| 1551 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
| 1552 | |
| 1553 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 1554 | } |
| 1555 | |
| 1556 | assert(!(*slot)); |
| 1557 | *slot = fn; |
| 1558 | } |
| 1559 | |
| 1560 | void spapr_unregister_hypercall(target_ulong opcode) |
| 1561 | { |
| 1562 | spapr_hcall_fn *slot; |
| 1563 | |
| 1564 | if (opcode <= MAX_HCALL_OPCODE) { |
| 1565 | assert((opcode & 0x3) == 0); |
| 1566 | |
| 1567 | slot = &papr_hypercall_table[opcode / 4]; |
| 1568 | } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { |
| 1569 | /* we only have SVM-related hcall numbers assigned in multiples of 4 */ |
| 1570 | assert((opcode & 0x3) == 0); |
| 1571 | |
| 1572 | slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; |
| 1573 | } else { |
| 1574 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
| 1575 | |
| 1576 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 1577 | } |
| 1578 | |
| 1579 | *slot = NULL; |
| 1580 | } |
| 1581 | |
| 1582 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
| 1583 | target_ulong *args) |
| 1584 | { |
| 1585 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 1586 | |
| 1587 | if ((opcode <= MAX_HCALL_OPCODE) |
| 1588 | && ((opcode & 0x3) == 0)) { |
| 1589 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
| 1590 | |
| 1591 | if (fn) { |
| 1592 | return fn(cpu, spapr, opcode, args); |
| 1593 | } |
| 1594 | } else if ((opcode >= SVM_HCALL_BASE) && |
| 1595 | (opcode <= SVM_HCALL_MAX)) { |
| 1596 | spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; |
| 1597 | |
| 1598 | if (fn) { |
| 1599 | return fn(cpu, spapr, opcode, args); |
| 1600 | } |
| 1601 | } else if ((opcode >= KVMPPC_HCALL_BASE) && |
| 1602 | (opcode <= KVMPPC_HCALL_MAX)) { |
| 1603 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 1604 | |
| 1605 | if (fn) { |
| 1606 | return fn(cpu, spapr, opcode, args); |
| 1607 | } |
| 1608 | } |
| 1609 | |
| 1610 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
| 1611 | opcode); |
| 1612 | return H_FUNCTION; |
| 1613 | } |
| 1614 | |
| 1615 | #ifdef CONFIG_TCG |
| 1616 | static void hypercall_register_softmmu(void) |
| 1617 | { |
| 1618 | /* DO NOTHING */ |
| 1619 | } |
| 1620 | #else |
| 1621 | static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 1622 | target_ulong opcode, target_ulong *args) |
| 1623 | { |
| 1624 | g_assert_not_reached(); |
| 1625 | } |
| 1626 | |
| 1627 | static void hypercall_register_softmmu(void) |
| 1628 | { |
| 1629 | /* hcall-pft */ |
| 1630 | spapr_register_hypercall(H_ENTER, h_softmmu); |
| 1631 | spapr_register_hypercall(H_REMOVE, h_softmmu); |
| 1632 | spapr_register_hypercall(H_PROTECT, h_softmmu); |
| 1633 | spapr_register_hypercall(H_READ, h_softmmu); |
| 1634 | |
| 1635 | /* hcall-bulk */ |
| 1636 | spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); |
| 1637 | } |
| 1638 | #endif |
| 1639 | |
| 1640 | static void hypercall_register_types(void) |
| 1641 | { |
| 1642 | hypercall_register_softmmu(); |
| 1643 | |
| 1644 | /* hcall-hpt-resize */ |
| 1645 | spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); |
| 1646 | spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); |
| 1647 | |
| 1648 | /* hcall-splpar */ |
| 1649 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); |
| 1650 | spapr_register_hypercall(H_CEDE, h_cede); |
| 1651 | spapr_register_hypercall(H_CONFER, h_confer); |
| 1652 | spapr_register_hypercall(H_PROD, h_prod); |
| 1653 | |
| 1654 | /* hcall-join */ |
| 1655 | spapr_register_hypercall(H_JOIN, h_join); |
| 1656 | |
| 1657 | spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); |
| 1658 | |
| 1659 | /* processor register resource access h-calls */ |
| 1660 | spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); |
| 1661 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
| 1662 | spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); |
| 1663 | spapr_register_hypercall(H_PAGE_INIT, h_page_init); |
| 1664 | spapr_register_hypercall(H_SET_MODE, h_set_mode); |
| 1665 | |
| 1666 | /* In Memory Table MMU h-calls */ |
| 1667 | spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); |
| 1668 | spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); |
| 1669 | spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); |
| 1670 | |
| 1671 | /* hcall-get-cpu-characteristics */ |
| 1672 | spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, |
| 1673 | h_get_cpu_characteristics); |
| 1674 | |
| 1675 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate |
| 1676 | * here between the "CI" and the "CACHE" variants, they will use whatever |
| 1677 | * mapping attributes qemu is using. When using KVM, the kernel will |
| 1678 | * enforce the attributes more strongly |
| 1679 | */ |
| 1680 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); |
| 1681 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); |
| 1682 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); |
| 1683 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); |
| 1684 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); |
| 1685 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); |
| 1686 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
| 1687 | |
| 1688 | /* qemu/KVM-PPC specific hcalls */ |
| 1689 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); |
| 1690 | |
| 1691 | /* ibm,client-architecture-support support */ |
| 1692 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); |
| 1693 | |
| 1694 | spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); |
| 1695 | } |
| 1696 | |
| 1697 | type_init(hypercall_register_types) |