| 1 | /* |
| 2 | * QEMU PowerPC sPAPR IRQ interface |
| 3 | * |
| 4 | * Copyright (c) 2018, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qemu/log.h" |
| 12 | #include "qemu/error-report.h" |
| 13 | #include "qapi/error.h" |
| 14 | #include "hw/core/irq.h" |
| 15 | #include "hw/ppc/spapr.h" |
| 16 | #include "hw/ppc/spapr_cpu_core.h" |
| 17 | #include "hw/ppc/spapr_xive.h" |
| 18 | #include "hw/ppc/xics.h" |
| 19 | #include "hw/ppc/xics_spapr.h" |
| 20 | #include "hw/core/qdev-properties.h" |
| 21 | #include "cpu-models.h" |
| 22 | #include "system/kvm.h" |
| 23 | |
| 24 | #include "trace.h" |
| 25 | |
| 26 | QEMU_BUILD_BUG_ON(SPAPR_IRQ_NR_IPIS > SPAPR_XIRQ_BASE); |
| 27 | |
| 28 | static const TypeInfo spapr_intc_info = { |
| 29 | .name = TYPE_SPAPR_INTC, |
| 30 | .parent = TYPE_INTERFACE, |
| 31 | .class_size = sizeof(SpaprInterruptControllerClass), |
| 32 | }; |
| 33 | |
| 34 | static void spapr_irq_msi_init(SpaprMachineState *spapr) |
| 35 | { |
| 36 | spapr->irq_map_nr = SPAPR_IRQ_NR_MSIS; |
| 37 | spapr->irq_map = bitmap_new(spapr->irq_map_nr); |
| 38 | } |
| 39 | |
| 40 | int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, |
| 41 | Error **errp) |
| 42 | { |
| 43 | int irq; |
| 44 | |
| 45 | /* |
| 46 | * The 'align_mask' parameter of bitmap_find_next_zero_area() |
| 47 | * should be one less than a power of 2; 0 means no |
| 48 | * alignment. Adapt the 'align' value of the former allocator |
| 49 | * to fit the requirements of bitmap_find_next_zero_area() |
| 50 | */ |
| 51 | align -= 1; |
| 52 | |
| 53 | irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num, |
| 54 | align); |
| 55 | if (irq == spapr->irq_map_nr) { |
| 56 | error_setg(errp, "can't find a free %d-IRQ block", num); |
| 57 | return -1; |
| 58 | } |
| 59 | |
| 60 | bitmap_set(spapr->irq_map, irq, num); |
| 61 | |
| 62 | return irq + SPAPR_IRQ_MSI; |
| 63 | } |
| 64 | |
| 65 | void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num) |
| 66 | { |
| 67 | bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); |
| 68 | } |
| 69 | |
| 70 | int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn, |
| 71 | SpaprInterruptController *intc, |
| 72 | uint32_t nr_servers, |
| 73 | Error **errp) |
| 74 | { |
| 75 | Error *local_err = NULL; |
| 76 | |
| 77 | if (kvm_enabled() && kvm_kernel_irqchip_allowed()) { |
| 78 | if (fn(intc, nr_servers, &local_err) < 0) { |
| 79 | if (kvm_kernel_irqchip_required()) { |
| 80 | error_prepend(&local_err, |
| 81 | "kernel_irqchip requested but unavailable: "); |
| 82 | error_propagate(errp, local_err); |
| 83 | return -1; |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * We failed to initialize the KVM device, fallback to |
| 88 | * emulated mode |
| 89 | */ |
| 90 | error_prepend(&local_err, |
| 91 | "kernel_irqchip allowed but unavailable: "); |
| 92 | error_append_hint(&local_err, |
| 93 | "Falling back to kernel-irqchip=off\n"); |
| 94 | warn_report_err(local_err); |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | /* |
| 102 | * XICS IRQ backend. |
| 103 | */ |
| 104 | |
| 105 | SpaprIrq spapr_irq_xics = { |
| 106 | .xics = true, |
| 107 | .xive = false, |
| 108 | }; |
| 109 | |
| 110 | /* |
| 111 | * XIVE IRQ backend. |
| 112 | */ |
| 113 | |
| 114 | SpaprIrq spapr_irq_xive = { |
| 115 | .xics = false, |
| 116 | .xive = true, |
| 117 | }; |
| 118 | |
| 119 | /* |
| 120 | * Dual XIVE and XICS IRQ backend. |
| 121 | * |
| 122 | * Both interrupt mode, XIVE and XICS, objects are created but the |
| 123 | * machine starts in legacy interrupt mode (XICS). It can be changed |
| 124 | * by the CAS negotiation process and, in that case, the new mode is |
| 125 | * activated after an extra machine reset. |
| 126 | */ |
| 127 | |
| 128 | /* |
| 129 | * Define values in sync with the XIVE and XICS backend |
| 130 | */ |
| 131 | SpaprIrq spapr_irq_dual = { |
| 132 | .xics = true, |
| 133 | .xive = true, |
| 134 | }; |
| 135 | |
| 136 | |
| 137 | static int spapr_irq_check(SpaprMachineState *spapr, Error **errp) |
| 138 | { |
| 139 | ERRP_GUARD(); |
| 140 | MachineState *machine = MACHINE(spapr); |
| 141 | |
| 142 | /* |
| 143 | * Sanity checks on non-P9 machines. On these, XIVE is not |
| 144 | * advertised, see spapr_dt_ov5_platform_support() |
| 145 | */ |
| 146 | if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, |
| 147 | 0, spapr->max_compat_pvr)) { |
| 148 | /* |
| 149 | * If the 'dual' interrupt mode is selected, force XICS as CAS |
| 150 | * negotiation is useless. |
| 151 | */ |
| 152 | if (spapr->irq == &spapr_irq_dual) { |
| 153 | spapr->irq = &spapr_irq_xics; |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Non-P9 machines using only XIVE is a bogus setup. We have two |
| 159 | * scenarios to take into account because of the compat mode: |
| 160 | * |
| 161 | * 1. POWER7/8 machines should fail to init later on when creating |
| 162 | * the XIVE interrupt presenters because a POWER9 exception |
| 163 | * model is required. |
| 164 | |
| 165 | * 2. POWER9 machines using the POWER8 compat mode won't fail and |
| 166 | * will let the OS boot with a partial XIVE setup : DT |
| 167 | * properties but no hcalls. |
| 168 | * |
| 169 | * To cover both and not confuse the OS, add an early failure in |
| 170 | * QEMU. |
| 171 | */ |
| 172 | if (!spapr->irq->xics) { |
| 173 | error_setg(errp, "XIVE-only machines require a POWER9 CPU"); |
| 174 | return -1; |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | /* |
| 179 | * On a POWER9 host, some older KVM XICS devices cannot be destroyed and |
| 180 | * re-created. Same happens with KVM nested guests. Detect that early to |
| 181 | * avoid QEMU to exit later when the guest reboots. |
| 182 | */ |
| 183 | if (kvm_enabled() && |
| 184 | spapr->irq == &spapr_irq_dual && |
| 185 | kvm_kernel_irqchip_required() && |
| 186 | xics_kvm_has_broken_disconnect()) { |
| 187 | error_setg(errp, |
| 188 | "KVM is incompatible with ic-mode=dual,kernel-irqchip=on"); |
| 189 | error_append_hint(errp, |
| 190 | "This can happen with an old KVM or in a KVM nested guest.\n"); |
| 191 | error_append_hint(errp, |
| 192 | "Try without kernel-irqchip or with kernel-irqchip=off.\n"); |
| 193 | return -1; |
| 194 | } |
| 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * sPAPR IRQ frontend routines for devices |
| 201 | */ |
| 202 | #define ALL_INTCS(spapr_) \ |
| 203 | { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), } |
| 204 | |
| 205 | int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, |
| 206 | PowerPCCPU *cpu, Error **errp) |
| 207 | { |
| 208 | SpaprInterruptController *intcs[] = ALL_INTCS(spapr); |
| 209 | int i; |
| 210 | int rc; |
| 211 | |
| 212 | for (i = 0; i < ARRAY_SIZE(intcs); i++) { |
| 213 | SpaprInterruptController *intc = intcs[i]; |
| 214 | if (intc) { |
| 215 | SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); |
| 216 | rc = sicc->cpu_intc_create(intc, cpu, errp); |
| 217 | if (rc < 0) { |
| 218 | return rc; |
| 219 | } |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu) |
| 227 | { |
| 228 | SpaprInterruptController *intcs[] = ALL_INTCS(spapr); |
| 229 | int i; |
| 230 | |
| 231 | for (i = 0; i < ARRAY_SIZE(intcs); i++) { |
| 232 | SpaprInterruptController *intc = intcs[i]; |
| 233 | if (intc) { |
| 234 | SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); |
| 235 | sicc->cpu_intc_reset(intc, cpu); |
| 236 | } |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu) |
| 241 | { |
| 242 | SpaprInterruptController *intcs[] = ALL_INTCS(spapr); |
| 243 | int i; |
| 244 | |
| 245 | for (i = 0; i < ARRAY_SIZE(intcs); i++) { |
| 246 | SpaprInterruptController *intc = intcs[i]; |
| 247 | if (intc) { |
| 248 | SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); |
| 249 | sicc->cpu_intc_destroy(intc, cpu); |
| 250 | } |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | static void spapr_set_irq(void *opaque, int irq, int level) |
| 255 | { |
| 256 | SpaprMachineState *spapr = SPAPR_MACHINE(opaque); |
| 257 | SpaprInterruptControllerClass *sicc |
| 258 | = SPAPR_INTC_GET_CLASS(spapr->active_intc); |
| 259 | |
| 260 | sicc->set_irq(spapr->active_intc, irq, level); |
| 261 | } |
| 262 | |
| 263 | void spapr_irq_print_info(SpaprMachineState *spapr, GString *buf) |
| 264 | { |
| 265 | SpaprInterruptControllerClass *sicc |
| 266 | = SPAPR_INTC_GET_CLASS(spapr->active_intc); |
| 267 | |
| 268 | sicc->print_info(spapr->active_intc, buf); |
| 269 | } |
| 270 | |
| 271 | void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, |
| 272 | void *fdt, uint32_t phandle) |
| 273 | { |
| 274 | SpaprInterruptControllerClass *sicc |
| 275 | = SPAPR_INTC_GET_CLASS(spapr->active_intc); |
| 276 | |
| 277 | sicc->dt(spapr->active_intc, nr_servers, fdt, phandle); |
| 278 | } |
| 279 | |
| 280 | void spapr_irq_init(SpaprMachineState *spapr, Error **errp) |
| 281 | { |
| 282 | if (kvm_enabled() && kvm_kernel_irqchip_split()) { |
| 283 | error_setg(errp, "kernel_irqchip split mode not supported on pseries"); |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | if (spapr_irq_check(spapr, errp) < 0) { |
| 288 | return; |
| 289 | } |
| 290 | |
| 291 | /* Initialize the MSI IRQ allocator. */ |
| 292 | spapr_irq_msi_init(spapr); |
| 293 | |
| 294 | if (spapr->irq->xics) { |
| 295 | Object *obj; |
| 296 | |
| 297 | obj = object_new(TYPE_ICS_SPAPR); |
| 298 | |
| 299 | object_property_add_child(OBJECT(spapr), "ics", obj); |
| 300 | object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
| 301 | &error_abort); |
| 302 | object_property_set_int(obj, "nr-irqs", SPAPR_NR_XIRQS, &error_abort); |
| 303 | if (!qdev_realize(DEVICE(obj), NULL, errp)) { |
| 304 | return; |
| 305 | } |
| 306 | |
| 307 | spapr->ics = ICS_SPAPR(obj); |
| 308 | } |
| 309 | |
| 310 | if (spapr->irq->xive) { |
| 311 | uint32_t nr_servers = spapr_max_server_number(spapr); |
| 312 | DeviceState *dev; |
| 313 | int i; |
| 314 | |
| 315 | dev = qdev_new(TYPE_SPAPR_XIVE); |
| 316 | qdev_prop_set_uint32(dev, "nr-irqs", SPAPR_NR_XIRQS + SPAPR_IRQ_NR_IPIS); |
| 317 | /* |
| 318 | * 8 XIVE END structures per CPU. One for each available |
| 319 | * priority |
| 320 | */ |
| 321 | qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); |
| 322 | object_property_set_link(OBJECT(dev), "xive-fabric", OBJECT(spapr), |
| 323 | &error_abort); |
| 324 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 325 | |
| 326 | spapr->xive = SPAPR_XIVE(dev); |
| 327 | |
| 328 | /* Enable the CPU IPIs */ |
| 329 | for (i = 0; i < nr_servers; ++i) { |
| 330 | SpaprInterruptControllerClass *sicc |
| 331 | = SPAPR_INTC_GET_CLASS(spapr->xive); |
| 332 | |
| 333 | if (sicc->claim_irq(SPAPR_INTC(spapr->xive), SPAPR_IRQ_IPI + i, |
| 334 | false, errp) < 0) { |
| 335 | return; |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | spapr_xive_hcall_init(spapr); |
| 340 | } |
| 341 | |
| 342 | spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr, |
| 343 | SPAPR_NR_XIRQS + SPAPR_IRQ_NR_IPIS); |
| 344 | |
| 345 | /* |
| 346 | * Mostly we don't actually need this until reset, except that not |
| 347 | * having this set up can cause VFIO devices to issue a |
| 348 | * false-positive warning during realize(), because they don't yet |
| 349 | * have an in-kernel irq chip. |
| 350 | */ |
| 351 | spapr_irq_update_active_intc(spapr); |
| 352 | } |
| 353 | |
| 354 | int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp) |
| 355 | { |
| 356 | SpaprInterruptController *intcs[] = ALL_INTCS(spapr); |
| 357 | int i; |
| 358 | int rc; |
| 359 | |
| 360 | assert(irq >= SPAPR_XIRQ_BASE); |
| 361 | assert(irq < (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); |
| 362 | |
| 363 | for (i = 0; i < ARRAY_SIZE(intcs); i++) { |
| 364 | SpaprInterruptController *intc = intcs[i]; |
| 365 | if (intc) { |
| 366 | SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc); |
| 367 | rc = sicc->claim_irq(intc, irq, lsi, errp); |
| 368 | if (rc < 0) { |
| 369 | return rc; |
| 370 | } |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) |
| 378 | { |
| 379 | SpaprInterruptController *intcs[] = ALL_INTCS(spapr); |
| 380 | int i, j; |
| 381 | |
| 382 | assert(irq >= SPAPR_XIRQ_BASE); |
| 383 | assert((irq + num) <= (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); |
| 384 | |
| 385 | for (i = irq; i < (irq + num); i++) { |
| 386 | for (j = 0; j < ARRAY_SIZE(intcs); j++) { |
| 387 | SpaprInterruptController *intc = intcs[j]; |
| 388 | |
| 389 | if (intc) { |
| 390 | SpaprInterruptControllerClass *sicc |
| 391 | = SPAPR_INTC_GET_CLASS(intc); |
| 392 | sicc->free_irq(intc, i); |
| 393 | } |
| 394 | } |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) |
| 399 | { |
| 400 | /* |
| 401 | * This interface is basically for VIO and PHB devices to find the |
| 402 | * right qemu_irq to manipulate, so we only allow access to the |
| 403 | * external irqs for now. Currently anything which needs to |
| 404 | * access the IPIs most naturally gets there via the guest side |
| 405 | * interfaces, we can change this if we need to in future. |
| 406 | */ |
| 407 | assert(irq >= SPAPR_XIRQ_BASE); |
| 408 | assert(irq < (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); |
| 409 | |
| 410 | if (spapr->ics) { |
| 411 | assert(ics_valid_irq(spapr->ics, irq)); |
| 412 | } |
| 413 | if (spapr->xive) { |
| 414 | assert(irq < spapr->xive->nr_irqs); |
| 415 | assert(xive_eas_is_valid(&spapr->xive->eat[irq])); |
| 416 | } |
| 417 | |
| 418 | return spapr->qirqs[irq]; |
| 419 | } |
| 420 | |
| 421 | int spapr_irq_post_load(SpaprMachineState *spapr, int version_id) |
| 422 | { |
| 423 | SpaprInterruptControllerClass *sicc; |
| 424 | |
| 425 | spapr_irq_update_active_intc(spapr); |
| 426 | sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc); |
| 427 | return sicc->post_load(spapr->active_intc, version_id); |
| 428 | } |
| 429 | |
| 430 | void spapr_irq_reset(SpaprMachineState *spapr, Error **errp) |
| 431 | { |
| 432 | assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_nr)); |
| 433 | |
| 434 | spapr_irq_update_active_intc(spapr); |
| 435 | } |
| 436 | |
| 437 | int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp) |
| 438 | { |
| 439 | const char *nodename = "interrupt-controller"; |
| 440 | int offset, phandle; |
| 441 | |
| 442 | offset = fdt_subnode_offset(fdt, 0, nodename); |
| 443 | if (offset < 0) { |
| 444 | error_setg(errp, "Can't find node \"%s\": %s", |
| 445 | nodename, fdt_strerror(offset)); |
| 446 | return -1; |
| 447 | } |
| 448 | |
| 449 | phandle = fdt_get_phandle(fdt, offset); |
| 450 | if (!phandle) { |
| 451 | error_setg(errp, "Can't get phandle of node \"%s\"", nodename); |
| 452 | return -1; |
| 453 | } |
| 454 | |
| 455 | return phandle; |
| 456 | } |
| 457 | |
| 458 | static void set_active_intc(SpaprMachineState *spapr, |
| 459 | SpaprInterruptController *new_intc) |
| 460 | { |
| 461 | SpaprInterruptControllerClass *sicc; |
| 462 | uint32_t nr_servers = spapr_max_server_number(spapr); |
| 463 | |
| 464 | assert(new_intc); |
| 465 | |
| 466 | if (new_intc == spapr->active_intc) { |
| 467 | /* Nothing to do */ |
| 468 | return; |
| 469 | } |
| 470 | |
| 471 | if (spapr->active_intc) { |
| 472 | sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc); |
| 473 | if (sicc->deactivate) { |
| 474 | sicc->deactivate(spapr->active_intc); |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | sicc = SPAPR_INTC_GET_CLASS(new_intc); |
| 479 | if (sicc->activate) { |
| 480 | sicc->activate(new_intc, nr_servers, &error_fatal); |
| 481 | } |
| 482 | |
| 483 | spapr->active_intc = new_intc; |
| 484 | |
| 485 | /* |
| 486 | * We've changed the kernel irqchip, let VFIO devices know they |
| 487 | * need to readjust. |
| 488 | */ |
| 489 | kvm_irqchip_change_notify(); |
| 490 | } |
| 491 | |
| 492 | void spapr_irq_update_active_intc(SpaprMachineState *spapr) |
| 493 | { |
| 494 | SpaprInterruptController *new_intc; |
| 495 | |
| 496 | if (!spapr->ics) { |
| 497 | /* |
| 498 | * XXX before we run CAS, ov5_cas is initialized empty, which |
| 499 | * indicates XICS, even if we have ic-mode=xive. TODO: clean |
| 500 | * up the CAS path so that we have a clearer way of handling |
| 501 | * this. |
| 502 | */ |
| 503 | new_intc = SPAPR_INTC(spapr->xive); |
| 504 | } else if (spapr->ov5_cas |
| 505 | && spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { |
| 506 | new_intc = SPAPR_INTC(spapr->xive); |
| 507 | } else { |
| 508 | new_intc = SPAPR_INTC(spapr->ics); |
| 509 | } |
| 510 | |
| 511 | set_active_intc(spapr, new_intc); |
| 512 | } |
| 513 | |
| 514 | /* |
| 515 | * XICS legacy routines - to deprecate one day |
| 516 | */ |
| 517 | |
| 518 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) |
| 519 | { |
| 520 | int first, i; |
| 521 | |
| 522 | for (first = 0; first < ics->nr_irqs; first += alignnum) { |
| 523 | if (num > (ics->nr_irqs - first)) { |
| 524 | return -1; |
| 525 | } |
| 526 | for (i = first; i < first + num; ++i) { |
| 527 | if (!ics_irq_free(ics, i)) { |
| 528 | break; |
| 529 | } |
| 530 | } |
| 531 | if (i == (first + num)) { |
| 532 | return first; |
| 533 | } |
| 534 | } |
| 535 | |
| 536 | return -1; |
| 537 | } |
| 538 | |
| 539 | int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp) |
| 540 | { |
| 541 | ICSState *ics = spapr->ics; |
| 542 | int first = -1; |
| 543 | |
| 544 | assert(ics); |
| 545 | |
| 546 | /* |
| 547 | * MSIMesage::data is used for storing VIRQ so |
| 548 | * it has to be aligned to num to support multiple |
| 549 | * MSI vectors. MSI-X is not affected by this. |
| 550 | * The hint is used for the first IRQ, the rest should |
| 551 | * be allocated continuously. |
| 552 | */ |
| 553 | if (align) { |
| 554 | assert((num == 1) || (num == 2) || (num == 4) || |
| 555 | (num == 8) || (num == 16) || (num == 32)); |
| 556 | first = ics_find_free_block(ics, num, num); |
| 557 | } else { |
| 558 | first = ics_find_free_block(ics, num, 1); |
| 559 | } |
| 560 | |
| 561 | if (first < 0) { |
| 562 | error_setg(errp, "can't find a free %d-IRQ block", num); |
| 563 | return -1; |
| 564 | } |
| 565 | |
| 566 | return first + ics->offset; |
| 567 | } |
| 568 | |
| 569 | static void spapr_irq_register_types(void) |
| 570 | { |
| 571 | type_register_static(&spapr_intc_info); |
| 572 | } |
| 573 | |
| 574 | type_init(spapr_irq_register_types) |